stm32f7/stm32f779/
i2c1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    oar1: OAR1,
8    oar2: OAR2,
9    timingr: TIMINGR,
10    timeoutr: TIMEOUTR,
11    isr: ISR,
12    icr: ICR,
13    pecr: PECR,
14    rxdr: RXDR,
15    txdr: TXDR,
16}
17impl RegisterBlock {
18    ///0x00 - Control register 1
19    #[inline(always)]
20    pub const fn cr1(&self) -> &CR1 {
21        &self.cr1
22    }
23    ///0x04 - Control register 2
24    #[inline(always)]
25    pub const fn cr2(&self) -> &CR2 {
26        &self.cr2
27    }
28    ///0x08 - Own address register 1
29    #[inline(always)]
30    pub const fn oar1(&self) -> &OAR1 {
31        &self.oar1
32    }
33    ///0x0c - Own address register 2
34    #[inline(always)]
35    pub const fn oar2(&self) -> &OAR2 {
36        &self.oar2
37    }
38    ///0x10 - Timing register
39    #[inline(always)]
40    pub const fn timingr(&self) -> &TIMINGR {
41        &self.timingr
42    }
43    ///0x14 - Status register 1
44    #[inline(always)]
45    pub const fn timeoutr(&self) -> &TIMEOUTR {
46        &self.timeoutr
47    }
48    ///0x18 - Interrupt and Status register
49    #[inline(always)]
50    pub const fn isr(&self) -> &ISR {
51        &self.isr
52    }
53    ///0x1c - Interrupt clear register
54    #[inline(always)]
55    pub const fn icr(&self) -> &ICR {
56        &self.icr
57    }
58    ///0x20 - PEC register
59    #[inline(always)]
60    pub const fn pecr(&self) -> &PECR {
61        &self.pecr
62    }
63    ///0x24 - Receive data register
64    #[inline(always)]
65    pub const fn rxdr(&self) -> &RXDR {
66        &self.rxdr
67    }
68    ///0x28 - Transmit data register
69    #[inline(always)]
70    pub const fn txdr(&self) -> &TXDR {
71        &self.txdr
72    }
73}
74/**CR1 (rw) register accessor: Control register 1
75
76You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
77
78See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:CR1)
79
80For information about available fields see [`mod@cr1`] module*/
81pub type CR1 = crate::Reg<cr1::CR1rs>;
82///Control register 1
83pub mod cr1;
84/**CR2 (rw) register accessor: Control register 2
85
86You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
87
88See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:CR2)
89
90For information about available fields see [`mod@cr2`] module*/
91pub type CR2 = crate::Reg<cr2::CR2rs>;
92///Control register 2
93pub mod cr2;
94/**OAR1 (rw) register accessor: Own address register 1
95
96You can [`read`](crate::Reg::read) this register and get [`oar1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
97
98See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:OAR1)
99
100For information about available fields see [`mod@oar1`] module*/
101pub type OAR1 = crate::Reg<oar1::OAR1rs>;
102///Own address register 1
103pub mod oar1;
104/**OAR2 (rw) register accessor: Own address register 2
105
106You can [`read`](crate::Reg::read) this register and get [`oar2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
107
108See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:OAR2)
109
110For information about available fields see [`mod@oar2`] module*/
111pub type OAR2 = crate::Reg<oar2::OAR2rs>;
112///Own address register 2
113pub mod oar2;
114/**TIMINGR (rw) register accessor: Timing register
115
116You can [`read`](crate::Reg::read) this register and get [`timingr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timingr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
117
118See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:TIMINGR)
119
120For information about available fields see [`mod@timingr`] module*/
121pub type TIMINGR = crate::Reg<timingr::TIMINGRrs>;
122///Timing register
123pub mod timingr;
124/**TIMEOUTR (rw) register accessor: Status register 1
125
126You can [`read`](crate::Reg::read) this register and get [`timeoutr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timeoutr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
127
128See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:TIMEOUTR)
129
130For information about available fields see [`mod@timeoutr`] module*/
131pub type TIMEOUTR = crate::Reg<timeoutr::TIMEOUTRrs>;
132///Status register 1
133pub mod timeoutr;
134/**ISR (rw) register accessor: Interrupt and Status register
135
136You can [`read`](crate::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
137
138See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:ISR)
139
140For information about available fields see [`mod@isr`] module*/
141pub type ISR = crate::Reg<isr::ISRrs>;
142///Interrupt and Status register
143pub mod isr;
144/**ICR (w) register accessor: Interrupt clear register
145
146You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
147
148See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:ICR)
149
150For information about available fields see [`mod@icr`] module*/
151pub type ICR = crate::Reg<icr::ICRrs>;
152///Interrupt clear register
153pub mod icr;
154/**PECR (r) register accessor: PEC register
155
156You can [`read`](crate::Reg::read) this register and get [`pecr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
157
158See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:PECR)
159
160For information about available fields see [`mod@pecr`] module*/
161pub type PECR = crate::Reg<pecr::PECRrs>;
162///PEC register
163pub mod pecr;
164/**RXDR (r) register accessor: Receive data register
165
166You can [`read`](crate::Reg::read) this register and get [`rxdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:RXDR)
169
170For information about available fields see [`mod@rxdr`] module*/
171pub type RXDR = crate::Reg<rxdr::RXDRrs>;
172///Receive data register
173pub mod rxdr;
174/**TXDR (rw) register accessor: Transmit data register
175
176You can [`read`](crate::Reg::read) this register and get [`txdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
177
178See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#I2C1:TXDR)
179
180For information about available fields see [`mod@txdr`] module*/
181pub type TXDR = crate::Reg<txdr::TXDRrs>;
182///Transmit data register
183pub mod txdr;
stm32f7/stm32f779/i2c1.rs

stm32f7/stm32f779/
i2c1.rs
