stm32f7/stm32f779/dsi.rs
1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5 vr: VR,
6 cr: CR,
7 ccr: CCR,
8 lvcidr: LVCIDR,
9 lcolcr: LCOLCR,
10 lpcr: LPCR,
11 lpmcr: LPMCR,
12 _reserved7: [u8; 0x10],
13 pcr: PCR,
14 gvcidr: GVCIDR,
15 mcr: MCR,
16 vmcr: VMCR,
17 vpcr: VPCR,
18 vccr: VCCR,
19 vnpcr: VNPCR,
20 vhsacr: VHSACR,
21 vhbpcr: VHBPCR,
22 vlcr: VLCR,
23 vvsacr: VVSACR,
24 vvbpcr: VVBPCR,
25 vvfpcr: VVFPCR,
26 vvacr: VVACR,
27 lccr: LCCR,
28 cmcr: CMCR,
29 ghcr: GHCR,
30 gpdr: GPDR,
31 gpsr: GPSR,
32 tccr0: TCCR0,
33 tccr1: TCCR1,
34 tccr2: TCCR2,
35 tccr3: TCCR3,
36 tccr4: TCCR4,
37 tccr5: TCCR5,
38 _reserved32: [u8; 0x04],
39 clcr: CLCR,
40 cltcr: CLTCR,
41 dltcr: DLTCR,
42 pctlr: PCTLR,
43 pconfr: PCONFR,
44 pucr: PUCR,
45 pttcr: PTTCR,
46 psr: PSR,
47 _reserved40: [u8; 0x08],
48 isr0: ISR0,
49 isr1: ISR1,
50 ier0: IER0,
51 ier1: IER1,
52 _reserved44: [u8; 0x0c],
53 fir0: FIR0,
54 fir1: FIR1,
55 _reserved46: [u8; 0x20],
56 vscr: VSCR,
57 _reserved47: [u8; 0x08],
58 lcvcidr: LCVCIDR,
59 lcccr: LCCCR,
60 _reserved49: [u8; 0x04],
61 lpmccr: LPMCCR,
62 _reserved50: [u8; 0x1c],
63 vmccr: VMCCR,
64 vpccr: VPCCR,
65 vcccr: VCCCR,
66 vnpccr: VNPCCR,
67 vhsaccr: VHSACCR,
68 vhbpccr: VHBPCCR,
69 vlccr: VLCCR,
70 vvsaccr: VVSACCR,
71 vvbpccr: VVBPCCR,
72 vvfpccr: VVFPCCR,
73 vvaccr: VVACCR,
74 _reserved61: [u8; 0x029c],
75 wcfgr: WCFGR,
76 wcr: WCR,
77 wier: WIER,
78 wisr: WISR,
79 wifcr: WIFCR,
80 _reserved66: [u8; 0x04],
81 wpcr0: WPCR0,
82 wpcr1: WPCR1,
83 wpcr2: WPCR2,
84 wpcr3: WPCR3,
85 wpcr4: WPCR4,
86 _reserved71: [u8; 0x04],
87 wrpcr: WRPCR,
88}
89impl RegisterBlock {
90 ///0x00 - DSI Host Version Register
91 #[inline(always)]
92 pub const fn vr(&self) -> &VR {
93 &self.vr
94 }
95 ///0x04 - DSI Host Control Register
96 #[inline(always)]
97 pub const fn cr(&self) -> &CR {
98 &self.cr
99 }
100 ///0x08 - DSI HOST Clock Control Register
101 #[inline(always)]
102 pub const fn ccr(&self) -> &CCR {
103 &self.ccr
104 }
105 ///0x0c - DSI Host LTDC VCID Register
106 #[inline(always)]
107 pub const fn lvcidr(&self) -> &LVCIDR {
108 &self.lvcidr
109 }
110 ///0x10 - DSI Host LTDC Color Coding Register
111 #[inline(always)]
112 pub const fn lcolcr(&self) -> &LCOLCR {
113 &self.lcolcr
114 }
115 ///0x14 - DSI Host LTDC Polarity Configuration Register
116 #[inline(always)]
117 pub const fn lpcr(&self) -> &LPCR {
118 &self.lpcr
119 }
120 ///0x18 - DSI Host Low-Power mode Configuration Register
121 #[inline(always)]
122 pub const fn lpmcr(&self) -> &LPMCR {
123 &self.lpmcr
124 }
125 ///0x2c - DSI Host Protocol Configuration Register
126 #[inline(always)]
127 pub const fn pcr(&self) -> &PCR {
128 &self.pcr
129 }
130 ///0x30 - DSI Host Generic VCID Register
131 #[inline(always)]
132 pub const fn gvcidr(&self) -> &GVCIDR {
133 &self.gvcidr
134 }
135 ///0x34 - DSI Host mode Configuration Register
136 #[inline(always)]
137 pub const fn mcr(&self) -> &MCR {
138 &self.mcr
139 }
140 ///0x38 - DSI Host Video mode Configuration Register
141 #[inline(always)]
142 pub const fn vmcr(&self) -> &VMCR {
143 &self.vmcr
144 }
145 ///0x3c - DSI Host Video Packet Configuration Register
146 #[inline(always)]
147 pub const fn vpcr(&self) -> &VPCR {
148 &self.vpcr
149 }
150 ///0x40 - DSI Host Video Chunks Configuration Register
151 #[inline(always)]
152 pub const fn vccr(&self) -> &VCCR {
153 &self.vccr
154 }
155 ///0x44 - DSI Host Video Null Packet Configuration Register
156 #[inline(always)]
157 pub const fn vnpcr(&self) -> &VNPCR {
158 &self.vnpcr
159 }
160 ///0x48 - DSI Host Video HSA Configuration Register
161 #[inline(always)]
162 pub const fn vhsacr(&self) -> &VHSACR {
163 &self.vhsacr
164 }
165 ///0x4c - DSI Host Video HBP Configuration Register
166 #[inline(always)]
167 pub const fn vhbpcr(&self) -> &VHBPCR {
168 &self.vhbpcr
169 }
170 ///0x50 - DSI Host Video Line Configuration Register
171 #[inline(always)]
172 pub const fn vlcr(&self) -> &VLCR {
173 &self.vlcr
174 }
175 ///0x54 - DSI Host Video VSA Configuration Register
176 #[inline(always)]
177 pub const fn vvsacr(&self) -> &VVSACR {
178 &self.vvsacr
179 }
180 ///0x58 - DSI Host Video VBP Configuration Register
181 #[inline(always)]
182 pub const fn vvbpcr(&self) -> &VVBPCR {
183 &self.vvbpcr
184 }
185 ///0x5c - DSI Host Video VFP Configuration Register
186 #[inline(always)]
187 pub const fn vvfpcr(&self) -> &VVFPCR {
188 &self.vvfpcr
189 }
190 ///0x60 - DSI Host Video VA Configuration Register
191 #[inline(always)]
192 pub const fn vvacr(&self) -> &VVACR {
193 &self.vvacr
194 }
195 ///0x64 - DSI Host LTDC Command Configuration Register
196 #[inline(always)]
197 pub const fn lccr(&self) -> &LCCR {
198 &self.lccr
199 }
200 ///0x68 - DSI Host Command mode Configuration Register
201 #[inline(always)]
202 pub const fn cmcr(&self) -> &CMCR {
203 &self.cmcr
204 }
205 ///0x6c - DSI Host Generic Header Configuration Register
206 #[inline(always)]
207 pub const fn ghcr(&self) -> &GHCR {
208 &self.ghcr
209 }
210 ///0x70 - DSI Host Generic Payload Data Register
211 #[inline(always)]
212 pub const fn gpdr(&self) -> &GPDR {
213 &self.gpdr
214 }
215 ///0x74 - DSI Host Generic Packet Status Register
216 #[inline(always)]
217 pub const fn gpsr(&self) -> &GPSR {
218 &self.gpsr
219 }
220 ///0x78 - DSI Host Timeout Counter Configuration Register 0
221 #[inline(always)]
222 pub const fn tccr0(&self) -> &TCCR0 {
223 &self.tccr0
224 }
225 ///0x7c - DSI Host Timeout Counter Configuration Register 1
226 #[inline(always)]
227 pub const fn tccr1(&self) -> &TCCR1 {
228 &self.tccr1
229 }
230 ///0x80 - DSI Host Timeout Counter Configuration Register 2
231 #[inline(always)]
232 pub const fn tccr2(&self) -> &TCCR2 {
233 &self.tccr2
234 }
235 ///0x84 - DSI Host Timeout Counter Configuration Register 3
236 #[inline(always)]
237 pub const fn tccr3(&self) -> &TCCR3 {
238 &self.tccr3
239 }
240 ///0x88 - DSI Host Timeout Counter Configuration Register 4
241 #[inline(always)]
242 pub const fn tccr4(&self) -> &TCCR4 {
243 &self.tccr4
244 }
245 ///0x8c - DSI Host Timeout Counter Configuration Register 5
246 #[inline(always)]
247 pub const fn tccr5(&self) -> &TCCR5 {
248 &self.tccr5
249 }
250 ///0x94 - DSI Host Clock Lane Configuration Register
251 #[inline(always)]
252 pub const fn clcr(&self) -> &CLCR {
253 &self.clcr
254 }
255 ///0x98 - DSI Host Clock Lane Timer Configuration Register
256 #[inline(always)]
257 pub const fn cltcr(&self) -> &CLTCR {
258 &self.cltcr
259 }
260 ///0x9c - DSI Host Data Lane Timer Configuration Register
261 #[inline(always)]
262 pub const fn dltcr(&self) -> &DLTCR {
263 &self.dltcr
264 }
265 ///0xa0 - DSI Host PHY Control Register
266 #[inline(always)]
267 pub const fn pctlr(&self) -> &PCTLR {
268 &self.pctlr
269 }
270 ///0xa4 - DSI Host PHY Configuration Register
271 #[inline(always)]
272 pub const fn pconfr(&self) -> &PCONFR {
273 &self.pconfr
274 }
275 ///0xa8 - DSI Host PHY ULPS Control Register
276 #[inline(always)]
277 pub const fn pucr(&self) -> &PUCR {
278 &self.pucr
279 }
280 ///0xac - DSI Host PHY TX Triggers Configuration Register
281 #[inline(always)]
282 pub const fn pttcr(&self) -> &PTTCR {
283 &self.pttcr
284 }
285 ///0xb0 - DSI Host PHY Status Register
286 #[inline(always)]
287 pub const fn psr(&self) -> &PSR {
288 &self.psr
289 }
290 ///0xbc - DSI Host Interrupt & Status Register 0
291 #[inline(always)]
292 pub const fn isr0(&self) -> &ISR0 {
293 &self.isr0
294 }
295 ///0xc0 - DSI Host Interrupt & Status Register 1
296 #[inline(always)]
297 pub const fn isr1(&self) -> &ISR1 {
298 &self.isr1
299 }
300 ///0xc4 - DSI Host Interrupt Enable Register 0
301 #[inline(always)]
302 pub const fn ier0(&self) -> &IER0 {
303 &self.ier0
304 }
305 ///0xc8 - DSI Host Interrupt Enable Register 1
306 #[inline(always)]
307 pub const fn ier1(&self) -> &IER1 {
308 &self.ier1
309 }
310 ///0xd8 - DSI Host Force Interrupt Register 0
311 #[inline(always)]
312 pub const fn fir0(&self) -> &FIR0 {
313 &self.fir0
314 }
315 ///0xdc - DSI Host Force Interrupt Register 1
316 #[inline(always)]
317 pub const fn fir1(&self) -> &FIR1 {
318 &self.fir1
319 }
320 ///0x100 - DSI Host Video Shadow Control Register
321 #[inline(always)]
322 pub const fn vscr(&self) -> &VSCR {
323 &self.vscr
324 }
325 ///0x10c - DSI Host LTDC Current VCID Register
326 #[inline(always)]
327 pub const fn lcvcidr(&self) -> &LCVCIDR {
328 &self.lcvcidr
329 }
330 ///0x110 - DSI Host LTDC Current Color Coding Register
331 #[inline(always)]
332 pub const fn lcccr(&self) -> &LCCCR {
333 &self.lcccr
334 }
335 ///0x118 - DSI Host Low-Power mode Current Configuration Register
336 #[inline(always)]
337 pub const fn lpmccr(&self) -> &LPMCCR {
338 &self.lpmccr
339 }
340 ///0x138 - DSI Host Video mode Current Configuration Register
341 #[inline(always)]
342 pub const fn vmccr(&self) -> &VMCCR {
343 &self.vmccr
344 }
345 ///0x13c - DSI Host Video Packet Current Configuration Register
346 #[inline(always)]
347 pub const fn vpccr(&self) -> &VPCCR {
348 &self.vpccr
349 }
350 ///0x140 - DSI Host Video Chunks Current Configuration Register
351 #[inline(always)]
352 pub const fn vcccr(&self) -> &VCCCR {
353 &self.vcccr
354 }
355 ///0x144 - DSI Host Video Null Packet Current Configuration Register
356 #[inline(always)]
357 pub const fn vnpccr(&self) -> &VNPCCR {
358 &self.vnpccr
359 }
360 ///0x148 - DSI Host Video HSA Current Configuration Register
361 #[inline(always)]
362 pub const fn vhsaccr(&self) -> &VHSACCR {
363 &self.vhsaccr
364 }
365 ///0x14c - DSI Host Video HBP Current Configuration Register
366 #[inline(always)]
367 pub const fn vhbpccr(&self) -> &VHBPCCR {
368 &self.vhbpccr
369 }
370 ///0x150 - DSI Host Video Line Current Configuration Register
371 #[inline(always)]
372 pub const fn vlccr(&self) -> &VLCCR {
373 &self.vlccr
374 }
375 ///0x154 - DSI Host Video VSA Current Configuration Register
376 #[inline(always)]
377 pub const fn vvsaccr(&self) -> &VVSACCR {
378 &self.vvsaccr
379 }
380 ///0x158 - DSI Host Video VBP Current Configuration Register
381 #[inline(always)]
382 pub const fn vvbpccr(&self) -> &VVBPCCR {
383 &self.vvbpccr
384 }
385 ///0x15c - DSI Host Video VFP Current Configuration Register
386 #[inline(always)]
387 pub const fn vvfpccr(&self) -> &VVFPCCR {
388 &self.vvfpccr
389 }
390 ///0x160 - DSI Host Video VA Current Configuration Register
391 #[inline(always)]
392 pub const fn vvaccr(&self) -> &VVACCR {
393 &self.vvaccr
394 }
395 ///0x400 - DSI Wrapper Configuration Register
396 #[inline(always)]
397 pub const fn wcfgr(&self) -> &WCFGR {
398 &self.wcfgr
399 }
400 ///0x404 - DSI Wrapper Control Register
401 #[inline(always)]
402 pub const fn wcr(&self) -> &WCR {
403 &self.wcr
404 }
405 ///0x408 - DSI Wrapper Interrupt Enable Register
406 #[inline(always)]
407 pub const fn wier(&self) -> &WIER {
408 &self.wier
409 }
410 ///0x40c - DSI Wrapper Interrupt & Status Register
411 #[inline(always)]
412 pub const fn wisr(&self) -> &WISR {
413 &self.wisr
414 }
415 ///0x410 - DSI Wrapper Interrupt Flag Clear Register
416 #[inline(always)]
417 pub const fn wifcr(&self) -> &WIFCR {
418 &self.wifcr
419 }
420 ///0x418 - DSI Wrapper PHY Configuration Register 1
421 #[inline(always)]
422 pub const fn wpcr0(&self) -> &WPCR0 {
423 &self.wpcr0
424 }
425 ///0x41c - DSI Wrapper PHY Configuration Register 2
426 #[inline(always)]
427 pub const fn wpcr1(&self) -> &WPCR1 {
428 &self.wpcr1
429 }
430 ///0x420 - DSI Wrapper PHY Configuration Register 3
431 #[inline(always)]
432 pub const fn wpcr2(&self) -> &WPCR2 {
433 &self.wpcr2
434 }
435 ///0x424 - DSI_WPCR4
436 #[inline(always)]
437 pub const fn wpcr3(&self) -> &WPCR3 {
438 &self.wpcr3
439 }
440 ///0x428 - DSI Wrapper PHY Configuration Register 5
441 #[inline(always)]
442 pub const fn wpcr4(&self) -> &WPCR4 {
443 &self.wpcr4
444 }
445 ///0x430 - DSI Wrapper Regulator and PLL Control Register
446 #[inline(always)]
447 pub const fn wrpcr(&self) -> &WRPCR {
448 &self.wrpcr
449 }
450}
451/**VR (r) register accessor: DSI Host Version Register
452
453You can [`read`](crate::Reg::read) this register and get [`vr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
454
455See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VR)
456
457For information about available fields see [`mod@vr`] module*/
458pub type VR = crate::Reg<vr::VRrs>;
459///DSI Host Version Register
460pub mod vr;
461/**CR (rw) register accessor: DSI Host Control Register
462
463You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
464
465See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:CR)
466
467For information about available fields see [`mod@cr`] module*/
468pub type CR = crate::Reg<cr::CRrs>;
469///DSI Host Control Register
470pub mod cr;
471/**CCR (rw) register accessor: DSI HOST Clock Control Register
472
473You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
474
475See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:CCR)
476
477For information about available fields see [`mod@ccr`] module*/
478pub type CCR = crate::Reg<ccr::CCRrs>;
479///DSI HOST Clock Control Register
480pub mod ccr;
481/**LVCIDR (rw) register accessor: DSI Host LTDC VCID Register
482
483You can [`read`](crate::Reg::read) this register and get [`lvcidr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lvcidr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
484
485See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:LVCIDR)
486
487For information about available fields see [`mod@lvcidr`] module*/
488pub type LVCIDR = crate::Reg<lvcidr::LVCIDRrs>;
489///DSI Host LTDC VCID Register
490pub mod lvcidr;
491/**LCOLCR (rw) register accessor: DSI Host LTDC Color Coding Register
492
493You can [`read`](crate::Reg::read) this register and get [`lcolcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcolcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
494
495See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:LCOLCR)
496
497For information about available fields see [`mod@lcolcr`] module*/
498pub type LCOLCR = crate::Reg<lcolcr::LCOLCRrs>;
499///DSI Host LTDC Color Coding Register
500pub mod lcolcr;
501/**LPCR (rw) register accessor: DSI Host LTDC Polarity Configuration Register
502
503You can [`read`](crate::Reg::read) this register and get [`lpcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
504
505See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:LPCR)
506
507For information about available fields see [`mod@lpcr`] module*/
508pub type LPCR = crate::Reg<lpcr::LPCRrs>;
509///DSI Host LTDC Polarity Configuration Register
510pub mod lpcr;
511/**LPMCR (rw) register accessor: DSI Host Low-Power mode Configuration Register
512
513You can [`read`](crate::Reg::read) this register and get [`lpmcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpmcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
514
515See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:LPMCR)
516
517For information about available fields see [`mod@lpmcr`] module*/
518pub type LPMCR = crate::Reg<lpmcr::LPMCRrs>;
519///DSI Host Low-Power mode Configuration Register
520pub mod lpmcr;
521/**PCR (rw) register accessor: DSI Host Protocol Configuration Register
522
523You can [`read`](crate::Reg::read) this register and get [`pcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
524
525See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:PCR)
526
527For information about available fields see [`mod@pcr`] module*/
528pub type PCR = crate::Reg<pcr::PCRrs>;
529///DSI Host Protocol Configuration Register
530pub mod pcr;
531/**GVCIDR (rw) register accessor: DSI Host Generic VCID Register
532
533You can [`read`](crate::Reg::read) this register and get [`gvcidr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gvcidr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
534
535See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:GVCIDR)
536
537For information about available fields see [`mod@gvcidr`] module*/
538pub type GVCIDR = crate::Reg<gvcidr::GVCIDRrs>;
539///DSI Host Generic VCID Register
540pub mod gvcidr;
541/**MCR (rw) register accessor: DSI Host mode Configuration Register
542
543You can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
544
545See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:MCR)
546
547For information about available fields see [`mod@mcr`] module*/
548pub type MCR = crate::Reg<mcr::MCRrs>;
549///DSI Host mode Configuration Register
550pub mod mcr;
551/**VMCR (rw) register accessor: DSI Host Video mode Configuration Register
552
553You can [`read`](crate::Reg::read) this register and get [`vmcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vmcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
554
555See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VMCR)
556
557For information about available fields see [`mod@vmcr`] module*/
558pub type VMCR = crate::Reg<vmcr::VMCRrs>;
559///DSI Host Video mode Configuration Register
560pub mod vmcr;
561/**VPCR (rw) register accessor: DSI Host Video Packet Configuration Register
562
563You can [`read`](crate::Reg::read) this register and get [`vpcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vpcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
564
565See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VPCR)
566
567For information about available fields see [`mod@vpcr`] module*/
568pub type VPCR = crate::Reg<vpcr::VPCRrs>;
569///DSI Host Video Packet Configuration Register
570pub mod vpcr;
571/**VCCR (rw) register accessor: DSI Host Video Chunks Configuration Register
572
573You can [`read`](crate::Reg::read) this register and get [`vccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
574
575See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VCCR)
576
577For information about available fields see [`mod@vccr`] module*/
578pub type VCCR = crate::Reg<vccr::VCCRrs>;
579///DSI Host Video Chunks Configuration Register
580pub mod vccr;
581/**VNPCR (rw) register accessor: DSI Host Video Null Packet Configuration Register
582
583You can [`read`](crate::Reg::read) this register and get [`vnpcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vnpcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
584
585See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VNPCR)
586
587For information about available fields see [`mod@vnpcr`] module*/
588pub type VNPCR = crate::Reg<vnpcr::VNPCRrs>;
589///DSI Host Video Null Packet Configuration Register
590pub mod vnpcr;
591/**VHSACR (rw) register accessor: DSI Host Video HSA Configuration Register
592
593You can [`read`](crate::Reg::read) this register and get [`vhsacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vhsacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
594
595See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VHSACR)
596
597For information about available fields see [`mod@vhsacr`] module*/
598pub type VHSACR = crate::Reg<vhsacr::VHSACRrs>;
599///DSI Host Video HSA Configuration Register
600pub mod vhsacr;
601/**VHBPCR (rw) register accessor: DSI Host Video HBP Configuration Register
602
603You can [`read`](crate::Reg::read) this register and get [`vhbpcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vhbpcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
604
605See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VHBPCR)
606
607For information about available fields see [`mod@vhbpcr`] module*/
608pub type VHBPCR = crate::Reg<vhbpcr::VHBPCRrs>;
609///DSI Host Video HBP Configuration Register
610pub mod vhbpcr;
611/**VLCR (rw) register accessor: DSI Host Video Line Configuration Register
612
613You can [`read`](crate::Reg::read) this register and get [`vlcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vlcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
614
615See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VLCR)
616
617For information about available fields see [`mod@vlcr`] module*/
618pub type VLCR = crate::Reg<vlcr::VLCRrs>;
619///DSI Host Video Line Configuration Register
620pub mod vlcr;
621/**VVSACR (rw) register accessor: DSI Host Video VSA Configuration Register
622
623You can [`read`](crate::Reg::read) this register and get [`vvsacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vvsacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
624
625See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VVSACR)
626
627For information about available fields see [`mod@vvsacr`] module*/
628pub type VVSACR = crate::Reg<vvsacr::VVSACRrs>;
629///DSI Host Video VSA Configuration Register
630pub mod vvsacr;
631/**VVBPCR (rw) register accessor: DSI Host Video VBP Configuration Register
632
633You can [`read`](crate::Reg::read) this register and get [`vvbpcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vvbpcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
634
635See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VVBPCR)
636
637For information about available fields see [`mod@vvbpcr`] module*/
638pub type VVBPCR = crate::Reg<vvbpcr::VVBPCRrs>;
639///DSI Host Video VBP Configuration Register
640pub mod vvbpcr;
641/**VVFPCR (rw) register accessor: DSI Host Video VFP Configuration Register
642
643You can [`read`](crate::Reg::read) this register and get [`vvfpcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vvfpcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
644
645See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VVFPCR)
646
647For information about available fields see [`mod@vvfpcr`] module*/
648pub type VVFPCR = crate::Reg<vvfpcr::VVFPCRrs>;
649///DSI Host Video VFP Configuration Register
650pub mod vvfpcr;
651/**VVACR (rw) register accessor: DSI Host Video VA Configuration Register
652
653You can [`read`](crate::Reg::read) this register and get [`vvacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vvacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
654
655See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VVACR)
656
657For information about available fields see [`mod@vvacr`] module*/
658pub type VVACR = crate::Reg<vvacr::VVACRrs>;
659///DSI Host Video VA Configuration Register
660pub mod vvacr;
661/**LCCR (rw) register accessor: DSI Host LTDC Command Configuration Register
662
663You can [`read`](crate::Reg::read) this register and get [`lccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
664
665See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:LCCR)
666
667For information about available fields see [`mod@lccr`] module*/
668pub type LCCR = crate::Reg<lccr::LCCRrs>;
669///DSI Host LTDC Command Configuration Register
670pub mod lccr;
671/**CMCR (rw) register accessor: DSI Host Command mode Configuration Register
672
673You can [`read`](crate::Reg::read) this register and get [`cmcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
674
675See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:CMCR)
676
677For information about available fields see [`mod@cmcr`] module*/
678pub type CMCR = crate::Reg<cmcr::CMCRrs>;
679///DSI Host Command mode Configuration Register
680pub mod cmcr;
681/**GHCR (rw) register accessor: DSI Host Generic Header Configuration Register
682
683You can [`read`](crate::Reg::read) this register and get [`ghcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
684
685See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:GHCR)
686
687For information about available fields see [`mod@ghcr`] module*/
688pub type GHCR = crate::Reg<ghcr::GHCRrs>;
689///DSI Host Generic Header Configuration Register
690pub mod ghcr;
691/**GPDR (rw) register accessor: DSI Host Generic Payload Data Register
692
693You can [`read`](crate::Reg::read) this register and get [`gpdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
694
695See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:GPDR)
696
697For information about available fields see [`mod@gpdr`] module*/
698pub type GPDR = crate::Reg<gpdr::GPDRrs>;
699///DSI Host Generic Payload Data Register
700pub mod gpdr;
701/**GPSR (r) register accessor: DSI Host Generic Packet Status Register
702
703You can [`read`](crate::Reg::read) this register and get [`gpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
704
705See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:GPSR)
706
707For information about available fields see [`mod@gpsr`] module*/
708pub type GPSR = crate::Reg<gpsr::GPSRrs>;
709///DSI Host Generic Packet Status Register
710pub mod gpsr;
711/**TCCR0 (rw) register accessor: DSI Host Timeout Counter Configuration Register 0
712
713You can [`read`](crate::Reg::read) this register and get [`tccr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
714
715See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:TCCR0)
716
717For information about available fields see [`mod@tccr0`] module*/
718pub type TCCR0 = crate::Reg<tccr0::TCCR0rs>;
719///DSI Host Timeout Counter Configuration Register 0
720pub mod tccr0;
721/**TCCR1 (rw) register accessor: DSI Host Timeout Counter Configuration Register 1
722
723You can [`read`](crate::Reg::read) this register and get [`tccr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
724
725See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:TCCR1)
726
727For information about available fields see [`mod@tccr1`] module*/
728pub type TCCR1 = crate::Reg<tccr1::TCCR1rs>;
729///DSI Host Timeout Counter Configuration Register 1
730pub mod tccr1;
731/**TCCR2 (rw) register accessor: DSI Host Timeout Counter Configuration Register 2
732
733You can [`read`](crate::Reg::read) this register and get [`tccr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
734
735See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:TCCR2)
736
737For information about available fields see [`mod@tccr2`] module*/
738pub type TCCR2 = crate::Reg<tccr2::TCCR2rs>;
739///DSI Host Timeout Counter Configuration Register 2
740pub mod tccr2;
741/**TCCR3 (rw) register accessor: DSI Host Timeout Counter Configuration Register 3
742
743You can [`read`](crate::Reg::read) this register and get [`tccr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
744
745See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:TCCR3)
746
747For information about available fields see [`mod@tccr3`] module*/
748pub type TCCR3 = crate::Reg<tccr3::TCCR3rs>;
749///DSI Host Timeout Counter Configuration Register 3
750pub mod tccr3;
751/**TCCR4 (rw) register accessor: DSI Host Timeout Counter Configuration Register 4
752
753You can [`read`](crate::Reg::read) this register and get [`tccr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
754
755See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:TCCR4)
756
757For information about available fields see [`mod@tccr4`] module*/
758pub type TCCR4 = crate::Reg<tccr4::TCCR4rs>;
759///DSI Host Timeout Counter Configuration Register 4
760pub mod tccr4;
761/**TCCR5 (rw) register accessor: DSI Host Timeout Counter Configuration Register 5
762
763You can [`read`](crate::Reg::read) this register and get [`tccr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tccr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
764
765See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:TCCR5)
766
767For information about available fields see [`mod@tccr5`] module*/
768pub type TCCR5 = crate::Reg<tccr5::TCCR5rs>;
769///DSI Host Timeout Counter Configuration Register 5
770pub mod tccr5;
771/**CLCR (rw) register accessor: DSI Host Clock Lane Configuration Register
772
773You can [`read`](crate::Reg::read) this register and get [`clcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
774
775See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:CLCR)
776
777For information about available fields see [`mod@clcr`] module*/
778pub type CLCR = crate::Reg<clcr::CLCRrs>;
779///DSI Host Clock Lane Configuration Register
780pub mod clcr;
781/**CLTCR (rw) register accessor: DSI Host Clock Lane Timer Configuration Register
782
783You can [`read`](crate::Reg::read) this register and get [`cltcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cltcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
784
785See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:CLTCR)
786
787For information about available fields see [`mod@cltcr`] module*/
788pub type CLTCR = crate::Reg<cltcr::CLTCRrs>;
789///DSI Host Clock Lane Timer Configuration Register
790pub mod cltcr;
791/**DLTCR (rw) register accessor: DSI Host Data Lane Timer Configuration Register
792
793You can [`read`](crate::Reg::read) this register and get [`dltcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dltcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
794
795See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:DLTCR)
796
797For information about available fields see [`mod@dltcr`] module*/
798pub type DLTCR = crate::Reg<dltcr::DLTCRrs>;
799///DSI Host Data Lane Timer Configuration Register
800pub mod dltcr;
801/**PCTLR (rw) register accessor: DSI Host PHY Control Register
802
803You can [`read`](crate::Reg::read) this register and get [`pctlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pctlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
804
805See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:PCTLR)
806
807For information about available fields see [`mod@pctlr`] module*/
808pub type PCTLR = crate::Reg<pctlr::PCTLRrs>;
809///DSI Host PHY Control Register
810pub mod pctlr;
811/**PCONFR (rw) register accessor: DSI Host PHY Configuration Register
812
813You can [`read`](crate::Reg::read) this register and get [`pconfr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pconfr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
814
815See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:PCONFR)
816
817For information about available fields see [`mod@pconfr`] module*/
818pub type PCONFR = crate::Reg<pconfr::PCONFRrs>;
819///DSI Host PHY Configuration Register
820pub mod pconfr;
821/**PUCR (rw) register accessor: DSI Host PHY ULPS Control Register
822
823You can [`read`](crate::Reg::read) this register and get [`pucr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pucr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
824
825See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:PUCR)
826
827For information about available fields see [`mod@pucr`] module*/
828pub type PUCR = crate::Reg<pucr::PUCRrs>;
829///DSI Host PHY ULPS Control Register
830pub mod pucr;
831/**PTTCR (rw) register accessor: DSI Host PHY TX Triggers Configuration Register
832
833You can [`read`](crate::Reg::read) this register and get [`pttcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pttcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
834
835See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:PTTCR)
836
837For information about available fields see [`mod@pttcr`] module*/
838pub type PTTCR = crate::Reg<pttcr::PTTCRrs>;
839///DSI Host PHY TX Triggers Configuration Register
840pub mod pttcr;
841/**PSR (r) register accessor: DSI Host PHY Status Register
842
843You can [`read`](crate::Reg::read) this register and get [`psr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
844
845See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:PSR)
846
847For information about available fields see [`mod@psr`] module*/
848pub type PSR = crate::Reg<psr::PSRrs>;
849///DSI Host PHY Status Register
850pub mod psr;
851/**ISR0 (r) register accessor: DSI Host Interrupt & Status Register 0
852
853You can [`read`](crate::Reg::read) this register and get [`isr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
854
855See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:ISR0)
856
857For information about available fields see [`mod@isr0`] module*/
858pub type ISR0 = crate::Reg<isr0::ISR0rs>;
859///DSI Host Interrupt & Status Register 0
860pub mod isr0;
861/**ISR1 (r) register accessor: DSI Host Interrupt & Status Register 1
862
863You can [`read`](crate::Reg::read) this register and get [`isr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
864
865See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:ISR1)
866
867For information about available fields see [`mod@isr1`] module*/
868pub type ISR1 = crate::Reg<isr1::ISR1rs>;
869///DSI Host Interrupt & Status Register 1
870pub mod isr1;
871/**IER0 (rw) register accessor: DSI Host Interrupt Enable Register 0
872
873You can [`read`](crate::Reg::read) this register and get [`ier0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
874
875See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:IER0)
876
877For information about available fields see [`mod@ier0`] module*/
878pub type IER0 = crate::Reg<ier0::IER0rs>;
879///DSI Host Interrupt Enable Register 0
880pub mod ier0;
881/**IER1 (rw) register accessor: DSI Host Interrupt Enable Register 1
882
883You can [`read`](crate::Reg::read) this register and get [`ier1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
884
885See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:IER1)
886
887For information about available fields see [`mod@ier1`] module*/
888pub type IER1 = crate::Reg<ier1::IER1rs>;
889///DSI Host Interrupt Enable Register 1
890pub mod ier1;
891/**FIR0 (w) register accessor: DSI Host Force Interrupt Register 0
892
893You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fir0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
894
895See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:FIR0)
896
897For information about available fields see [`mod@fir0`] module*/
898pub type FIR0 = crate::Reg<fir0::FIR0rs>;
899///DSI Host Force Interrupt Register 0
900pub mod fir0;
901/**FIR1 (w) register accessor: DSI Host Force Interrupt Register 1
902
903You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fir1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
904
905See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:FIR1)
906
907For information about available fields see [`mod@fir1`] module*/
908pub type FIR1 = crate::Reg<fir1::FIR1rs>;
909///DSI Host Force Interrupt Register 1
910pub mod fir1;
911/**VSCR (rw) register accessor: DSI Host Video Shadow Control Register
912
913You can [`read`](crate::Reg::read) this register and get [`vscr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vscr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
914
915See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VSCR)
916
917For information about available fields see [`mod@vscr`] module*/
918pub type VSCR = crate::Reg<vscr::VSCRrs>;
919///DSI Host Video Shadow Control Register
920pub mod vscr;
921/**LCVCIDR (r) register accessor: DSI Host LTDC Current VCID Register
922
923You can [`read`](crate::Reg::read) this register and get [`lcvcidr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
924
925See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:LCVCIDR)
926
927For information about available fields see [`mod@lcvcidr`] module*/
928pub type LCVCIDR = crate::Reg<lcvcidr::LCVCIDRrs>;
929///DSI Host LTDC Current VCID Register
930pub mod lcvcidr;
931/**LCCCR (r) register accessor: DSI Host LTDC Current Color Coding Register
932
933You can [`read`](crate::Reg::read) this register and get [`lcccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
934
935See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:LCCCR)
936
937For information about available fields see [`mod@lcccr`] module*/
938pub type LCCCR = crate::Reg<lcccr::LCCCRrs>;
939///DSI Host LTDC Current Color Coding Register
940pub mod lcccr;
941/**LPMCCR (r) register accessor: DSI Host Low-Power mode Current Configuration Register
942
943You can [`read`](crate::Reg::read) this register and get [`lpmccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
944
945See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:LPMCCR)
946
947For information about available fields see [`mod@lpmccr`] module*/
948pub type LPMCCR = crate::Reg<lpmccr::LPMCCRrs>;
949///DSI Host Low-Power mode Current Configuration Register
950pub mod lpmccr;
951/**VMCCR (r) register accessor: DSI Host Video mode Current Configuration Register
952
953You can [`read`](crate::Reg::read) this register and get [`vmccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
954
955See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VMCCR)
956
957For information about available fields see [`mod@vmccr`] module*/
958pub type VMCCR = crate::Reg<vmccr::VMCCRrs>;
959///DSI Host Video mode Current Configuration Register
960pub mod vmccr;
961/**VPCCR (r) register accessor: DSI Host Video Packet Current Configuration Register
962
963You can [`read`](crate::Reg::read) this register and get [`vpccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
964
965See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VPCCR)
966
967For information about available fields see [`mod@vpccr`] module*/
968pub type VPCCR = crate::Reg<vpccr::VPCCRrs>;
969///DSI Host Video Packet Current Configuration Register
970pub mod vpccr;
971/**VCCCR (r) register accessor: DSI Host Video Chunks Current Configuration Register
972
973You can [`read`](crate::Reg::read) this register and get [`vcccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
974
975See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VCCCR)
976
977For information about available fields see [`mod@vcccr`] module*/
978pub type VCCCR = crate::Reg<vcccr::VCCCRrs>;
979///DSI Host Video Chunks Current Configuration Register
980pub mod vcccr;
981/**VNPCCR (r) register accessor: DSI Host Video Null Packet Current Configuration Register
982
983You can [`read`](crate::Reg::read) this register and get [`vnpccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
984
985See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VNPCCR)
986
987For information about available fields see [`mod@vnpccr`] module*/
988pub type VNPCCR = crate::Reg<vnpccr::VNPCCRrs>;
989///DSI Host Video Null Packet Current Configuration Register
990pub mod vnpccr;
991/**VHSACCR (r) register accessor: DSI Host Video HSA Current Configuration Register
992
993You can [`read`](crate::Reg::read) this register and get [`vhsaccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
994
995See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VHSACCR)
996
997For information about available fields see [`mod@vhsaccr`] module*/
998pub type VHSACCR = crate::Reg<vhsaccr::VHSACCRrs>;
999///DSI Host Video HSA Current Configuration Register
1000pub mod vhsaccr;
1001/**VHBPCCR (r) register accessor: DSI Host Video HBP Current Configuration Register
1002
1003You can [`read`](crate::Reg::read) this register and get [`vhbpccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1004
1005See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VHBPCCR)
1006
1007For information about available fields see [`mod@vhbpccr`] module*/
1008pub type VHBPCCR = crate::Reg<vhbpccr::VHBPCCRrs>;
1009///DSI Host Video HBP Current Configuration Register
1010pub mod vhbpccr;
1011/**VLCCR (r) register accessor: DSI Host Video Line Current Configuration Register
1012
1013You can [`read`](crate::Reg::read) this register and get [`vlccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1014
1015See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VLCCR)
1016
1017For information about available fields see [`mod@vlccr`] module*/
1018pub type VLCCR = crate::Reg<vlccr::VLCCRrs>;
1019///DSI Host Video Line Current Configuration Register
1020pub mod vlccr;
1021/**VVSACCR (r) register accessor: DSI Host Video VSA Current Configuration Register
1022
1023You can [`read`](crate::Reg::read) this register and get [`vvsaccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1024
1025See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VVSACCR)
1026
1027For information about available fields see [`mod@vvsaccr`] module*/
1028pub type VVSACCR = crate::Reg<vvsaccr::VVSACCRrs>;
1029///DSI Host Video VSA Current Configuration Register
1030pub mod vvsaccr;
1031/**VVBPCCR (r) register accessor: DSI Host Video VBP Current Configuration Register
1032
1033You can [`read`](crate::Reg::read) this register and get [`vvbpccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1034
1035See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VVBPCCR)
1036
1037For information about available fields see [`mod@vvbpccr`] module*/
1038pub type VVBPCCR = crate::Reg<vvbpccr::VVBPCCRrs>;
1039///DSI Host Video VBP Current Configuration Register
1040pub mod vvbpccr;
1041/**VVFPCCR (r) register accessor: DSI Host Video VFP Current Configuration Register
1042
1043You can [`read`](crate::Reg::read) this register and get [`vvfpccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1044
1045See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VVFPCCR)
1046
1047For information about available fields see [`mod@vvfpccr`] module*/
1048pub type VVFPCCR = crate::Reg<vvfpccr::VVFPCCRrs>;
1049///DSI Host Video VFP Current Configuration Register
1050pub mod vvfpccr;
1051/**VVACCR (r) register accessor: DSI Host Video VA Current Configuration Register
1052
1053You can [`read`](crate::Reg::read) this register and get [`vvaccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1054
1055See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:VVACCR)
1056
1057For information about available fields see [`mod@vvaccr`] module*/
1058pub type VVACCR = crate::Reg<vvaccr::VVACCRrs>;
1059///DSI Host Video VA Current Configuration Register
1060pub mod vvaccr;
1061/**WCFGR (rw) register accessor: DSI Wrapper Configuration Register
1062
1063You can [`read`](crate::Reg::read) this register and get [`wcfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wcfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1064
1065See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WCFGR)
1066
1067For information about available fields see [`mod@wcfgr`] module*/
1068pub type WCFGR = crate::Reg<wcfgr::WCFGRrs>;
1069///DSI Wrapper Configuration Register
1070pub mod wcfgr;
1071/**WCR (rw) register accessor: DSI Wrapper Control Register
1072
1073You can [`read`](crate::Reg::read) this register and get [`wcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1074
1075See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WCR)
1076
1077For information about available fields see [`mod@wcr`] module*/
1078pub type WCR = crate::Reg<wcr::WCRrs>;
1079///DSI Wrapper Control Register
1080pub mod wcr;
1081/**WIER (rw) register accessor: DSI Wrapper Interrupt Enable Register
1082
1083You can [`read`](crate::Reg::read) this register and get [`wier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1084
1085See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WIER)
1086
1087For information about available fields see [`mod@wier`] module*/
1088pub type WIER = crate::Reg<wier::WIERrs>;
1089///DSI Wrapper Interrupt Enable Register
1090pub mod wier;
1091/**WISR (r) register accessor: DSI Wrapper Interrupt & Status Register
1092
1093You can [`read`](crate::Reg::read) this register and get [`wisr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1094
1095See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WISR)
1096
1097For information about available fields see [`mod@wisr`] module*/
1098pub type WISR = crate::Reg<wisr::WISRrs>;
1099///DSI Wrapper Interrupt & Status Register
1100pub mod wisr;
1101/**WIFCR (rw) register accessor: DSI Wrapper Interrupt Flag Clear Register
1102
1103You can [`read`](crate::Reg::read) this register and get [`wifcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wifcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1104
1105See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WIFCR)
1106
1107For information about available fields see [`mod@wifcr`] module*/
1108pub type WIFCR = crate::Reg<wifcr::WIFCRrs>;
1109///DSI Wrapper Interrupt Flag Clear Register
1110pub mod wifcr;
1111/**WPCR0 (rw) register accessor: DSI Wrapper PHY Configuration Register 1
1112
1113You can [`read`](crate::Reg::read) this register and get [`wpcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1114
1115See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WPCR0)
1116
1117For information about available fields see [`mod@wpcr0`] module*/
1118pub type WPCR0 = crate::Reg<wpcr0::WPCR0rs>;
1119///DSI Wrapper PHY Configuration Register 1
1120pub mod wpcr0;
1121/**WPCR1 (rw) register accessor: DSI Wrapper PHY Configuration Register 2
1122
1123You can [`read`](crate::Reg::read) this register and get [`wpcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1124
1125See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WPCR1)
1126
1127For information about available fields see [`mod@wpcr1`] module*/
1128pub type WPCR1 = crate::Reg<wpcr1::WPCR1rs>;
1129///DSI Wrapper PHY Configuration Register 2
1130pub mod wpcr1;
1131/**WPCR2 (rw) register accessor: DSI Wrapper PHY Configuration Register 3
1132
1133You can [`read`](crate::Reg::read) this register and get [`wpcr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpcr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1134
1135See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WPCR2)
1136
1137For information about available fields see [`mod@wpcr2`] module*/
1138pub type WPCR2 = crate::Reg<wpcr2::WPCR2rs>;
1139///DSI Wrapper PHY Configuration Register 3
1140pub mod wpcr2;
1141/**WPCR3 (rw) register accessor: DSI_WPCR4
1142
1143You can [`read`](crate::Reg::read) this register and get [`wpcr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpcr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1144
1145See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WPCR3)
1146
1147For information about available fields see [`mod@wpcr3`] module*/
1148pub type WPCR3 = crate::Reg<wpcr3::WPCR3rs>;
1149///DSI_WPCR4
1150pub mod wpcr3;
1151/**WPCR4 (rw) register accessor: DSI Wrapper PHY Configuration Register 5
1152
1153You can [`read`](crate::Reg::read) this register and get [`wpcr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpcr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1154
1155See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WPCR4)
1156
1157For information about available fields see [`mod@wpcr4`] module*/
1158pub type WPCR4 = crate::Reg<wpcr4::WPCR4rs>;
1159///DSI Wrapper PHY Configuration Register 5
1160pub mod wpcr4;
1161/**WRPCR (rw) register accessor: DSI Wrapper Regulator and PLL Control Register
1162
1163You can [`read`](crate::Reg::read) this register and get [`wrpcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wrpcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1164
1165See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WRPCR)
1166
1167For information about available fields see [`mod@wrpcr`] module*/
1168pub type WRPCR = crate::Reg<wrpcr::WRPCRrs>;
1169///DSI Wrapper Regulator and PLL Control Register
1170pub mod wrpcr;