stm32f7/stm32f779/dfsdm/
ch.rs

1#[repr(C)]
2#[derive(Debug)]
3///DFSDM channel configuration cluster
4pub struct CH {
5    cfgr1: CFGR1,
6    cfgr2: CFGR2,
7    awscdr: AWSCDR,
8    wdatr: WDATR,
9    datinr: DATINR,
10    _reserved_end: [u8; 0x0c],
11}
12impl CH {
13    ///0x00 - DFSDM channel configuration 0 register 1
14    #[inline(always)]
15    pub const fn cfgr1(&self) -> &CFGR1 {
16        &self.cfgr1
17    }
18    ///0x04 - DFSDM channel configuration 0 register 2
19    #[inline(always)]
20    pub const fn cfgr2(&self) -> &CFGR2 {
21        &self.cfgr2
22    }
23    ///0x08 - DFSDM analog watchdog and short-circuit detector register
24    #[inline(always)]
25    pub const fn awscdr(&self) -> &AWSCDR {
26        &self.awscdr
27    }
28    ///0x0c - DFSDM channel watchdog filter data register
29    #[inline(always)]
30    pub const fn wdatr(&self) -> &WDATR {
31        &self.wdatr
32    }
33    ///0x10 - DFSDM channel data input register
34    #[inline(always)]
35    pub const fn datinr(&self) -> &DATINR {
36        &self.datinr
37    }
38}
39/**CFGR1 (rw) register accessor: DFSDM channel configuration 0 register 1
40
41You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
42
43For information about available fields see [`mod@cfgr1`] module*/
44pub type CFGR1 = crate::Reg<cfgr1::CFGR1rs>;
45///DFSDM channel configuration 0 register 1
46pub mod cfgr1;
47/**CFGR2 (rw) register accessor: DFSDM channel configuration 0 register 2
48
49You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
50
51For information about available fields see [`mod@cfgr2`] module*/
52pub type CFGR2 = crate::Reg<cfgr2::CFGR2rs>;
53///DFSDM channel configuration 0 register 2
54pub mod cfgr2;
55/**AWSCDR (rw) register accessor: DFSDM analog watchdog and short-circuit detector register
56
57You can [`read`](crate::Reg::read) this register and get [`awscdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awscdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
58
59For information about available fields see [`mod@awscdr`] module*/
60pub type AWSCDR = crate::Reg<awscdr::AWSCDRrs>;
61///DFSDM analog watchdog and short-circuit detector register
62pub mod awscdr;
63/**WDATR (r) register accessor: DFSDM channel watchdog filter data register
64
65You can [`read`](crate::Reg::read) this register and get [`wdatr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
66
67For information about available fields see [`mod@wdatr`] module*/
68pub type WDATR = crate::Reg<wdatr::WDATRrs>;
69///DFSDM channel watchdog filter data register
70pub mod wdatr;
71/**DATINR (rw) register accessor: DFSDM channel data input register
72
73You can [`read`](crate::Reg::read) this register and get [`datinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
74
75For information about available fields see [`mod@datinr`] module*/
76pub type DATINR = crate::Reg<datinr::DATINRrs>;
77///DFSDM channel data input register
78pub mod datinr;
stm32f7/stm32f779/dfsdm/ch.rs

stm32f7/stm32f779/dfsdm/
ch.rs
