stm32f7/stm32f733/
tim2.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    _reserved12: [u8; 0x04],
18    ccr: [CCR; 4],
19    _reserved13: [u8; 0x04],
20    dcr: DCR,
21    dmar: DMAR,
22    or: OR,
23}
24impl RegisterBlock {
25    ///0x00 - control register 1
26    #[inline(always)]
27    pub const fn cr1(&self) -> &CR1 {
28        &self.cr1
29    }
30    ///0x04 - control register 2
31    #[inline(always)]
32    pub const fn cr2(&self) -> &CR2 {
33        &self.cr2
34    }
35    ///0x08 - slave mode control register
36    #[inline(always)]
37    pub const fn smcr(&self) -> &SMCR {
38        &self.smcr
39    }
40    ///0x0c - DMA/Interrupt enable register
41    #[inline(always)]
42    pub const fn dier(&self) -> &DIER {
43        &self.dier
44    }
45    ///0x10 - status register
46    #[inline(always)]
47    pub const fn sr(&self) -> &SR {
48        &self.sr
49    }
50    ///0x14 - event generation register
51    #[inline(always)]
52    pub const fn egr(&self) -> &EGR {
53        &self.egr
54    }
55    ///0x18 - capture/compare mode register 1 (input mode)
56    #[inline(always)]
57    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
58        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
59    }
60    ///0x18 - capture/compare mode register 1 (output mode)
61    #[inline(always)]
62    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
63        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
64    }
65    ///0x1c - capture/compare mode register 2 (input mode)
66    #[inline(always)]
67    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
68        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
69    }
70    ///0x1c - capture/compare mode register 2 (output mode)
71    #[inline(always)]
72    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
73        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
74    }
75    ///0x20 - capture/compare enable register
76    #[inline(always)]
77    pub const fn ccer(&self) -> &CCER {
78        &self.ccer
79    }
80    ///0x24 - counter
81    #[inline(always)]
82    pub const fn cnt(&self) -> &CNT {
83        &self.cnt
84    }
85    ///0x28 - prescaler
86    #[inline(always)]
87    pub const fn psc(&self) -> &PSC {
88        &self.psc
89    }
90    ///0x2c - auto-reload register
91    #[inline(always)]
92    pub const fn arr(&self) -> &ARR {
93        &self.arr
94    }
95    ///0x34..0x44 - capture/compare register
96    ///
97    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
98    #[inline(always)]
99    pub const fn ccr(&self, n: usize) -> &CCR {
100        &self.ccr[n]
101    }
102    ///Iterator for array of:
103    ///0x34..0x44 - capture/compare register
104    #[inline(always)]
105    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
106        self.ccr.iter()
107    }
108    ///0x34 - capture/compare register
109    #[inline(always)]
110    pub const fn ccr1(&self) -> &CCR {
111        self.ccr(0)
112    }
113    ///0x38 - capture/compare register
114    #[inline(always)]
115    pub const fn ccr2(&self) -> &CCR {
116        self.ccr(1)
117    }
118    ///0x3c - capture/compare register
119    #[inline(always)]
120    pub const fn ccr3(&self) -> &CCR {
121        self.ccr(2)
122    }
123    ///0x40 - capture/compare register
124    #[inline(always)]
125    pub const fn ccr4(&self) -> &CCR {
126        self.ccr(3)
127    }
128    ///0x48 - DMA control register
129    #[inline(always)]
130    pub const fn dcr(&self) -> &DCR {
131        &self.dcr
132    }
133    ///0x4c - DMA address for full transfer
134    #[inline(always)]
135    pub const fn dmar(&self) -> &DMAR {
136        &self.dmar
137    }
138    ///0x50 - TIM2 option register 1
139    #[inline(always)]
140    pub const fn or(&self) -> &OR {
141        &self.or
142    }
143}
144/**CR1 (rw) register accessor: control register 1
145
146You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
147
148See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CR1)
149
150For information about available fields see [`mod@cr1`] module*/
151pub type CR1 = crate::Reg<cr1::CR1rs>;
152///control register 1
153pub mod cr1;
154/**CR2 (rw) register accessor: control register 2
155
156You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
157
158See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CR2)
159
160For information about available fields see [`mod@cr2`] module*/
161pub type CR2 = crate::Reg<cr2::CR2rs>;
162///control register 2
163pub mod cr2;
164/**SMCR (rw) register accessor: slave mode control register
165
166You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:SMCR)
169
170For information about available fields see [`mod@smcr`] module*/
171pub type SMCR = crate::Reg<smcr::SMCRrs>;
172///slave mode control register
173pub mod smcr;
174/**DIER (rw) register accessor: DMA/Interrupt enable register
175
176You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
177
178See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:DIER)
179
180For information about available fields see [`mod@dier`] module*/
181pub type DIER = crate::Reg<dier::DIERrs>;
182///DMA/Interrupt enable register
183pub mod dier;
184/**SR (rw) register accessor: status register
185
186You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
187
188See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:SR)
189
190For information about available fields see [`mod@sr`] module*/
191pub type SR = crate::Reg<sr::SRrs>;
192///status register
193pub mod sr;
194/**EGR (w) register accessor: event generation register
195
196You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
197
198See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:EGR)
199
200For information about available fields see [`mod@egr`] module*/
201pub type EGR = crate::Reg<egr::EGRrs>;
202///event generation register
203pub mod egr;
204/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
205
206You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
207
208See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CCMR1_Output)
209
210For information about available fields see [`mod@ccmr1_output`] module*/
211#[doc(alias = "CCMR1_Output")]
212pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
213///capture/compare mode register 1 (output mode)
214pub mod ccmr1_output;
215/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
216
217You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
218
219See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CCMR1_Input)
220
221For information about available fields see [`mod@ccmr1_input`] module*/
222#[doc(alias = "CCMR1_Input")]
223pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
224///capture/compare mode register 1 (input mode)
225pub mod ccmr1_input;
226/**CCMR2_Output (rw) register accessor: capture/compare mode register 2 (output mode)
227
228You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
229
230See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CCMR2_Output)
231
232For information about available fields see [`mod@ccmr2_output`] module*/
233#[doc(alias = "CCMR2_Output")]
234pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUTrs>;
235///capture/compare mode register 2 (output mode)
236pub mod ccmr2_output;
237/**CCMR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)
238
239You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
240
241See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CCMR2_Input)
242
243For information about available fields see [`mod@ccmr2_input`] module*/
244#[doc(alias = "CCMR2_Input")]
245pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUTrs>;
246///capture/compare mode register 2 (input mode)
247pub mod ccmr2_input;
248/**CCER (rw) register accessor: capture/compare enable register
249
250You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
251
252See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CCER)
253
254For information about available fields see [`mod@ccer`] module*/
255pub type CCER = crate::Reg<ccer::CCERrs>;
256///capture/compare enable register
257pub mod ccer;
258/**CNT (rw) register accessor: counter
259
260You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
261
262See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CNT)
263
264For information about available fields see [`mod@cnt`] module*/
265pub type CNT = crate::Reg<cnt::CNTrs>;
266///counter
267pub mod cnt;
268/**PSC (rw) register accessor: prescaler
269
270You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
271
272See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:PSC)
273
274For information about available fields see [`mod@psc`] module*/
275pub type PSC = crate::Reg<psc::PSCrs>;
276///prescaler
277pub mod psc;
278/**ARR (rw) register accessor: auto-reload register
279
280You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
281
282See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:ARR)
283
284For information about available fields see [`mod@arr`] module*/
285pub type ARR = crate::Reg<arr::ARRrs>;
286///auto-reload register
287pub mod arr;
288/**CCR (rw) register accessor: capture/compare register
289
290You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
291
292See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CCR[1])
293
294For information about available fields see [`mod@ccr`] module*/
295pub type CCR = crate::Reg<ccr::CCRrs>;
296///capture/compare register
297pub mod ccr;
298/**DCR (rw) register accessor: DMA control register
299
300You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
301
302See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:DCR)
303
304For information about available fields see [`mod@dcr`] module*/
305pub type DCR = crate::Reg<dcr::DCRrs>;
306///DMA control register
307pub mod dcr;
308/**DMAR (rw) register accessor: DMA address for full transfer
309
310You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
311
312See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:DMAR)
313
314For information about available fields see [`mod@dmar`] module*/
315pub type DMAR = crate::Reg<dmar::DMARrs>;
316///DMA address for full transfer
317pub mod dmar;
318/**OR (rw) register accessor: TIM2 option register 1
319
320You can [`read`](crate::Reg::read) this register and get [`or::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
321
322See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:OR)
323
324For information about available fields see [`mod@or`] module*/
325pub type OR = crate::Reg<or::ORrs>;
326///TIM2 option register 1
327pub mod or;
stm32f7/stm32f733/tim2.rs

stm32f7/stm32f733/
tim2.rs
