stm32f7/stm32f733/
quadspi.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    dcr: DCR,
7    sr: SR,
8    fcr: FCR,
9    dlr: DLR,
10    ccr: CCR,
11    ar: AR,
12    abr: ABR,
13    _reserved_8_dr: [u8; 0x04],
14    psmkr: PSMKR,
15    psmar: PSMAR,
16    pir: PIR,
17    lptr: LPTR,
18}
19impl RegisterBlock {
20    ///0x00 - control register
21    #[inline(always)]
22    pub const fn cr(&self) -> &CR {
23        &self.cr
24    }
25    ///0x04 - device configuration register
26    #[inline(always)]
27    pub const fn dcr(&self) -> &DCR {
28        &self.dcr
29    }
30    ///0x08 - status register
31    #[inline(always)]
32    pub const fn sr(&self) -> &SR {
33        &self.sr
34    }
35    ///0x0c - flag clear register
36    #[inline(always)]
37    pub const fn fcr(&self) -> &FCR {
38        &self.fcr
39    }
40    ///0x10 - data length register
41    #[inline(always)]
42    pub const fn dlr(&self) -> &DLR {
43        &self.dlr
44    }
45    ///0x14 - communication configuration register
46    #[inline(always)]
47    pub const fn ccr(&self) -> &CCR {
48        &self.ccr
49    }
50    ///0x18 - address register
51    #[inline(always)]
52    pub const fn ar(&self) -> &AR {
53        &self.ar
54    }
55    ///0x1c - ABR
56    #[inline(always)]
57    pub const fn abr(&self) -> &ABR {
58        &self.abr
59    }
60    ///0x20 - Data register: one byte (8 bit) access
61    #[inline(always)]
62    pub const fn dr8(&self) -> &DR8 {
63        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
64    }
65    ///0x20 - Data register: half word (16 bit) access
66    #[inline(always)]
67    pub const fn dr16(&self) -> &DR16 {
68        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
69    }
70    ///0x20 - Data register: full word (32 bit) access
71    #[inline(always)]
72    pub const fn dr(&self) -> &DR {
73        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
74    }
75    ///0x24 - polling status mask register
76    #[inline(always)]
77    pub const fn psmkr(&self) -> &PSMKR {
78        &self.psmkr
79    }
80    ///0x28 - polling status match register
81    #[inline(always)]
82    pub const fn psmar(&self) -> &PSMAR {
83        &self.psmar
84    }
85    ///0x2c - polling interval register
86    #[inline(always)]
87    pub const fn pir(&self) -> &PIR {
88        &self.pir
89    }
90    ///0x30 - low-power timeout register
91    #[inline(always)]
92    pub const fn lptr(&self) -> &LPTR {
93        &self.lptr
94    }
95}
96/**CR (rw) register accessor: control register
97
98You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
99
100See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:CR)
101
102For information about available fields see [`mod@cr`] module*/
103pub type CR = crate::Reg<cr::CRrs>;
104///control register
105pub mod cr;
106/**DCR (rw) register accessor: device configuration register
107
108You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
109
110See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:DCR)
111
112For information about available fields see [`mod@dcr`] module*/
113pub type DCR = crate::Reg<dcr::DCRrs>;
114///device configuration register
115pub mod dcr;
116/**SR (r) register accessor: status register
117
118You can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
119
120See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:SR)
121
122For information about available fields see [`mod@sr`] module*/
123pub type SR = crate::Reg<sr::SRrs>;
124///status register
125pub mod sr;
126/**FCR (rw) register accessor: flag clear register
127
128You can [`read`](crate::Reg::read) this register and get [`fcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
129
130See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:FCR)
131
132For information about available fields see [`mod@fcr`] module*/
133pub type FCR = crate::Reg<fcr::FCRrs>;
134///flag clear register
135pub mod fcr;
136/**DLR (rw) register accessor: data length register
137
138You can [`read`](crate::Reg::read) this register and get [`dlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
139
140See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:DLR)
141
142For information about available fields see [`mod@dlr`] module*/
143pub type DLR = crate::Reg<dlr::DLRrs>;
144///data length register
145pub mod dlr;
146/**CCR (rw) register accessor: communication configuration register
147
148You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
149
150See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:CCR)
151
152For information about available fields see [`mod@ccr`] module*/
153pub type CCR = crate::Reg<ccr::CCRrs>;
154///communication configuration register
155pub mod ccr;
156/**AR (rw) register accessor: address register
157
158You can [`read`](crate::Reg::read) this register and get [`ar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
159
160See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:AR)
161
162For information about available fields see [`mod@ar`] module*/
163pub type AR = crate::Reg<ar::ARrs>;
164///address register
165pub mod ar;
166/**ABR (rw) register accessor: ABR
167
168You can [`read`](crate::Reg::read) this register and get [`abr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`abr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
169
170See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:ABR)
171
172For information about available fields see [`mod@abr`] module*/
173pub type ABR = crate::Reg<abr::ABRrs>;
174///ABR
175pub mod abr;
176/**DR (rw) register accessor: Data register: full word (32 bit) access
177
178You can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
179
180See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:DR)
181
182For information about available fields see [`mod@dr`] module*/
183pub type DR = crate::Reg<dr::DRrs>;
184///Data register: full word (32 bit) access
185pub mod dr;
186/**DR16 (rw) register accessor: Data register: half word (16 bit) access
187
188You can [`read`](crate::Reg::read) this register and get [`dr16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
189
190See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:DR16)
191
192For information about available fields see [`mod@dr16`] module*/
193pub type DR16 = crate::Reg<dr16::DR16rs>;
194///Data register: half word (16 bit) access
195pub mod dr16;
196/**DR8 (rw) register accessor: Data register: one byte (8 bit) access
197
198You can [`read`](crate::Reg::read) this register and get [`dr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
199
200See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:DR8)
201
202For information about available fields see [`mod@dr8`] module*/
203pub type DR8 = crate::Reg<dr8::DR8rs>;
204///Data register: one byte (8 bit) access
205pub mod dr8;
206/**PSMKR (rw) register accessor: polling status mask register
207
208You can [`read`](crate::Reg::read) this register and get [`psmkr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psmkr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
209
210See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:PSMKR)
211
212For information about available fields see [`mod@psmkr`] module*/
213pub type PSMKR = crate::Reg<psmkr::PSMKRrs>;
214///polling status mask register
215pub mod psmkr;
216/**PSMAR (rw) register accessor: polling status match register
217
218You can [`read`](crate::Reg::read) this register and get [`psmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
219
220See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:PSMAR)
221
222For information about available fields see [`mod@psmar`] module*/
223pub type PSMAR = crate::Reg<psmar::PSMARrs>;
224///polling status match register
225pub mod psmar;
226/**PIR (rw) register accessor: polling interval register
227
228You can [`read`](crate::Reg::read) this register and get [`pir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
229
230See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:PIR)
231
232For information about available fields see [`mod@pir`] module*/
233pub type PIR = crate::Reg<pir::PIRrs>;
234///polling interval register
235pub mod pir;
236/**LPTR (rw) register accessor: low-power timeout register
237
238You can [`read`](crate::Reg::read) this register and get [`lptr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lptr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
239
240See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI:LPTR)
241
242For information about available fields see [`mod@lptr`] module*/
243pub type LPTR = crate::Reg<lptr::LPTRrs>;
244///low-power timeout register
245pub mod lptr;
stm32f7/stm32f733/quadspi.rs

stm32f7/stm32f733/
quadspi.rs
