stm32f7/stm32f733/can1/
btr.rs

1///Register `BTR` reader
2pub type R = crate::R<BTRrs>;
3///Register `BTR` writer
4pub type W = crate::W<BTRrs>;
5///Field `BRP` reader - BRP
6pub type BRP_R = crate::FieldReader<u16>;
7///Field `BRP` writer - BRP
8pub type BRP_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
9///Field `TS1` reader - TS1
10pub type TS1_R = crate::FieldReader;
11///Field `TS1` writer - TS1
12pub type TS1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13///Field `TS2` reader - TS2
14pub type TS2_R = crate::FieldReader;
15///Field `TS2` writer - TS2
16pub type TS2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17///Field `SJW` reader - SJW
18pub type SJW_R = crate::FieldReader;
19///Field `SJW` writer - SJW
20pub type SJW_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21/**LBKM
22
23Value on reset: 0*/
24#[cfg_attr(feature = "defmt", derive(defmt::Format))]
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26pub enum LBKM {
27    ///0: Loop Back Mode disabled
28    Disabled = 0,
29    ///1: Loop Back Mode enabled
30    Enabled = 1,
31}
32impl From<LBKM> for bool {
33    #[inline(always)]
34    fn from(variant: LBKM) -> Self {
35        variant as u8 != 0
36    }
37}
38///Field `LBKM` reader - LBKM
39pub type LBKM_R = crate::BitReader<LBKM>;
40impl LBKM_R {
41    ///Get enumerated values variant
42    #[inline(always)]
43    pub const fn variant(&self) -> LBKM {
44        match self.bits {
45            false => LBKM::Disabled,
46            true => LBKM::Enabled,
47        }
48    }
49    ///Loop Back Mode disabled
50    #[inline(always)]
51    pub fn is_disabled(&self) -> bool {
52        *self == LBKM::Disabled
53    }
54    ///Loop Back Mode enabled
55    #[inline(always)]
56    pub fn is_enabled(&self) -> bool {
57        *self == LBKM::Enabled
58    }
59}
60///Field `LBKM` writer - LBKM
61pub type LBKM_W<'a, REG> = crate::BitWriter<'a, REG, LBKM>;
62impl<'a, REG> LBKM_W<'a, REG>
63where
64    REG: crate::Writable + crate::RegisterSpec,
65{
66    ///Loop Back Mode disabled
67    #[inline(always)]
68    pub fn disabled(self) -> &'a mut crate::W<REG> {
69        self.variant(LBKM::Disabled)
70    }
71    ///Loop Back Mode enabled
72    #[inline(always)]
73    pub fn enabled(self) -> &'a mut crate::W<REG> {
74        self.variant(LBKM::Enabled)
75    }
76}
77/**SILM
78
79Value on reset: 0*/
80#[cfg_attr(feature = "defmt", derive(defmt::Format))]
81#[derive(Clone, Copy, Debug, PartialEq, Eq)]
82pub enum SILM {
83    ///0: Normal operation
84    Normal = 0,
85    ///1: Silent Mode
86    Silent = 1,
87}
88impl From<SILM> for bool {
89    #[inline(always)]
90    fn from(variant: SILM) -> Self {
91        variant as u8 != 0
92    }
93}
94///Field `SILM` reader - SILM
95pub type SILM_R = crate::BitReader<SILM>;
96impl SILM_R {
97    ///Get enumerated values variant
98    #[inline(always)]
99    pub const fn variant(&self) -> SILM {
100        match self.bits {
101            false => SILM::Normal,
102            true => SILM::Silent,
103        }
104    }
105    ///Normal operation
106    #[inline(always)]
107    pub fn is_normal(&self) -> bool {
108        *self == SILM::Normal
109    }
110    ///Silent Mode
111    #[inline(always)]
112    pub fn is_silent(&self) -> bool {
113        *self == SILM::Silent
114    }
115}
116///Field `SILM` writer - SILM
117pub type SILM_W<'a, REG> = crate::BitWriter<'a, REG, SILM>;
118impl<'a, REG> SILM_W<'a, REG>
119where
120    REG: crate::Writable + crate::RegisterSpec,
121{
122    ///Normal operation
123    #[inline(always)]
124    pub fn normal(self) -> &'a mut crate::W<REG> {
125        self.variant(SILM::Normal)
126    }
127    ///Silent Mode
128    #[inline(always)]
129    pub fn silent(self) -> &'a mut crate::W<REG> {
130        self.variant(SILM::Silent)
131    }
132}
133impl R {
134    ///Bits 0:9 - BRP
135    #[inline(always)]
136    pub fn brp(&self) -> BRP_R {
137        BRP_R::new((self.bits & 0x03ff) as u16)
138    }
139    ///Bits 16:19 - TS1
140    #[inline(always)]
141    pub fn ts1(&self) -> TS1_R {
142        TS1_R::new(((self.bits >> 16) & 0x0f) as u8)
143    }
144    ///Bits 20:22 - TS2
145    #[inline(always)]
146    pub fn ts2(&self) -> TS2_R {
147        TS2_R::new(((self.bits >> 20) & 7) as u8)
148    }
149    ///Bits 24:25 - SJW
150    #[inline(always)]
151    pub fn sjw(&self) -> SJW_R {
152        SJW_R::new(((self.bits >> 24) & 3) as u8)
153    }
154    ///Bit 30 - LBKM
155    #[inline(always)]
156    pub fn lbkm(&self) -> LBKM_R {
157        LBKM_R::new(((self.bits >> 30) & 1) != 0)
158    }
159    ///Bit 31 - SILM
160    #[inline(always)]
161    pub fn silm(&self) -> SILM_R {
162        SILM_R::new(((self.bits >> 31) & 1) != 0)
163    }
164}
165impl core::fmt::Debug for R {
166    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
167        f.debug_struct("BTR")
168            .field("silm", &self.silm())
169            .field("lbkm", &self.lbkm())
170            .field("sjw", &self.sjw())
171            .field("ts2", &self.ts2())
172            .field("ts1", &self.ts1())
173            .field("brp", &self.brp())
174            .finish()
175    }
176}
177impl W {
178    ///Bits 0:9 - BRP
179    #[inline(always)]
180    pub fn brp(&mut self) -> BRP_W<BTRrs> {
181        BRP_W::new(self, 0)
182    }
183    ///Bits 16:19 - TS1
184    #[inline(always)]
185    pub fn ts1(&mut self) -> TS1_W<BTRrs> {
186        TS1_W::new(self, 16)
187    }
188    ///Bits 20:22 - TS2
189    #[inline(always)]
190    pub fn ts2(&mut self) -> TS2_W<BTRrs> {
191        TS2_W::new(self, 20)
192    }
193    ///Bits 24:25 - SJW
194    #[inline(always)]
195    pub fn sjw(&mut self) -> SJW_W<BTRrs> {
196        SJW_W::new(self, 24)
197    }
198    ///Bit 30 - LBKM
199    #[inline(always)]
200    pub fn lbkm(&mut self) -> LBKM_W<BTRrs> {
201        LBKM_W::new(self, 30)
202    }
203    ///Bit 31 - SILM
204    #[inline(always)]
205    pub fn silm(&mut self) -> SILM_W<BTRrs> {
206        SILM_W::new(self, 31)
207    }
208}
209/**bit timing register
210
211You can [`read`](crate::Reg::read) this register and get [`btr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
212
213See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#CAN1:BTR)*/
214pub struct BTRrs;
215impl crate::RegisterSpec for BTRrs {
216    type Ux = u32;
217}
218///`read()` method returns [`btr::R`](R) reader structure
219impl crate::Readable for BTRrs {}
220///`write(|w| ..)` method takes [`btr::W`](W) writer structure
221impl crate::Writable for BTRrs {
222    type Safety = crate::Unsafe;
223}
224///`reset()` method sets BTR to value 0
225impl crate::Resettable for BTRrs {}
stm32f7/stm32f733/can1/btr.rs

stm32f7/stm32f733/can1/
btr.rs
