Struct stm32f7::W[−][src]

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

Writes raw bits to the register

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>[src]

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>[src]

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>[src]

pub fn ois4(&mut self) -> OIS4_W<'_>[src]

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>[src]

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>[src]

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>[src]

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>[src]

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>[src]

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>[src]

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>[src]

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>[src]

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>[src]

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>[src]

Bit 0 - Capture/compare preloaded control

pub fn mms2(&mut self) -> MMS2_W<'_>[src]

Bits 20:23 - Master mode selection 2

pub fn ois6(&mut self) -> OIS6_W<'_>[src]

Bit 18 - Output Idle state 6 (OC6 output)

pub fn ois5(&mut self) -> OIS5_W<'_>[src]

Bit 16 - Output Idle state 5 (OC5 output)

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn sms_3(&mut self) -> SMS_3_W<'_>[src]

Bit 16 - Slave model selection - bit[3]

pub fn etp(&mut self) -> ETP_W<'_>[src]

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>[src]

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>[src]

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>[src]

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection - bit[2:0]

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tde(&mut self) -> TDE_W<'_>[src]

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>[src]

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>[src]

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>[src]

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>[src]

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>[src]

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>[src]

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>[src]

Bit 5 - COM interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc4of(&mut self) -> CC4OF_W<'_>[src]

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>[src]

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>[src]

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>[src]

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

pub fn b2if(&mut self) -> B2IF_W<'_>[src]

Bit 8 - Break 2 interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn bg(&mut self) -> BG_W<'_>[src]

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>[src]

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>[src]

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>[src]

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

pub fn b2g(&mut self) -> B2G_W<'_>[src]

Bit 8 - Break 2 generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2ce(&mut self) -> OC2CE_W<'_>[src]

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>[src]

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>[src]

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>[src]

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>[src]

pub fn oc4ce(&mut self) -> OC4CE_W<'_>[src]

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>[src]

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>[src]

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>[src]

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>[src]

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>[src]

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>[src]

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>[src]

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/Compare 3 selection

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>[src]

Bit 24 - Output Compare 4 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>[src]

Bit 16 - Output Compare 3 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>[src]

pub fn ic4f(&mut self) -> IC4F_W<'_>[src]

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>[src]

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>[src]

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>[src]

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc4p(&mut self) -> CC4P_W<'_>[src]

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>[src]

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>[src]

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>[src]

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>[src]

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>[src]

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>[src]

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>[src]

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

pub fn cc6p(&mut self) -> CC6P_W<'_>[src]

Bit 21 - Capture/Compare 6 output polarity

pub fn cc6e(&mut self) -> CC6E_W<'_>[src]

Bit 20 - Capture/Compare 6 output enable

pub fn cc5p(&mut self) -> CC5P_W<'_>[src]

Bit 17 - Capture/Compare 5 output polarity

pub fn cc5e(&mut self) -> CC5E_W<'_>[src]

Bit 16 - Capture/Compare 5 output enable

pub fn cc4np(&mut self) -> CC4NP_W<'_>[src]

Bit 15 - Capture/Compare 4 complementary output polarity

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>[src]

pub fn dbl(&mut self) -> DBL_W<'_>[src]

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>[src]

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>[src]

pub fn dmab(&mut self) -> DMAB_W<'_>[src]

Bits 0:31 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>[src]

pub fn rep(&mut self) -> REP_W<'_>[src]

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>[src]

pub fn moe(&mut self) -> MOE_W<'_>[src]

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>[src]

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>[src]

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>[src]

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>[src]

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>[src]

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>[src]

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>[src]

Bits 0:7 - Dead-time generator setup

pub fn bk2p(&mut self) -> BK2P_W<'_>[src]

Bit 25 - Break 2 polarity

pub fn bk2e(&mut self) -> BK2E_W<'_>[src]

Bit 24 - Break 2 enable

pub fn bk2f(&mut self) -> BK2F_W<'_>[src]

Bits 20:23 - Break 2 filter

pub fn bkf(&mut self) -> BKF_W<'_>[src]

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>[src]

pub fn oc5fe(&mut self) -> OC5FE_W<'_>[src]

Bit 2 - Output compare 5 fast enable

pub fn oc5pe(&mut self) -> OC5PE_W<'_>[src]

Bit 3 - Output compare 5 preload enable

pub fn oc5m(&mut self) -> OC5M_W<'_>[src]

Bits 4:6 - Output compare 5 mode

pub fn oc5ce(&mut self) -> OC5CE_W<'_>[src]

Bit 7 - Output compare 5 clear enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>[src]

Bit 10 - Output compare 6 fast enable

pub fn oc6pe(&mut self) -> OC6PE_W<'_>[src]

Bit 11 - Output compare 6 preload enable

pub fn oc6m(&mut self) -> OC6M_W<'_>[src]

Bits 12:14 - Output compare 6 mode

pub fn oc6ce(&mut self) -> OC6CE_W<'_>[src]

Bit 15 - Output compare 6 clear enable

pub fn oc5m3(&mut self) -> OC5M3_W<'_>[src]

Bit 16 - Output Compare 5 mode

pub fn oc6m3(&mut self) -> OC6M3_W<'_>[src]

Bit 24 - Output Compare 6 mode

impl W<u32, Reg<u32, _CCR5>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 5 value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>[src]

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>[src]

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>[src]

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 6 value

impl W<u32, Reg<u32, _SR>>[src]

pub fn ovr(&mut self) -> OVR_W<'_>[src]

Bit 5 - Overrun

pub fn strt(&mut self) -> STRT_W<'_>[src]

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>[src]

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>[src]

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>[src]

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>[src]

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ovrie(&mut self) -> OVRIE_W<'_>[src]

Bit 26 - Overrun interrupt enable

pub fn res(&mut self) -> RES_W<'_>[src]

Bits 24:25 - Resolution

pub fn awden(&mut self) -> AWDEN_W<'_>[src]

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>[src]

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>[src]

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>[src]

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>[src]

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>[src]

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>[src]

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>[src]

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>[src]

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>[src]

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>[src]

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>[src]

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>[src]

pub fn swstart(&mut self) -> SWSTART_W<'_>[src]

Bit 30 - Start conversion of regular channels

pub fn exten(&mut self) -> EXTEN_W<'_>[src]

Bits 28:29 - External trigger enable for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>[src]

Bits 24:27 - External event select for regular group

pub fn jswstart(&mut self) -> JSWSTART_W<'_>[src]

Bit 22 - Start conversion of injected channels

pub fn jexten(&mut self) -> JEXTEN_W<'_>[src]

Bits 20:21 - External trigger enable for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>[src]

Bits 16:19 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>[src]

Bit 11 - Data alignment

pub fn eocs(&mut self) -> EOCS_W<'_>[src]

Bit 10 - End of conversion selection

pub fn dds(&mut self) -> DDS_W<'_>[src]

Bit 9 - DMA disable selection (for single ADC mode)

pub fn dma(&mut self) -> DMA_W<'_>[src]

Bit 8 - Direct memory access mode (for single ADC mode)

pub fn cont(&mut self) -> CONT_W<'_>[src]

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>[src]

Bit 0 - A/D Converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>[src]

pub fn smp18(&mut self) -> SMP18_W<'_>[src]

Bits 24:26 - Channel 18 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>[src]

Bits 21:23 - Channel 17 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>[src]

Bits 18:20 - Channel 16 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>[src]

Bits 15:17 - Channel 15 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>[src]

Bits 12:14 - Channel 14 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>[src]

Bits 9:11 - Channel 13 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>[src]

Bits 6:8 - Channel 12 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>[src]

Bits 3:5 - Channel 11 sampling time selection

pub fn smp10(&mut self) -> SMP10_W<'_>[src]

Bits 0:2 - Channel 10 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>[src]

pub fn smp9(&mut self) -> SMP9_W<'_>[src]

Bits 27:29 - Channel 9 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>[src]

Bits 24:26 - Channel 8 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>[src]

Bits 21:23 - Channel 7 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>[src]

Bits 18:20 - Channel 6 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>[src]

Bits 15:17 - Channel 5 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>[src]

Bits 12:14 - Channel 4 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>[src]

Bits 9:11 - Channel 3 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>[src]

Bits 6:8 - Channel 2 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>[src]

Bits 3:5 - Channel 1 sampling time selection

pub fn smp0(&mut self) -> SMP0_W<'_>[src]

Bits 0:2 - Channel 0 sampling time selection

impl W<u32, Reg<u32, _JOFR>>[src]

pub fn joffset(&mut self) -> JOFFSET_W<'_>[src]

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>[src]

pub fn ht(&mut self) -> HT_W<'_>[src]

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>[src]

pub fn lt(&mut self) -> LT_W<'_>[src]

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>[src]

pub fn l(&mut self) -> L_W<'_>[src]

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>[src]

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>[src]

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>[src]

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>[src]

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>[src]

pub fn sq12(&mut self) -> SQ12_W<'_>[src]

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>[src]

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>[src]

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>[src]

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>[src]

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>[src]

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>[src]

pub fn sq6(&mut self) -> SQ6_W<'_>[src]

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>[src]

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>[src]

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>[src]

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>[src]

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>[src]

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>[src]

pub fn jl(&mut self) -> JL_W<'_>[src]

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>[src]

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>[src]

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>[src]

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>[src]

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _CR1>>[src]

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>[src]

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>[src]

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>[src]

Bit 23 - Temperature sensor and VREFINT enable

pub fn vbate(&mut self) -> VBATE_W<'_>[src]

Bit 22 - VBAT enable

pub fn adcpre(&mut self) -> ADCPRE_W<'_>[src]

Bits 16:17 - ADC prescaler

pub fn dma(&mut self) -> DMA_W<'_>[src]

Bits 14:15 - Direct memory access mode for multi ADC mode

pub fn dds(&mut self) -> DDS_W<'_>[src]

Bit 13 - DMA disable selection for multi-ADC mode

pub fn delay(&mut self) -> DELAY_W<'_>[src]

Bits 8:11 - Delay between 2 sampling phases

pub fn multi(&mut self) -> MULTI_W<'_>[src]

Bits 0:4 - Multi ADC mode selection

impl W<u32, Reg<u32, _TIR>>[src]

pub fn stid(&mut self) -> STID_W<'_>[src]

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>[src]

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>[src]

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>[src]

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>[src]

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>[src]

pub fn time(&mut self) -> TIME_W<'_>[src]

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>[src]

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>[src]

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>[src]

pub fn data3(&mut self) -> DATA3_W<'_>[src]

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>[src]

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>[src]

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>[src]

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>[src]

pub fn data7(&mut self) -> DATA7_W<'_>[src]

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>[src]

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>[src]

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>[src]

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>[src]

pub fn fb0(&mut self) -> FB0_W<'_>[src]

Bit 0 - Filter bits

pub fn fb1(&mut self) -> FB1_W<'_>[src]

Bit 1 - Filter bits

pub fn fb2(&mut self) -> FB2_W<'_>[src]

Bit 2 - Filter bits

pub fn fb3(&mut self) -> FB3_W<'_>[src]

Bit 3 - Filter bits

pub fn fb4(&mut self) -> FB4_W<'_>[src]

Bit 4 - Filter bits

pub fn fb5(&mut self) -> FB5_W<'_>[src]

Bit 5 - Filter bits

pub fn fb6(&mut self) -> FB6_W<'_>[src]

Bit 6 - Filter bits

pub fn fb7(&mut self) -> FB7_W<'_>[src]

Bit 7 - Filter bits

pub fn fb8(&mut self) -> FB8_W<'_>[src]

Bit 8 - Filter bits

pub fn fb9(&mut self) -> FB9_W<'_>[src]

Bit 9 - Filter bits

pub fn fb10(&mut self) -> FB10_W<'_>[src]

Bit 10 - Filter bits

pub fn fb11(&mut self) -> FB11_W<'_>[src]

Bit 11 - Filter bits

pub fn fb12(&mut self) -> FB12_W<'_>[src]

Bit 12 - Filter bits

pub fn fb13(&mut self) -> FB13_W<'_>[src]

Bit 13 - Filter bits

pub fn fb14(&mut self) -> FB14_W<'_>[src]

Bit 14 - Filter bits

pub fn fb15(&mut self) -> FB15_W<'_>[src]

Bit 15 - Filter bits

pub fn fb16(&mut self) -> FB16_W<'_>[src]

Bit 16 - Filter bits

pub fn fb17(&mut self) -> FB17_W<'_>[src]

Bit 17 - Filter bits

pub fn fb18(&mut self) -> FB18_W<'_>[src]

Bit 18 - Filter bits

pub fn fb19(&mut self) -> FB19_W<'_>[src]

Bit 19 - Filter bits

pub fn fb20(&mut self) -> FB20_W<'_>[src]

Bit 20 - Filter bits

pub fn fb21(&mut self) -> FB21_W<'_>[src]

Bit 21 - Filter bits

pub fn fb22(&mut self) -> FB22_W<'_>[src]

Bit 22 - Filter bits

pub fn fb23(&mut self) -> FB23_W<'_>[src]

Bit 23 - Filter bits

pub fn fb24(&mut self) -> FB24_W<'_>[src]

Bit 24 - Filter bits

pub fn fb25(&mut self) -> FB25_W<'_>[src]

Bit 25 - Filter bits

pub fn fb26(&mut self) -> FB26_W<'_>[src]

Bit 26 - Filter bits

pub fn fb27(&mut self) -> FB27_W<'_>[src]

Bit 27 - Filter bits

pub fn fb28(&mut self) -> FB28_W<'_>[src]

Bit 28 - Filter bits

pub fn fb29(&mut self) -> FB29_W<'_>[src]

Bit 29 - Filter bits

pub fn fb30(&mut self) -> FB30_W<'_>[src]

Bit 30 - Filter bits

pub fn fb31(&mut self) -> FB31_W<'_>[src]

Bit 31 - Filter bits

impl W<u32, Reg<u32, _FR2>>[src]

pub fn fb0(&mut self) -> FB0_W<'_>[src]

Bit 0 - Filter bits

pub fn fb1(&mut self) -> FB1_W<'_>[src]

Bit 1 - Filter bits

pub fn fb2(&mut self) -> FB2_W<'_>[src]

Bit 2 - Filter bits

pub fn fb3(&mut self) -> FB3_W<'_>[src]

Bit 3 - Filter bits

pub fn fb4(&mut self) -> FB4_W<'_>[src]

Bit 4 - Filter bits

pub fn fb5(&mut self) -> FB5_W<'_>[src]

Bit 5 - Filter bits

pub fn fb6(&mut self) -> FB6_W<'_>[src]

Bit 6 - Filter bits

pub fn fb7(&mut self) -> FB7_W<'_>[src]

Bit 7 - Filter bits

pub fn fb8(&mut self) -> FB8_W<'_>[src]

Bit 8 - Filter bits

pub fn fb9(&mut self) -> FB9_W<'_>[src]

Bit 9 - Filter bits

pub fn fb10(&mut self) -> FB10_W<'_>[src]

Bit 10 - Filter bits

pub fn fb11(&mut self) -> FB11_W<'_>[src]

Bit 11 - Filter bits

pub fn fb12(&mut self) -> FB12_W<'_>[src]

Bit 12 - Filter bits

pub fn fb13(&mut self) -> FB13_W<'_>[src]

Bit 13 - Filter bits

pub fn fb14(&mut self) -> FB14_W<'_>[src]

Bit 14 - Filter bits

pub fn fb15(&mut self) -> FB15_W<'_>[src]

Bit 15 - Filter bits

pub fn fb16(&mut self) -> FB16_W<'_>[src]

Bit 16 - Filter bits

pub fn fb17(&mut self) -> FB17_W<'_>[src]

Bit 17 - Filter bits

pub fn fb18(&mut self) -> FB18_W<'_>[src]

Bit 18 - Filter bits

pub fn fb19(&mut self) -> FB19_W<'_>[src]

Bit 19 - Filter bits

pub fn fb20(&mut self) -> FB20_W<'_>[src]

Bit 20 - Filter bits

pub fn fb21(&mut self) -> FB21_W<'_>[src]

Bit 21 - Filter bits

pub fn fb22(&mut self) -> FB22_W<'_>[src]

Bit 22 - Filter bits

pub fn fb23(&mut self) -> FB23_W<'_>[src]

Bit 23 - Filter bits

pub fn fb24(&mut self) -> FB24_W<'_>[src]

Bit 24 - Filter bits

pub fn fb25(&mut self) -> FB25_W<'_>[src]

Bit 25 - Filter bits

pub fn fb26(&mut self) -> FB26_W<'_>[src]

Bit 26 - Filter bits

pub fn fb27(&mut self) -> FB27_W<'_>[src]

Bit 27 - Filter bits

pub fn fb28(&mut self) -> FB28_W<'_>[src]

Bit 28 - Filter bits

pub fn fb29(&mut self) -> FB29_W<'_>[src]

Bit 29 - Filter bits

pub fn fb30(&mut self) -> FB30_W<'_>[src]

Bit 30 - Filter bits

pub fn fb31(&mut self) -> FB31_W<'_>[src]

Bit 31 - Filter bits

impl W<u32, Reg<u32, _MCR>>[src]

pub fn dbf(&mut self) -> DBF_W<'_>[src]

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>[src]

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>[src]

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>[src]

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>[src]

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>[src]

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>[src]

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>[src]

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>[src]

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>[src]

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>[src]

pub fn slaki(&mut self) -> SLAKI_W<'_>[src]

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>[src]

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>[src]

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>[src]

pub fn abrq2(&mut self) -> ABRQ2_W<'_>[src]

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>[src]

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>[src]

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>[src]

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>[src]

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>[src]

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>[src]

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>[src]

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>[src]

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>[src]

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>[src]

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>[src]

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>[src]

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>[src]

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>[src]

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>[src]

pub fn rfom(&mut self) -> RFOM_W<'_>[src]

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>[src]

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>[src]

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>[src]

pub fn slkie(&mut self) -> SLKIE_W<'_>[src]

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>[src]

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>[src]

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>[src]

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>[src]

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>[src]

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>[src]

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>[src]

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>[src]

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>[src]

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>[src]

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>[src]

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>[src]

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>[src]

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>[src]

pub fn lec(&mut self) -> LEC_W<'_>[src]

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>[src]

pub fn silm(&mut self) -> SILM_W<'_>[src]

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>[src]

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>[src]

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>[src]

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>[src]

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>[src]

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>[src]

pub fn finit(&mut self) -> FINIT_W<'_>[src]

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>[src]

pub fn fbm0(&mut self) -> FBM0_W<'_>[src]

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>[src]

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>[src]

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>[src]

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>[src]

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>[src]

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>[src]

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>[src]

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>[src]

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>[src]

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>[src]

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>[src]

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>[src]

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>[src]

Bit 13 - Filter mode

impl W<u32, Reg<u32, _FS1R>>[src]

pub fn fsc0(&mut self) -> FSC0_W<'_>[src]

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>[src]

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>[src]

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>[src]

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>[src]

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>[src]

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>[src]

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>[src]

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>[src]

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>[src]

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>[src]

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>[src]

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>[src]

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>[src]

Bit 13 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>[src]

pub fn ffa0(&mut self) -> FFA0_W<'_>[src]

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>[src]

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>[src]

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>[src]

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>[src]

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>[src]

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>[src]

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>[src]

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>[src]

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>[src]

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>[src]

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>[src]

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>[src]

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>[src]

Bit 13 - Filter FIFO assignment for filter 13

impl W<u32, Reg<u32, _FA1R>>[src]

pub fn fact0(&mut self) -> FACT0_W<'_>[src]

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>[src]

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>[src]

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>[src]

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>[src]

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>[src]

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>[src]

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>[src]

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>[src]

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>[src]

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>[src]

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>[src]

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>[src]

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>[src]

Bit 13 - Filter active

impl W<u32, Reg<u32, _DR>>[src]

pub fn dr(&mut self) -> DR_W<'_>[src]

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>[src]

pub fn idr(&mut self) -> IDR_W<'_>[src]

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>[src]

pub fn reset(&mut self) -> RESET_W<'_>[src]

Bit 0 - RESET bit

pub fn polysize(&mut self) -> POLYSIZE_W<'_>[src]

Bits 3:4 - Polynomial size

pub fn rev_in(&mut self) -> REV_IN_W<'_>[src]

Bits 5:6 - Reverse input data

pub fn rev_out(&mut self) -> REV_OUT_W<'_>[src]

Bit 7 - Reverse output data

impl W<u32, Reg<u32, _INIT>>[src]

pub fn init(&mut self) -> INIT_W<'_>[src]

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>[src]

pub fn pol(&mut self) -> POL_W<'_>[src]

Bits 0:31 - Programmable polynomial

impl W<u8, Reg<u8, _DR8>>[src]

pub fn dr8(&mut self) -> DR8_W<'_>[src]

Bits 0:7 - Data register bits

impl W<u16, Reg<u16, _DR16>>[src]

pub fn dr16(&mut self) -> DR16_W<'_>[src]

Bits 0:15 - Data register bits

impl W<u32, Reg<u32, _CR>>[src]

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>[src]

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>[src]

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>[src]

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>[src]

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>[src]

Bits 6:7 - TRACE_MODE

impl W<u32, Reg<u32, _APB1_FZ>>[src]

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>[src]

Bit 0 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>[src]

Bit 1 - DBG_TIM3 _STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>[src]

Bit 2 - DBG_TIM4_STOP

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>[src]

Bit 3 - DBG_TIM5_STOP

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>[src]

Bit 4 - DBG_TIM6_STOP

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>[src]

Bit 5 - DBG_TIM7_STOP

pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<'_>[src]

Bit 6 - DBG_TIM12_STOP

pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<'_>[src]

Bit 7 - DBG_TIM13_STOP

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>[src]

Bit 8 - DBG_TIM14_STOP

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>[src]

Bit 11 - DBG_WWDG_STOP

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>[src]

Bit 12 - DBG_IWDEG_STOP

pub fn dbg_j2c1_smbus_timeout(&mut self) -> DBG_J2C1_SMBUS_TIMEOUT_W<'_>[src]

Bit 21 - DBG_J2C1_SMBUS_TIMEOUT

pub fn dbg_j2c2_smbus_timeout(&mut self) -> DBG_J2C2_SMBUS_TIMEOUT_W<'_>[src]

Bit 22 - DBG_J2C2_SMBUS_TIMEOUT

pub fn dbg_j2c3smbus_timeout(&mut self) -> DBG_J2C3SMBUS_TIMEOUT_W<'_>[src]

Bit 23 - DBG_J2C3SMBUS_TIMEOUT

pub fn dbg_can1_stop(&mut self) -> DBG_CAN1_STOP_W<'_>[src]

Bit 25 - DBG_CAN1_STOP

pub fn dbg_can2_stop(&mut self) -> DBG_CAN2_STOP_W<'_>[src]

Bit 26 - DBG_CAN2_STOP

impl W<u32, Reg<u32, _APB2_FZ>>[src]

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>[src]

Bit 0 - TIM1 counter stopped when core is halted

pub fn dbg_tim8_stop(&mut self) -> DBG_TIM8_STOP_W<'_>[src]

Bit 1 - TIM8 counter stopped when core is halted

pub fn dbg_tim9_stop(&mut self) -> DBG_TIM9_STOP_W<'_>[src]

Bit 16 - TIM9 counter stopped when core is halted

pub fn dbg_tim10_stop(&mut self) -> DBG_TIM10_STOP_W<'_>[src]

Bit 17 - TIM10 counter stopped when core is halted

pub fn dbg_tim11_stop(&mut self) -> DBG_TIM11_STOP_W<'_>[src]

Bit 18 - TIM11 counter stopped when core is halted

impl W<u32, Reg<u32, _CR>>[src]

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>[src]

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>[src]

Bit 28 - DAC channel2 DMA enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>[src]

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn wave2(&mut self) -> WAVE2_W<'_>[src]

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>[src]

Bits 19:21 - DAC channel2 trigger selection

pub fn ten2(&mut self) -> TEN2_W<'_>[src]

Bit 18 - DAC channel2 trigger enable

pub fn boff2(&mut self) -> BOFF2_W<'_>[src]

Bit 17 - DAC channel2 output buffer disable

pub fn en2(&mut self) -> EN2_W<'_>[src]

Bit 16 - DAC channel2 enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>[src]

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>[src]

Bit 12 - DAC channel1 DMA enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>[src]

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn wave1(&mut self) -> WAVE1_W<'_>[src]

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>[src]

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>[src]

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>[src]

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>[src]

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>[src]

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>[src]

Bit 1 - DAC channel2 software trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>[src]

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>[src]

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>[src]

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>[src]

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 16:27 - DAC channel2 12-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 20:31 - DAC channel2 12-bit left-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 8:15 - DAC channel2 8-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>[src]

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>[src]

Bit 29 - DAC channel2 DMA underrun flag

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>[src]

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _CR>>[src]

pub fn chsel(&mut self) -> CHSEL_W<'_>[src]

Bits 25:28 - Channel selection

pub fn mburst(&mut self) -> MBURST_W<'_>[src]

Bits 23:24 - Memory burst transfer configuration

pub fn pburst(&mut self) -> PBURST_W<'_>[src]

Bits 21:22 - Peripheral burst transfer configuration

pub fn ct(&mut self) -> CT_W<'_>[src]

Bit 19 - Current target (only in double buffer mode)

pub fn dbm(&mut self) -> DBM_W<'_>[src]

Bit 18 - Double buffer mode

pub fn pl(&mut self) -> PL_W<'_>[src]

Bits 16:17 - Priority level

pub fn pincos(&mut self) -> PINCOS_W<'_>[src]

Bit 15 - Peripheral increment offset size

pub fn msize(&mut self) -> MSIZE_W<'_>[src]

Bits 13:14 - Memory data size

pub fn psize(&mut self) -> PSIZE_W<'_>[src]

Bits 11:12 - Peripheral data size

pub fn minc(&mut self) -> MINC_W<'_>[src]

Bit 10 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>[src]

Bit 9 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>[src]

Bit 8 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bits 6:7 - Data transfer direction

pub fn pfctrl(&mut self) -> PFCTRL_W<'_>[src]

Bit 5 - Peripheral flow controller

pub fn tcie(&mut self) -> TCIE_W<'_>[src]

Bit 4 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>[src]

Bit 3 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>[src]

Bit 2 - Transfer error interrupt enable

pub fn dmeie(&mut self) -> DMEIE_W<'_>[src]

Bit 1 - Direct mode error interrupt enable

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - Stream enable / flag stream ready when read low

impl W<u32, Reg<u32, _NDTR>>[src]

pub fn ndt(&mut self) -> NDT_W<'_>[src]

Bits 0:15 - Number of data items to transfer

impl W<u32, Reg<u32, _PAR>>[src]

pub fn pa(&mut self) -> PA_W<'_>[src]

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _M0AR>>[src]

pub fn m0a(&mut self) -> M0A_W<'_>[src]

Bits 0:31 - Memory 0 address

impl W<u32, Reg<u32, _M1AR>>[src]

pub fn m1a(&mut self) -> M1A_W<'_>[src]

Bits 0:31 - Memory 1 address (used in case of Double buffer mode)

impl W<u32, Reg<u32, _FCR>>[src]

pub fn feie(&mut self) -> FEIE_W<'_>[src]

Bit 7 - FIFO error interrupt enable

pub fn dmdis(&mut self) -> DMDIS_W<'_>[src]

Bit 2 - Direct mode disable

pub fn fth(&mut self) -> FTH_W<'_>[src]

Bits 0:1 - FIFO threshold selection

impl W<u32, Reg<u32, _LIFCR>>[src]

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>[src]

Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>[src]

Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>[src]

Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif3(&mut self) -> CDMEIF3_W<'_>[src]

Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif3(&mut self) -> CFEIF3_W<'_>[src]

Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>[src]

Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>[src]

Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>[src]

Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif2(&mut self) -> CDMEIF2_W<'_>[src]

Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif2(&mut self) -> CFEIF2_W<'_>[src]

Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>[src]

Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>[src]

Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>[src]

Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif1(&mut self) -> CDMEIF1_W<'_>[src]

Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif1(&mut self) -> CFEIF1_W<'_>[src]

Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif0(&mut self) -> CTCIF0_W<'_>[src]

Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif0(&mut self) -> CHTIF0_W<'_>[src]

Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif0(&mut self) -> CTEIF0_W<'_>[src]

Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif0(&mut self) -> CDMEIF0_W<'_>[src]

Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif0(&mut self) -> CFEIF0_W<'_>[src]

Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)

impl W<u32, Reg<u32, _HIFCR>>[src]

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>[src]

Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>[src]

Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif7(&mut self) -> CTEIF7_W<'_>[src]

Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif7(&mut self) -> CDMEIF7_W<'_>[src]

Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif7(&mut self) -> CFEIF7_W<'_>[src]

Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>[src]

Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>[src]

Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>[src]

Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif6(&mut self) -> CDMEIF6_W<'_>[src]

Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif6(&mut self) -> CFEIF6_W<'_>[src]

Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>[src]

Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>[src]

Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>[src]

Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif5(&mut self) -> CDMEIF5_W<'_>[src]

Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif5(&mut self) -> CFEIF5_W<'_>[src]

Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>[src]

Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>[src]

Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>[src]

Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif4(&mut self) -> CDMEIF4_W<'_>[src]

Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif4(&mut self) -> CFEIF4_W<'_>[src]

Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)

impl W<u32, Reg<u32, _IMR>>[src]

pub fn im0(&mut self) -> IM0_W<'_>[src]

Bit 0 - Interrupt Mask on line 0

pub fn im1(&mut self) -> IM1_W<'_>[src]

Bit 1 - Interrupt Mask on line 1

pub fn im2(&mut self) -> IM2_W<'_>[src]

Bit 2 - Interrupt Mask on line 2

pub fn im3(&mut self) -> IM3_W<'_>[src]

Bit 3 - Interrupt Mask on line 3

pub fn im4(&mut self) -> IM4_W<'_>[src]

Bit 4 - Interrupt Mask on line 4

pub fn im5(&mut self) -> IM5_W<'_>[src]

Bit 5 - Interrupt Mask on line 5

pub fn im6(&mut self) -> IM6_W<'_>[src]

Bit 6 - Interrupt Mask on line 6

pub fn im7(&mut self) -> IM7_W<'_>[src]

Bit 7 - Interrupt Mask on line 7

pub fn im8(&mut self) -> IM8_W<'_>[src]

Bit 8 - Interrupt Mask on line 8

pub fn mi9(&mut self) -> MI9_W<'_>[src]

Bit 9 - Interrupt Mask on line 9

pub fn im10(&mut self) -> IM10_W<'_>[src]

Bit 10 - Interrupt Mask on line 10

pub fn im11(&mut self) -> IM11_W<'_>[src]

Bit 11 - Interrupt Mask on line 11

pub fn im12(&mut self) -> IM12_W<'_>[src]

Bit 12 - Interrupt Mask on line 12

pub fn im13(&mut self) -> IM13_W<'_>[src]

Bit 13 - Interrupt Mask on line 13

pub fn im14(&mut self) -> IM14_W<'_>[src]

Bit 14 - Interrupt Mask on line 14

pub fn im15(&mut self) -> IM15_W<'_>[src]

Bit 15 - Interrupt Mask on line 15

pub fn im16(&mut self) -> IM16_W<'_>[src]

Bit 16 - Interrupt Mask on line 16

pub fn im17(&mut self) -> IM17_W<'_>[src]

Bit 17 - Interrupt Mask on line 17

pub fn im18(&mut self) -> IM18_W<'_>[src]

Bit 18 - Interrupt Mask on line 18

pub fn im19(&mut self) -> IM19_W<'_>[src]

Bit 19 - Interrupt Mask on line 19

pub fn im20(&mut self) -> IM20_W<'_>[src]

Bit 20 - Interrupt Mask on line 20

pub fn im21(&mut self) -> IM21_W<'_>[src]

Bit 21 - Interrupt Mask on line 21

pub fn im22(&mut self) -> IM22_W<'_>[src]

Bit 22 - Interrupt Mask on line 22

pub fn im23(&mut self) -> IM23_W<'_>[src]

Bit 23 - Interrupt Mask on line 23

impl W<u32, Reg<u32, _EMR>>[src]

pub fn em0(&mut self) -> EM0_W<'_>[src]

Bit 0 - Event Mask on line 0

pub fn em1(&mut self) -> EM1_W<'_>[src]

Bit 1 - Event Mask on line 1

pub fn em2(&mut self) -> EM2_W<'_>[src]

Bit 2 - Event Mask on line 2

pub fn em3(&mut self) -> EM3_W<'_>[src]

Bit 3 - Event Mask on line 3

pub fn em4(&mut self) -> EM4_W<'_>[src]

Bit 4 - Event Mask on line 4

pub fn em5(&mut self) -> EM5_W<'_>[src]

Bit 5 - Event Mask on line 5

pub fn em6(&mut self) -> EM6_W<'_>[src]

Bit 6 - Event Mask on line 6

pub fn em7(&mut self) -> EM7_W<'_>[src]

Bit 7 - Event Mask on line 7

pub fn em8(&mut self) -> EM8_W<'_>[src]

Bit 8 - Event Mask on line 8

pub fn em9(&mut self) -> EM9_W<'_>[src]

Bit 9 - Event Mask on line 9

pub fn em10(&mut self) -> EM10_W<'_>[src]

Bit 10 - Event Mask on line 10

pub fn em11(&mut self) -> EM11_W<'_>[src]

Bit 11 - Event Mask on line 11

pub fn em12(&mut self) -> EM12_W<'_>[src]

Bit 12 - Event Mask on line 12

pub fn em13(&mut self) -> EM13_W<'_>[src]

Bit 13 - Event Mask on line 13

pub fn em14(&mut self) -> EM14_W<'_>[src]

Bit 14 - Event Mask on line 14

pub fn em15(&mut self) -> EM15_W<'_>[src]

Bit 15 - Event Mask on line 15

pub fn em16(&mut self) -> EM16_W<'_>[src]

Bit 16 - Event Mask on line 16

pub fn em17(&mut self) -> EM17_W<'_>[src]

Bit 17 - Event Mask on line 17

pub fn em18(&mut self) -> EM18_W<'_>[src]

Bit 18 - Event Mask on line 18

pub fn em19(&mut self) -> EM19_W<'_>[src]

Bit 19 - Event Mask on line 19

pub fn em20(&mut self) -> EM20_W<'_>[src]

Bit 20 - Event Mask on line 20

pub fn em21(&mut self) -> EM21_W<'_>[src]

Bit 21 - Event Mask on line 21

pub fn em22(&mut self) -> EM22_W<'_>[src]

Bit 22 - Event Mask on line 22

pub fn em23(&mut self) -> EM23_W<'_>[src]

Bit 23 - Event Mask on line 23

impl W<u32, Reg<u32, _RTSR>>[src]

pub fn tr0(&mut self) -> TR0_W<'_>[src]

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>[src]

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>[src]

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>[src]

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>[src]

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>[src]

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>[src]

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>[src]

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>[src]

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>[src]

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>[src]

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>[src]

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>[src]

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>[src]

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>[src]

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>[src]

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>[src]

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>[src]

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>[src]

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>[src]

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>[src]

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>[src]

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>[src]

Bit 22 - Rising trigger event configuration of line 22

pub fn tr23(&mut self) -> TR23_W<'_>[src]

Bit 23 - Rising trigger event configuration of line 23

impl W<u32, Reg<u32, _FTSR>>[src]

pub fn tr0(&mut self) -> TR0_W<'_>[src]

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>[src]

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>[src]

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>[src]

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>[src]

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>[src]

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>[src]

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>[src]

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>[src]

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>[src]

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>[src]

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>[src]

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>[src]

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>[src]

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>[src]

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>[src]

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>[src]

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>[src]

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>[src]

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>[src]

Bit 19 - Falling trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>[src]

Bit 20 - Falling trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>[src]

Bit 21 - Falling trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>[src]

Bit 22 - Falling trigger event configuration of line 22

pub fn tr23(&mut self) -> TR23_W<'_>[src]

Bit 23 - Falling trigger event configuration of line 23

impl W<u32, Reg<u32, _SWIER>>[src]

pub fn swier0(&mut self) -> SWIER0_W<'_>[src]

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>[src]

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>[src]

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>[src]

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>[src]

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>[src]

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>[src]

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>[src]

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>[src]

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>[src]

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>[src]

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>[src]

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>[src]

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>[src]

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>[src]

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>[src]

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>[src]

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>[src]

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>[src]

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>[src]

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>[src]

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>[src]

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>[src]

Bit 22 - Software Interrupt on line 22

pub fn swier23(&mut self) -> SWIER23_W<'_>[src]

Bit 23 - Software Interrupt on line 22

impl W<u32, Reg<u32, _PR>>[src]

pub fn pr0(&mut self) -> PR0_W<'_>[src]

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>[src]

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>[src]

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>[src]

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>[src]

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>[src]

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>[src]

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>[src]

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>[src]

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>[src]

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>[src]

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>[src]

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>[src]

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>[src]

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>[src]

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>[src]

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>[src]

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>[src]

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>[src]

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>[src]

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>[src]

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>[src]

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>[src]

Bit 22 - Pending bit 22

pub fn pr23(&mut self) -> PR23_W<'_>[src]

Bit 23 - Pending bit 23

impl W<u32, Reg<u32, _ACR>>[src]

pub fn latency(&mut self) -> LATENCY_W<'_>[src]

Bits 0:3 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>[src]

Bit 8 - Prefetch enable

pub fn arten(&mut self) -> ARTEN_W<'_>[src]

Bit 9 - ART Accelerator Enable

pub fn artrst(&mut self) -> ARTRST_W<'_>[src]

Bit 11 - ART Accelerator reset

impl W<u32, Reg<u32, _KEYR>>[src]

pub fn key(&mut self) -> KEY_W<'_>[src]

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>[src]

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>[src]

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>[src]

pub fn eop(&mut self) -> EOP_W<'_>[src]

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>[src]

Bit 1 - Operation error

pub fn wrperr(&mut self) -> WRPERR_W<'_>[src]

Bit 4 - Write protection error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>[src]

Bit 5 - Programming alignment error

pub fn pgperr(&mut self) -> PGPERR_W<'_>[src]

Bit 6 - Programming parallelism error

pub fn erserr(&mut self) -> ERSERR_W<'_>[src]

Bit 7 - Erase Sequence Error

pub fn rderr(&mut self) -> RDERR_W<'_>[src]

Bit 8 - RDERR

impl W<u32, Reg<u32, _CR>>[src]

pub fn pg(&mut self) -> PG_W<'_>[src]

Bit 0 - Programming

pub fn ser(&mut self) -> SER_W<'_>[src]

Bit 1 - Sector Erase

pub fn mer(&mut self) -> MER_W<'_>[src]

Bit 2 - Mass Erase of sectors 0 to 11

pub fn snb(&mut self) -> SNB_W<'_>[src]

Bits 3:6 - Sector number

pub fn psize(&mut self) -> PSIZE_W<'_>[src]

Bits 8:9 - Program size

pub fn strt(&mut self) -> STRT_W<'_>[src]

Bit 16 - Start

pub fn eopie(&mut self) -> EOPIE_W<'_>[src]

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>[src]

Bit 25 - Error interrupt enable

pub fn lock(&mut self) -> LOCK_W<'_>[src]

Bit 31 - Lock

pub fn rderrie(&mut self) -> RDERRIE_W<'_>[src]

Bit 26 - PCROP error interrupt enable

impl W<u32, Reg<u32, _OPTCR>>[src]

pub fn optlock(&mut self) -> OPTLOCK_W<'_>[src]

Bit 0 - Option lock

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>[src]

Bit 1 - Option start

pub fn bor_lev(&mut self) -> BOR_LEV_W<'_>[src]

Bits 2:3 - BOR reset Level

pub fn iwdg_sw(&mut self) -> IWDG_SW_W<'_>[src]

Bit 5 - WDG_SW User option bytes

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>[src]

Bit 6 - nRST_STOP User option bytes

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>[src]

Bit 7 - nRST_STDBY User option bytes

pub fn rdp(&mut self) -> RDP_W<'_>[src]

Bits 8:15 - Read protect

pub fn n_wrp(&mut self) -> NWRP_W<'_>[src]

Bits 16:23 - Not write protect

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>[src]

Bit 4 - User option bytes

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>[src]

Bit 31 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>[src]

Bit 30 - Independent watchdog counter freeze in standby mode

impl W<u32, Reg<u32, _OPTCR1>>[src]

pub fn boot_add1(&mut self) -> BOOT_ADD1_W<'_>[src]

Bits 16:31 - Boot base address when Boot pin =1

pub fn boot_add0(&mut self) -> BOOT_ADD0_W<'_>[src]

Bits 0:15 - Boot base address when Boot pin =0

impl W<u32, Reg<u32, _OPTCR2>>[src]

pub fn pcrop_rdp(&mut self) -> PCROP_RDP_W<'_>[src]

Bit 31 - PCROP zone preserved when RDP level decreased

pub fn pcropi(&mut self) -> PCROPI_W<'_>[src]

Bits 0:7 - PCROP option byte

impl W<u32, Reg<u32, _BCR1>>[src]

pub fn cclken(&mut self) -> CCLKEN_W<'_>[src]

Bit 20 - CCLKEN

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>[src]

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>[src]

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>[src]

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>[src]

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>[src]

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>[src]

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>[src]

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>[src]

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>[src]

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>[src]

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>[src]

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>[src]

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>[src]

Bit 0 - MBKEN

pub fn wfdis(&mut self) -> WFDIS_W<'_>[src]

Bit 21 - Write FIFO Disable

pub fn cpsize(&mut self) -> CPSIZE_W<'_>[src]

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BTR>>[src]

pub fn accmod(&mut self) -> ACCMOD_W<'_>[src]

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>[src]

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>[src]

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>[src]

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>[src]

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>[src]

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>[src]

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR>>[src]

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>[src]

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>[src]

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>[src]

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>[src]

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>[src]

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>[src]

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>[src]

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>[src]

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>[src]

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>[src]

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>[src]

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>[src]

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>[src]

Bit 0 - MBKEN

pub fn cpsize(&mut self) -> CPSIZE_W<'_>[src]

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _PCR>>[src]

pub fn eccps(&mut self) -> ECCPS_W<'_>[src]

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>[src]

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>[src]

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>[src]

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>[src]

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>[src]

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>[src]

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>[src]

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR>>[src]

pub fn ifen(&mut self) -> IFEN_W<'_>[src]

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>[src]

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>[src]

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>[src]

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>[src]

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>[src]

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM>>[src]

pub fn memhiz(&mut self) -> MEMHIZ_W<'_>[src]

Bits 24:31 - MEMHIZx

pub fn memhold(&mut self) -> MEMHOLD_W<'_>[src]

Bits 16:23 - MEMHOLDx

pub fn memwait(&mut self) -> MEMWAIT_W<'_>[src]

Bits 8:15 - MEMWAITx

pub fn memset(&mut self) -> MEMSET_W<'_>[src]

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT>>[src]

pub fn atthiz(&mut self) -> ATTHIZ_W<'_>[src]

Bits 24:31 - ATTHIZx

pub fn atthold(&mut self) -> ATTHOLD_W<'_>[src]

Bits 16:23 - ATTHOLDx

pub fn attwait(&mut self) -> ATTWAIT_W<'_>[src]

Bits 8:15 - ATTWAITx

pub fn attset(&mut self) -> ATTSET_W<'_>[src]

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _BWTR>>[src]

pub fn accmod(&mut self) -> ACCMOD_W<'_>[src]

Bits 28:29 - ACCMOD

pub fn datast(&mut self) -> DATAST_W<'_>[src]

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>[src]

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>[src]

Bits 0:3 - ADDSET

pub fn busturn(&mut self) -> BUSTURN_W<'_>[src]

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _SDCR>>[src]

pub fn nc(&mut self) -> NC_W<'_>[src]

Bits 0:1 - Number of column address bits

pub fn nr(&mut self) -> NR_W<'_>[src]

Bits 2:3 - Number of row address bits

pub fn mwid(&mut self) -> MWID_W<'_>[src]

Bits 4:5 - Memory data bus width

pub fn nb(&mut self) -> NB_W<'_>[src]

Bit 6 - Number of internal banks

pub fn cas(&mut self) -> CAS_W<'_>[src]

Bits 7:8 - CAS latency

pub fn wp(&mut self) -> WP_W<'_>[src]

Bit 9 - Write protection

pub fn sdclk(&mut self) -> SDCLK_W<'_>[src]

Bits 10:11 - SDRAM clock configuration

pub fn rburst(&mut self) -> RBURST_W<'_>[src]

Bit 12 - Burst read

pub fn rpipe(&mut self) -> RPIPE_W<'_>[src]

Bits 13:14 - Read pipe

impl W<u32, Reg<u32, _SDTR>>[src]

pub fn tmrd(&mut self) -> TMRD_W<'_>[src]

Bits 0:3 - Load Mode Register to Active

pub fn txsr(&mut self) -> TXSR_W<'_>[src]

Bits 4:7 - Exit self-refresh delay

pub fn tras(&mut self) -> TRAS_W<'_>[src]

Bits 8:11 - Self refresh time

pub fn trc(&mut self) -> TRC_W<'_>[src]

Bits 12:15 - Row cycle delay

pub fn twr(&mut self) -> TWR_W<'_>[src]

Bits 16:19 - Recovery delay

pub fn trp(&mut self) -> TRP_W<'_>[src]

Bits 20:23 - Row precharge delay

pub fn trcd(&mut self) -> TRCD_W<'_>[src]

Bits 24:27 - Row to column delay

impl W<u32, Reg<u32, _SDCMR>>[src]

pub fn mode(&mut self) -> MODE_W<'_>[src]

Bits 0:2 - Command mode

pub fn ctb2(&mut self) -> CTB2_W<'_>[src]

Bit 3 - Command target bank 2

pub fn ctb1(&mut self) -> CTB1_W<'_>[src]

Bit 4 - Command target bank 1

pub fn nrfs(&mut self) -> NRFS_W<'_>[src]

Bits 5:8 - Number of Auto-refresh

pub fn mrd(&mut self) -> MRD_W<'_>[src]

Bits 9:21 - Mode Register definition

impl W<u32, Reg<u32, _SDRTR>>[src]

pub fn cre(&mut self) -> CRE_W<'_>[src]

Bit 0 - Clear Refresh error flag

pub fn count(&mut self) -> COUNT_W<'_>[src]

Bits 1:13 - Refresh Timer Count

pub fn reie(&mut self) -> REIE_W<'_>[src]

Bit 14 - RES Interrupt Enable

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>[src]

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>[src]

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:14 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:6 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>[src]

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>[src]

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>[src]

pub fn ti1s(&mut self) -> TI1S_W<'_>[src]

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>[src]

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>[src]

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>[src]

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>[src]

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>[src]

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>[src]

Bit 16 - Slave model selection - bit[3]

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tde(&mut self) -> TDE_W<'_>[src]

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>[src]

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>[src]

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>[src]

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>[src]

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc4of(&mut self) -> CC4OF_W<'_>[src]

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>[src]

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>[src]

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>[src]

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2ce(&mut self) -> OC2CE_W<'_>[src]

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>[src]

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - CC1S

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>[src]

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>[src]

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>[src]

pub fn oc4ce(&mut self) -> OC4CE_W<'_>[src]

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>[src]

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>[src]

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>[src]

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>[src]

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>[src]

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>[src]

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>[src]

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - CC3S

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>[src]

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>[src]

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>[src]

pub fn ic4f(&mut self) -> IC4F_W<'_>[src]

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>[src]

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>[src]

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>[src]

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc4np(&mut self) -> CC4NP_W<'_>[src]

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>[src]

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>[src]

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>[src]

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>[src]

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>[src]

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>[src]

pub fn dbl(&mut self) -> DBL_W<'_>[src]

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>[src]

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>[src]

pub fn dmab(&mut self) -> DMAB_W<'_>[src]

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>[src]

pub fn itr1_rmp(&mut self) -> ITR1_RMP_W<'_>[src]

Bits 10:11 - Internal trigger 1 remap

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>[src]

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>[src]

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>[src]

pub fn ti1s(&mut self) -> TI1S_W<'_>[src]

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>[src]

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>[src]

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>[src]

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>[src]

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>[src]

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>[src]

Bit 16 - Slave model selection - bit[3]

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tde(&mut self) -> TDE_W<'_>[src]

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>[src]

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>[src]

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>[src]

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>[src]

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc4of(&mut self) -> CC4OF_W<'_>[src]

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>[src]

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>[src]

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>[src]

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2ce(&mut self) -> OC2CE_W<'_>[src]

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>[src]

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - CC1S

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>[src]

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>[src]

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>[src]

pub fn oc4ce(&mut self) -> OC4CE_W<'_>[src]

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>[src]

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>[src]

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>[src]

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>[src]

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>[src]

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>[src]

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>[src]

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - CC3S

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>[src]

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>[src]

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>[src]

pub fn ic4f(&mut self) -> IC4F_W<'_>[src]

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>[src]

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>[src]

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>[src]

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc4np(&mut self) -> CC4NP_W<'_>[src]

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>[src]

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>[src]

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>[src]

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>[src]

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>[src]

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt_h(&mut self) -> CNT_H_W<'_>[src]

Bits 16:31 - High counter value

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr_h(&mut self) -> ARR_H_W<'_>[src]

Bits 16:31 - High Auto-reload value

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>[src]

Bits 16:31 - High Capture/Compare 1 value

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>[src]

pub fn dbl(&mut self) -> DBL_W<'_>[src]

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>[src]

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>[src]

pub fn dmab(&mut self) -> DMAB_W<'_>[src]

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>[src]

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>[src]

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>[src]

pub fn ti1s(&mut self) -> TI1S_W<'_>[src]

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>[src]

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn etf(&mut self) -> ETF_W<'_>[src]

Bits 8:11 - External trigger filter

pub fn etps(&mut self) -> ETPS_W<'_>[src]

Bits 12:13 - External trigger prescaler

pub fn ece(&mut self) -> ECE_W<'_>[src]

Bit 14 - External clock enable

pub fn etp(&mut self) -> ETP_W<'_>[src]

Bit 15 - External trigger polarity

pub fn sms_3(&mut self) -> SMS_3_W<'_>[src]

Bit 16 - Slave model selection - bit[3]

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tde(&mut self) -> TDE_W<'_>[src]

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>[src]

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>[src]

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>[src]

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>[src]

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc4of(&mut self) -> CC4OF_W<'_>[src]

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>[src]

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>[src]

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>[src]

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2ce(&mut self) -> OC2CE_W<'_>[src]

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>[src]

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - CC1S

pub fn oc2m_3(&mut self) -> OC2M_3_W<'_>[src]

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>[src]

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>[src]

pub fn oc4ce(&mut self) -> OC4CE_W<'_>[src]

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>[src]

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>[src]

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>[src]

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>[src]

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>[src]

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>[src]

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>[src]

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - CC3S

pub fn oc4m_3(&mut self) -> OC4M_3_W<'_>[src]

Bit 24 - Output Compare 2 mode - bit 3

pub fn oc3m_3(&mut self) -> OC3M_3_W<'_>[src]

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR2_INPUT>>[src]

pub fn ic4f(&mut self) -> IC4F_W<'_>[src]

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>[src]

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>[src]

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>[src]

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc4np(&mut self) -> CC4NP_W<'_>[src]

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>[src]

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>[src]

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>[src]

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>[src]

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>[src]

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>[src]

pub fn dbl(&mut self) -> DBL_W<'_>[src]

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>[src]

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>[src]

pub fn dmab(&mut self) -> DMAB_W<'_>[src]

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>[src]

pub fn ti4_rmp(&mut self) -> TI4_RMP_W<'_>[src]

Bits 6:7 - Timer Input 4 remap

impl W<u32, Reg<u32, _MODER>>[src]

pub fn moder15(&mut self) -> MODER15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>[src]

pub fn ot15(&mut self) -> OT15_W<'_>[src]

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>[src]

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>[src]

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>[src]

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>[src]

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>[src]

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>[src]

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>[src]

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>[src]

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>[src]

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>[src]

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>[src]

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>[src]

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>[src]

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>[src]

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>[src]

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>[src]

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>[src]

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>[src]

pub fn odr15(&mut self) -> ODR15_W<'_>[src]

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>[src]

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>[src]

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>[src]

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>[src]

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>[src]

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>[src]

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>[src]

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>[src]

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>[src]

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>[src]

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>[src]

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>[src]

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>[src]

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>[src]

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>[src]

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>[src]

pub fn br15(&mut self) -> BR15_W<'_>[src]

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>[src]

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>[src]

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>[src]

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>[src]

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>[src]

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>[src]

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>[src]

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>[src]

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>[src]

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>[src]

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>[src]

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>[src]

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>[src]

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>[src]

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>[src]

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>[src]

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>[src]

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>[src]

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>[src]

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>[src]

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>[src]

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>[src]

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>[src]

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>[src]

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>[src]

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>[src]

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>[src]

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>[src]

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>[src]

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>[src]

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>[src]

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>[src]

pub fn lckk(&mut self) -> LCKK_W<'_>[src]

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>[src]

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>[src]

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>[src]

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>[src]

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>[src]

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>[src]

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>[src]

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>[src]

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>[src]

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>[src]

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>[src]

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>[src]

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>[src]

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>[src]

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>[src]

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>[src]

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>[src]

pub fn afrl7(&mut self) -> AFRL7_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>[src]

pub fn afrh15(&mut self) -> AFRH15_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>[src]

pub fn moder15(&mut self) -> MODER15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>[src]

pub fn ot15(&mut self) -> OT15_W<'_>[src]

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>[src]

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>[src]

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>[src]

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>[src]

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>[src]

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>[src]

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>[src]

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>[src]

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>[src]

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>[src]

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>[src]

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>[src]

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>[src]

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>[src]

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>[src]

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>[src]

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>[src]

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>[src]

pub fn odr15(&mut self) -> ODR15_W<'_>[src]

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>[src]

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>[src]

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>[src]

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>[src]

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>[src]

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>[src]

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>[src]

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>[src]

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>[src]

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>[src]

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>[src]

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>[src]

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>[src]

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>[src]

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>[src]

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>[src]

pub fn br15(&mut self) -> BR15_W<'_>[src]

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>[src]

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>[src]

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>[src]

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>[src]

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>[src]

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>[src]

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>[src]

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>[src]

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>[src]

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>[src]

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>[src]

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>[src]

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>[src]

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>[src]

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>[src]

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>[src]

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>[src]

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>[src]

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>[src]

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>[src]

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>[src]

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>[src]

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>[src]

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>[src]

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>[src]

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>[src]

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>[src]

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>[src]

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>[src]

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>[src]

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>[src]

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>[src]

pub fn lckk(&mut self) -> LCKK_W<'_>[src]

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>[src]

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>[src]

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>[src]

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>[src]

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>[src]

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>[src]

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>[src]

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>[src]

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>[src]

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>[src]

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>[src]

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>[src]

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>[src]

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>[src]

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>[src]

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>[src]

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>[src]

pub fn afrl7(&mut self) -> AFRL7_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>[src]

pub fn afrh15(&mut self) -> AFRH15_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>[src]

pub fn moder15(&mut self) -> MODER15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>[src]

pub fn ot15(&mut self) -> OT15_W<'_>[src]

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>[src]

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>[src]

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>[src]

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>[src]

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>[src]

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>[src]

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>[src]

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>[src]

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>[src]

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>[src]

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>[src]

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>[src]

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>[src]

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>[src]

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>[src]

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>[src]

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>[src]

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>[src]

pub fn odr15(&mut self) -> ODR15_W<'_>[src]

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>[src]

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>[src]

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>[src]

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>[src]

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>[src]

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>[src]

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>[src]

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>[src]

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>[src]

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>[src]

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>[src]

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>[src]

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>[src]

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>[src]

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>[src]

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>[src]

pub fn br15(&mut self) -> BR15_W<'_>[src]

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>[src]

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>[src]

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>[src]

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>[src]

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>[src]

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>[src]

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>[src]

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>[src]

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>[src]

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>[src]

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>[src]

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>[src]

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>[src]

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>[src]

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>[src]

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>[src]

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>[src]

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>[src]

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>[src]

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>[src]

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>[src]

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>[src]

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>[src]

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>[src]

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>[src]

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>[src]

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>[src]

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>[src]

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>[src]

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>[src]

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>[src]

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>[src]

pub fn lckk(&mut self) -> LCKK_W<'_>[src]

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>[src]

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>[src]

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>[src]

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>[src]

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>[src]

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>[src]

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>[src]

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>[src]

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>[src]

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>[src]

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>[src]

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>[src]

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>[src]

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>[src]

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>[src]

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>[src]

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>[src]

pub fn afrl7(&mut self) -> AFRL7_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>[src]

pub fn afrh15(&mut self) -> AFRH15_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

impl W<u32, Reg<u32, _DIER>>[src]

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

pub fn oc1m_3(&mut self) -> OC1M_3_W<'_>[src]

Bit 16 - Output Compare 1 mode - bit 3

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _OR>>[src]

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>[src]

Bits 0:1 - TIM11 Input 1 remapping capability

impl W<u32, Reg<u32, _KR>>[src]

pub fn key(&mut self) -> KEY_W<'_>[src]

Bits 0:15 - Key value (write only, read 0000h)

impl W<u32, Reg<u32, _PR>>[src]

pub fn pr(&mut self) -> PR_W<'_>[src]

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>[src]

pub fn rl(&mut self) -> RL_W<'_>[src]

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>[src]

pub fn win(&mut self) -> WIN_W<'_>[src]

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR1>>[src]

pub fn pe(&mut self) -> PE_W<'_>[src]

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>[src]

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>[src]

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>[src]

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>[src]

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>[src]

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>[src]

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>[src]

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>[src]

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>[src]

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>[src]

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>[src]

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>[src]

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>[src]

Bit 17 - Clock stretching disable

pub fn gcen(&mut self) -> GCEN_W<'_>[src]

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>[src]

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>[src]

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>[src]

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>[src]

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>[src]

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>[src]

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>[src]

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>[src]

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>[src]

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>[src]

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>[src]

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>[src]

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>[src]

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>[src]

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>[src]

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>[src]

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>[src]

pub fn oa1(&mut self) -> OA1_W<'_>[src]

Bits 0:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>[src]

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>[src]

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>[src]

pub fn oa2(&mut self) -> OA2_W<'_>[src]

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>[src]

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>[src]

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>[src]

pub fn scll(&mut self) -> SCLL_W<'_>[src]

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>[src]

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>[src]

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>[src]

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>[src]

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>[src]

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>[src]

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>[src]

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>[src]

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>[src]

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>[src]

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>[src]

pub fn txis(&mut self) -> TXIS_W<'_>[src]

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>[src]

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>[src]

pub fn alertcf(&mut self) -> ALERTCF_W<'_>[src]

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>[src]

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>[src]

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>[src]

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>[src]

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>[src]

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>[src]

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>[src]

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>[src]

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>[src]

pub fn txdata(&mut self) -> TXDATA_W<'_>[src]

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _ICR>>[src]

pub fn downcf(&mut self) -> DOWNCF_W<'_>[src]

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>[src]

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>[src]

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>[src]

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>[src]

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>[src]

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>[src]

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>[src]

pub fn downie(&mut self) -> DOWNIE_W<'_>[src]

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>[src]

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>[src]

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>[src]

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>[src]

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>[src]

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>[src]

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>[src]

pub fn enc(&mut self) -> ENC_W<'_>[src]

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>[src]

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>[src]

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>[src]

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>[src]

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>[src]

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>[src]

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>[src]

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>[src]

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>[src]

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>[src]

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>[src]

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>[src]

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>[src]

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>[src]

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>[src]

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>[src]

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>[src]

pub fn cmp(&mut self) -> CMP_W<'_>[src]

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _CR1>>[src]

pub fn lpds(&mut self) -> LPDS_W<'_>[src]

Bit 0 - Low-power deep sleep

pub fn pdds(&mut self) -> PDDS_W<'_>[src]

Bit 1 - Power down deepsleep

pub fn csbf(&mut self) -> CSBF_W<'_>[src]

Bit 3 - Clear standby flag

pub fn pvde(&mut self) -> PVDE_W<'_>[src]

Bit 4 - Power voltage detector enable

pub fn pls(&mut self) -> PLS_W<'_>[src]

Bits 5:7 - PVD level selection

pub fn dbp(&mut self) -> DBP_W<'_>[src]

Bit 8 - Disable backup domain write protection

pub fn fpds(&mut self) -> FPDS_W<'_>[src]

Bit 9 - Flash power down in Stop mode

pub fn lpuds(&mut self) -> LPUDS_W<'_>[src]

Bit 10 - Low-power regulator in deepsleep under-drive mode

pub fn mruds(&mut self) -> MRUDS_W<'_>[src]

Bit 11 - Main regulator in deepsleep under-drive mode

pub fn adcdc1(&mut self) -> ADCDC1_W<'_>[src]

Bit 13 - ADCDC1

pub fn vos(&mut self) -> VOS_W<'_>[src]

Bits 14:15 - Regulator voltage scaling output selection

pub fn oden(&mut self) -> ODEN_W<'_>[src]

Bit 16 - Over-drive enable

pub fn odswen(&mut self) -> ODSWEN_W<'_>[src]

Bit 17 - Over-drive switching enabled

pub fn uden(&mut self) -> UDEN_W<'_>[src]

Bits 18:19 - Under-drive enable in stop mode

impl W<u32, Reg<u32, _CSR1>>[src]

pub fn bre(&mut self) -> BRE_W<'_>[src]

Bit 9 - Backup regulator enable

pub fn vosrdy(&mut self) -> VOSRDY_W<'_>[src]

Bit 14 - Regulator voltage scaling output selection ready bit

pub fn odrdy(&mut self) -> ODRDY_W<'_>[src]

Bit 16 - Over-drive mode ready

pub fn odswrdy(&mut self) -> ODSWRDY_W<'_>[src]

Bit 17 - Over-drive mode switching ready

pub fn udrdy(&mut self) -> UDRDY_W<'_>[src]

Bits 18:19 - Under-drive ready flag

pub fn eiwup(&mut self) -> EIWUP_W<'_>[src]

Bit 8 - Enable internal wakeup

impl W<u32, Reg<u32, _CR2>>[src]

pub fn wupp1(&mut self) -> WUPP1_W<'_>[src]

Bit 8 - Wakeup pin polarity bit for PA0

pub fn wupp2(&mut self) -> WUPP2_W<'_>[src]

Bit 9 - Wakeup pin polarity bit for PA2

pub fn wupp3(&mut self) -> WUPP3_W<'_>[src]

Bit 10 - Wakeup pin polarity bit for PC1

pub fn wupp4(&mut self) -> WUPP4_W<'_>[src]

Bit 11 - Wakeup pin polarity bit for PC13

pub fn wupp5(&mut self) -> WUPP5_W<'_>[src]

Bit 12 - Wakeup pin polarity bit for PI8

pub fn wupp6(&mut self) -> WUPP6_W<'_>[src]

Bit 13 - Wakeup pin polarity bit for PI11

impl W<u32, Reg<u32, _CSR2>>[src]

pub fn ewup1(&mut self) -> EWUP1_W<'_>[src]

Bit 8 - Enable Wakeup pin for PA0

pub fn ewup2(&mut self) -> EWUP2_W<'_>[src]

Bit 9 - Enable Wakeup pin for PA2

pub fn ewup3(&mut self) -> EWUP3_W<'_>[src]

Bit 10 - Enable Wakeup pin for PC1

pub fn ewup4(&mut self) -> EWUP4_W<'_>[src]

Bit 11 - Enable Wakeup pin for PC13

pub fn ewup5(&mut self) -> EWUP5_W<'_>[src]

Bit 12 - Enable Wakeup pin for PI8

pub fn ewup6(&mut self) -> EWUP6_W<'_>[src]

Bit 13 - Enable Wakeup pin for PI11

impl W<u32, Reg<u32, _CR>>[src]

pub fn prescaler(&mut self) -> PRESCALER_W<'_>[src]

Bits 24:31 - Clock prescaler

pub fn pmm(&mut self) -> PMM_W<'_>[src]

Bit 23 - Polling match mode

pub fn apms(&mut self) -> APMS_W<'_>[src]

Bit 22 - Automatic poll mode stop

pub fn toie(&mut self) -> TOIE_W<'_>[src]

Bit 20 - TimeOut interrupt enable

pub fn smie(&mut self) -> SMIE_W<'_>[src]

Bit 19 - Status match interrupt enable

pub fn ftie(&mut self) -> FTIE_W<'_>[src]

Bit 18 - FIFO threshold interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>[src]

Bit 17 - Transfer complete interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>[src]

Bit 16 - Transfer error interrupt enable

pub fn fthres(&mut self) -> FTHRES_W<'_>[src]

Bits 8:12 - IFO threshold level

pub fn fsel(&mut self) -> FSEL_W<'_>[src]

Bit 7 - FLASH memory selection

pub fn dfm(&mut self) -> DFM_W<'_>[src]

Bit 6 - Dual-flash mode

pub fn sshift(&mut self) -> SSHIFT_W<'_>[src]

Bit 4 - Sample shift

pub fn tcen(&mut self) -> TCEN_W<'_>[src]

Bit 3 - Timeout counter enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]

Bit 2 - DMA enable

pub fn abort(&mut self) -> ABORT_W<'_>[src]

Bit 1 - Abort request

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - Enable

impl W<u32, Reg<u32, _DCR>>[src]

pub fn fsize(&mut self) -> FSIZE_W<'_>[src]

Bits 16:20 - FLASH memory size

pub fn csht(&mut self) -> CSHT_W<'_>[src]

Bits 8:10 - Chip select high time

pub fn ckmode(&mut self) -> CKMODE_W<'_>[src]

Bit 0 - Mode 0 / mode 3

impl W<u32, Reg<u32, _FCR>>[src]

pub fn ctof(&mut self) -> CTOF_W<'_>[src]

Bit 4 - Clear timeout flag

pub fn csmf(&mut self) -> CSMF_W<'_>[src]

Bit 3 - Clear status match flag

pub fn ctcf(&mut self) -> CTCF_W<'_>[src]

Bit 1 - Clear transfer complete flag

pub fn ctef(&mut self) -> CTEF_W<'_>[src]

Bit 0 - Clear transfer error flag

impl W<u32, Reg<u32, _DLR>>[src]

pub fn dl(&mut self) -> DL_W<'_>[src]

Bits 0:31 - Data length

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ddrm(&mut self) -> DDRM_W<'_>[src]

Bit 31 - Double data rate mode

pub fn dhhc(&mut self) -> DHHC_W<'_>[src]

Bit 30 - DDR hold half cycle

pub fn sioo(&mut self) -> SIOO_W<'_>[src]

Bit 28 - Send instruction only once mode

pub fn fmode(&mut self) -> FMODE_W<'_>[src]

Bits 26:27 - Functional mode

pub fn dmode(&mut self) -> DMODE_W<'_>[src]

Bits 24:25 - Data mode

pub fn dcyc(&mut self) -> DCYC_W<'_>[src]

Bits 18:22 - Number of dummy cycles

pub fn absize(&mut self) -> ABSIZE_W<'_>[src]

Bits 16:17 - Alternate bytes size

pub fn abmode(&mut self) -> ABMODE_W<'_>[src]

Bits 14:15 - Alternate bytes mode

pub fn adsize(&mut self) -> ADSIZE_W<'_>[src]

Bits 12:13 - Address size

pub fn admode(&mut self) -> ADMODE_W<'_>[src]

Bits 10:11 - Address mode

pub fn imode(&mut self) -> IMODE_W<'_>[src]

Bits 8:9 - Instruction mode

pub fn instruction(&mut self) -> INSTRUCTION_W<'_>[src]

Bits 0:7 - Instruction

impl W<u32, Reg<u32, _AR>>[src]

pub fn address(&mut self) -> ADDRESS_W<'_>[src]

Bits 0:31 - Address

impl W<u32, Reg<u32, _ABR>>[src]

pub fn alternate(&mut self) -> ALTERNATE_W<'_>[src]

Bits 0:31 - ALTERNATE

impl W<u32, Reg<u32, _DR>>[src]

pub fn data(&mut self) -> DATA_W<'_>[src]

Bits 0:31 - Data

impl W<u32, Reg<u32, _PSMKR>>[src]

pub fn mask(&mut self) -> MASK_W<'_>[src]

Bits 0:31 - Status mask

impl W<u32, Reg<u32, _PSMAR>>[src]

pub fn match_(&mut self) -> MATCH_W<'_>[src]

Bits 0:31 - Status match

impl W<u32, Reg<u32, _PIR>>[src]

pub fn interval(&mut self) -> INTERVAL_W<'_>[src]

Bits 0:15 - Polling interval

impl W<u32, Reg<u32, _LPTR>>[src]

pub fn timeout(&mut self) -> TIMEOUT_W<'_>[src]

Bits 0:15 - Timeout period

impl W<u32, Reg<u32, _CR>>[src]

pub fn ie(&mut self) -> IE_W<'_>[src]

Bit 3 - Interrupt enable

pub fn rngen(&mut self) -> RNGEN_W<'_>[src]

Bit 2 - Random number generator enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn seis(&mut self) -> SEIS_W<'_>[src]

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>[src]

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _TR>>[src]

pub fn pm(&mut self) -> PM_W<'_>[src]

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>[src]

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>[src]

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>[src]

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>[src]

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>[src]

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>[src]

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>[src]

pub fn yt(&mut self) -> YT_W<'_>[src]

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>[src]

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>[src]

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>[src]

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>[src]

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>[src]

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>[src]

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>[src]

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>[src]

Bits 0:2 - Wakeup clock selection

pub fn tsedge(&mut self) -> TSEDGE_W<'_>[src]

Bit 3 - Time-stamp event active edge

pub fn refckon(&mut self) -> REFCKON_W<'_>[src]

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>[src]

Bit 5 - Bypass the shadow registers

pub fn fmt(&mut self) -> FMT_W<'_>[src]

Bit 6 - Hour format

pub fn alrae(&mut self) -> ALRAE_W<'_>[src]

Bit 8 - Alarm A enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>[src]

Bit 9 - Alarm B enable

pub fn wute(&mut self) -> WUTE_W<'_>[src]

Bit 10 - Wakeup timer enable

pub fn tse(&mut self) -> TSE_W<'_>[src]

Bit 11 - Time stamp enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>[src]

Bit 12 - Alarm A interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>[src]

Bit 13 - Alarm B interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>[src]

Bit 14 - Wakeup timer interrupt enable

pub fn tsie(&mut self) -> TSIE_W<'_>[src]

Bit 15 - Time-stamp interrupt enable

pub fn add1h(&mut self) -> ADD1H_W<'_>[src]

Bit 16 - Add 1 hour (summer time change)

pub fn sub1h(&mut self) -> SUB1H_W<'_>[src]

Bit 17 - Subtract 1 hour (winter time change)

pub fn bkp(&mut self) -> BKP_W<'_>[src]

Bit 18 - Backup

pub fn cosel(&mut self) -> COSEL_W<'_>[src]

Bit 19 - Calibration output selection

pub fn pol(&mut self) -> POL_W<'_>[src]

Bit 20 - Output polarity

pub fn osel(&mut self) -> OSEL_W<'_>[src]

Bits 21:22 - Output selection

pub fn coe(&mut self) -> COE_W<'_>[src]

Bit 23 - Calibration output enable

pub fn itse(&mut self) -> ITSE_W<'_>[src]

Bit 24 - timestamp on internal event enable

impl W<u32, Reg<u32, _ISR>>[src]

pub fn shpf(&mut self) -> SHPF_W<'_>[src]

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>[src]

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>[src]

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>[src]

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>[src]

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>[src]

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>[src]

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>[src]

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>[src]

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>[src]

Bit 14 - RTC_TAMP2 detection flag

pub fn tamp3f(&mut self) -> TAMP3F_W<'_>[src]

Bit 15 - RTC_TAMP3 detection flag

impl W<u32, Reg<u32, _PRER>>[src]

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>[src]

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>[src]

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>[src]

pub fn wut(&mut self) -> WUT_W<'_>[src]

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _ALRMAR>>[src]

pub fn msk4(&mut self) -> MSK4_W<'_>[src]

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>[src]

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>[src]

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>[src]

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>[src]

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>[src]

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>[src]

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>[src]

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>[src]

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>[src]

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>[src]

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>[src]

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>[src]

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>[src]

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>[src]

pub fn msk4(&mut self) -> MSK4_W<'_>[src]

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>[src]

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>[src]

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>[src]

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>[src]

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>[src]

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>[src]

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>[src]

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>[src]

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>[src]

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>[src]

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>[src]

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>[src]

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>[src]

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>[src]

pub fn key(&mut self) -> KEY_W<'_>[src]

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>[src]

pub fn add1s(&mut self) -> ADD1S_W<'_>[src]

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>[src]

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>[src]

pub fn calp(&mut self) -> CALP_W<'_>[src]

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>[src]

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>[src]

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>[src]

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAMPCR>>[src]

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>[src]

Bit 0 - Tamper 1 detection enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>[src]

Bit 1 - Active level for tamper 1

pub fn tampie(&mut self) -> TAMPIE_W<'_>[src]

Bit 2 - Tamper interrupt enable

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>[src]

Bit 3 - Tamper 2 detection enable

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>[src]

Bit 4 - Active level for tamper 2

pub fn tamp3e(&mut self) -> TAMP3E_W<'_>[src]

Bit 5 - Tamper 3 detection enable

pub fn tamp3trg(&mut self) -> TAMP3TRG_W<'_>[src]

Bit 6 - Active level for tamper 3

pub fn tampts(&mut self) -> TAMPTS_W<'_>[src]

Bit 7 - Activate timestamp on tamper detection event

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>[src]

Bits 8:10 - Tamper sampling frequency

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>[src]

Bits 11:12 - Tamper filter count

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>[src]

Bits 13:14 - Tamper precharge duration

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>[src]

Bit 15 - TAMPER pull-up disable

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>[src]

Bit 16 - Tamper 1 interrupt enable

pub fn tamp1noerase(&mut self) -> TAMP1NOERASE_W<'_>[src]

Bit 17 - Tamper 1 no erase

pub fn tamp1mf(&mut self) -> TAMP1MF_W<'_>[src]

Bit 18 - Tamper 1 mask flag

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>[src]

Bit 19 - Tamper 2 interrupt enable

pub fn tamp2noerase(&mut self) -> TAMP2NOERASE_W<'_>[src]

Bit 20 - Tamper 2 no erase

pub fn tamp2mf(&mut self) -> TAMP2MF_W<'_>[src]

Bit 21 - Tamper 2 mask flag

pub fn tamp3ie(&mut self) -> TAMP3IE_W<'_>[src]

Bit 22 - Tamper 3 interrupt enable

pub fn tamp3noerase(&mut self) -> TAMP3NOERASE_W<'_>[src]

Bit 23 - Tamper 3 no erase

pub fn tamp3mf(&mut self) -> TAMP3MF_W<'_>[src]

Bit 24 - Tamper 3 mask flag

impl W<u32, Reg<u32, _ALRMASSR>>[src]

pub fn maskss(&mut self) -> MASKSS_W<'_>[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>[src]

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>[src]

pub fn maskss(&mut self) -> MASKSS_W<'_>[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>[src]

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _OR>>[src]

pub fn rtc_alarm_type(&mut self) -> RTC_ALARM_TYPE_W<'_>[src]

Bit 3 - RTC_ALARM on PC13 output type

pub fn tsinsel(&mut self) -> TSINSEL_W<'_>[src]

Bit 1 - TIMESTAMP mapping

impl W<u32, Reg<u32, _BKPR>>[src]

pub fn bkp(&mut self) -> BKP_W<'_>[src]

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR>>[src]

pub fn plli2son(&mut self) -> PLLI2SON_W<'_>[src]

Bit 26 - PLLI2S enable

pub fn pllon(&mut self) -> PLLON_W<'_>[src]

Bit 24 - Main PLL (PLL) enable

pub fn csson(&mut self) -> CSSON_W<'_>[src]

Bit 19 - Clock security system enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>[src]

Bit 18 - HSE clock bypass

pub fn hseon(&mut self) -> HSEON_W<'_>[src]

Bit 16 - HSE clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>[src]

Bits 3:7 - Internal high-speed clock trimming

pub fn hsion(&mut self) -> HSION_W<'_>[src]

Bit 0 - Internal high-speed clock enable

pub fn pllsaion(&mut self) -> PLLSAION_W<'_>[src]

Bit 28 - PLLSAI enable

impl W<u32, Reg<u32, _PLLCFGR>>[src]

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>[src]

Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source

pub fn pllm(&mut self) -> PLLM_W<'_>[src]

Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock

pub fn plln(&mut self) -> PLLN_W<'_>[src]

Bits 6:14 - Main PLL (PLL) multiplication factor for VCO

pub fn pllp(&mut self) -> PLLP_W<'_>[src]

Bits 16:17 - Main PLL (PLL) division factor for main system clock

pub fn pllq(&mut self) -> PLLQ_W<'_>[src]

Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks

impl W<u32, Reg<u32, _CFGR>>[src]

pub fn mco2(&mut self) -> MCO2_W<'_>[src]

Bits 30:31 - Microcontroller clock output 2

pub fn mco2pre(&mut self) -> MCO2PRE_W<'_>[src]

Bits 27:29 - MCO2 prescaler

pub fn mco1pre(&mut self) -> MCO1PRE_W<'_>[src]

Bits 24:26 - MCO1 prescaler

pub fn i2ssrc(&mut self) -> I2SSRC_W<'_>[src]

Bit 23 - I2S clock selection

pub fn mco1(&mut self) -> MCO1_W<'_>[src]

Bits 21:22 - Microcontroller clock output 1

pub fn rtcpre(&mut self) -> RTCPRE_W<'_>[src]

Bits 16:20 - HSE division factor for RTC clock

pub fn ppre2(&mut self) -> PPRE2_W<'_>[src]

Bits 13:15 - APB high-speed prescaler (APB2)

pub fn ppre1(&mut self) -> PPRE1_W<'_>[src]

Bits 10:12 - APB Low speed prescaler (APB1)

pub fn hpre(&mut self) -> HPRE_W<'_>[src]

Bits 4:7 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>[src]

Bits 0:1 - System clock switch

pub fn sws(&mut self) -> SWS_W<'_>[src]

Bits 2:3 - System clock switch status

impl W<u32, Reg<u32, _CIR>>[src]

pub fn cssc(&mut self) -> CSSC_W<'_>[src]

Bit 23 - Clock security system interrupt clear

pub fn pllsairdyc(&mut self) -> PLLSAIRDYC_W<'_>[src]

Bit 22 - PLLSAI Ready Interrupt Clear

pub fn plli2srdyc(&mut self) -> PLLI2SRDYC_W<'_>[src]

Bit 21 - PLLI2S ready interrupt clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>[src]

Bit 20 - Main PLL(PLL) ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>[src]

Bit 19 - HSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>[src]

Bit 18 - HSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>[src]

Bit 17 - LSE ready interrupt clear

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>[src]

Bit 16 - LSI ready interrupt clear

pub fn pllsairdyie(&mut self) -> PLLSAIRDYIE_W<'_>[src]

Bit 14 - PLLSAI Ready Interrupt Enable

pub fn plli2srdyie(&mut self) -> PLLI2SRDYIE_W<'_>[src]

Bit 13 - PLLI2S ready interrupt enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>[src]

Bit 12 - Main PLL (PLL) ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>[src]

Bit 11 - HSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>[src]

Bit 10 - HSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>[src]

Bit 9 - LSE ready interrupt enable

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>[src]

Bit 8 - LSI ready interrupt enable

impl W<u32, Reg<u32, _AHB1RSTR>>[src]

pub fn otghsrst(&mut self) -> OTGHSRST_W<'_>[src]

Bit 29 - USB OTG HS module reset

pub fn dma2rst(&mut self) -> DMA2RST_W<'_>[src]

Bit 22 - DMA2 reset

pub fn dma1rst(&mut self) -> DMA1RST_W<'_>[src]

Bit 21 - DMA2 reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>[src]

Bit 12 - CRC reset

pub fn gpioirst(&mut self) -> GPIOIRST_W<'_>[src]

Bit 8 - IO port I reset

pub fn gpiohrst(&mut self) -> GPIOHRST_W<'_>[src]

Bit 7 - IO port H reset

pub fn gpiogrst(&mut self) -> GPIOGRST_W<'_>[src]

Bit 6 - IO port G reset

pub fn gpiofrst(&mut self) -> GPIOFRST_W<'_>[src]

Bit 5 - IO port F reset

pub fn gpioerst(&mut self) -> GPIOERST_W<'_>[src]

Bit 4 - IO port E reset

pub fn gpiodrst(&mut self) -> GPIODRST_W<'_>[src]

Bit 3 - IO port D reset

pub fn gpiocrst(&mut self) -> GPIOCRST_W<'_>[src]

Bit 2 - IO port C reset

pub fn gpiobrst(&mut self) -> GPIOBRST_W<'_>[src]

Bit 1 - IO port B reset

pub fn gpioarst(&mut self) -> GPIOARST_W<'_>[src]

Bit 0 - IO port A reset

impl W<u32, Reg<u32, _AHB2RSTR>>[src]

pub fn otgfsrst(&mut self) -> OTGFSRST_W<'_>[src]

Bit 7 - USB OTG FS module reset

pub fn rngrst(&mut self) -> RNGRST_W<'_>[src]

Bit 6 - Random number generator module reset

pub fn aesrst(&mut self) -> AESRST_W<'_>[src]

Bit 4 - AES module reset

impl W<u32, Reg<u32, _AHB3RSTR>>[src]

pub fn fmcrst(&mut self) -> FMCRST_W<'_>[src]

Bit 0 - Flexible memory controller module reset

pub fn qspirst(&mut self) -> QSPIRST_W<'_>[src]

Bit 1 - Quad SPI memory controller reset

impl W<u32, Reg<u32, _APB1RSTR>>[src]

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>[src]

Bit 0 - TIM2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>[src]

Bit 1 - TIM3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>[src]

Bit 2 - TIM4 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>[src]

Bit 3 - TIM5 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>[src]

Bit 4 - TIM6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>[src]

Bit 5 - TIM7 reset

pub fn tim12rst(&mut self) -> TIM12RST_W<'_>[src]

Bit 6 - TIM12 reset

pub fn tim13rst(&mut self) -> TIM13RST_W<'_>[src]

Bit 7 - TIM13 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>[src]

Bit 8 - TIM14 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>[src]

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>[src]

Bit 14 - SPI 2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>[src]

Bit 15 - SPI 3 reset

pub fn uart2rst(&mut self) -> UART2RST_W<'_>[src]

Bit 17 - USART 2 reset

pub fn uart3rst(&mut self) -> UART3RST_W<'_>[src]

Bit 18 - USART 3 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>[src]

Bit 19 - USART 4 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>[src]

Bit 20 - USART 5 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>[src]

Bit 21 - I2C 1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>[src]

Bit 22 - I2C 2 reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>[src]

Bit 23 - I2C3 reset

pub fn can1rst(&mut self) -> CAN1RST_W<'_>[src]

Bit 25 - CAN1 reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>[src]

Bit 28 - Power interface reset

pub fn dacrst(&mut self) -> DACRST_W<'_>[src]

Bit 29 - DAC reset

pub fn uart7rst(&mut self) -> UART7RST_W<'_>[src]

Bit 30 - UART7 reset

pub fn uart8rst(&mut self) -> UART8RST_W<'_>[src]

Bit 31 - UART8 reset

pub fn cecrst(&mut self) -> CECRST_W<'_>[src]

Bit 27 - HDMI-CEC reset

pub fn lptim1rst(&mut self) -> LPTIM1RST_W<'_>[src]

Bit 9 - Low power timer 1 reset

impl W<u32, Reg<u32, _APB2RSTR>>[src]

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>[src]

Bit 0 - TIM1 reset

pub fn tim8rst(&mut self) -> TIM8RST_W<'_>[src]

Bit 1 - TIM8 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>[src]

Bit 4 - USART1 reset

pub fn usart6rst(&mut self) -> USART6RST_W<'_>[src]

Bit 5 - USART6 reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>[src]

Bit 8 - ADC interface reset (common to all ADCs)

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>[src]

Bit 12 - SPI 1 reset

pub fn spi4rst(&mut self) -> SPI4RST_W<'_>[src]

Bit 13 - SPI4 reset

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>[src]

Bit 14 - System configuration controller reset

pub fn tim9rst(&mut self) -> TIM9RST_W<'_>[src]

Bit 16 - TIM9 reset

pub fn tim10rst(&mut self) -> TIM10RST_W<'_>[src]

Bit 17 - TIM10 reset

pub fn tim11rst(&mut self) -> TIM11RST_W<'_>[src]

Bit 18 - TIM11 reset

pub fn spi5rst(&mut self) -> SPI5RST_W<'_>[src]

Bit 20 - SPI5 reset

pub fn sai1rst(&mut self) -> SAI1RST_W<'_>[src]

Bit 22 - SAI1 reset

pub fn sai2rst(&mut self) -> SAI2RST_W<'_>[src]

Bit 23 - SAI2 reset

pub fn sdmmc1rst(&mut self) -> SDMMC1RST_W<'_>[src]

Bit 11 - SDMMC1 reset

pub fn sdmmc2rst(&mut self) -> SDMMC2RST_W<'_>[src]

Bit 7 - SDMMC2 reset

pub fn usbphycrst(&mut self) -> USBPHYCRST_W<'_>[src]

Bit 31 - USB OTG HS PHY controller reset

impl W<u32, Reg<u32, _AHB1ENR>>[src]

pub fn otghsulpien(&mut self) -> OTGHSULPIEN_W<'_>[src]

Bit 30 - USB OTG HSULPI clock enable

pub fn otghsen(&mut self) -> OTGHSEN_W<'_>[src]

Bit 29 - USB OTG HS clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>[src]

Bit 22 - DMA2 clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>[src]

Bit 21 - DMA1 clock enable

pub fn dtcmramen(&mut self) -> DTCMRAMEN_W<'_>[src]

Bit 20 - CCM data RAM clock enable

pub fn bkpsramen(&mut self) -> BKPSRAMEN_W<'_>[src]

Bit 18 - Backup SRAM interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>[src]

Bit 12 - CRC clock enable

pub fn gpioien(&mut self) -> GPIOIEN_W<'_>[src]

Bit 8 - IO port I clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>[src]

Bit 7 - IO port H clock enable

pub fn gpiogen(&mut self) -> GPIOGEN_W<'_>[src]

Bit 6 - IO port G clock enable

pub fn gpiofen(&mut self) -> GPIOFEN_W<'_>[src]

Bit 5 - IO port F clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>[src]

Bit 4 - IO port E clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>[src]

Bit 3 - IO port D clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>[src]

Bit 2 - IO port C clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>[src]

Bit 1 - IO port B clock enable

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>[src]

Bit 0 - IO port A clock enable

impl W<u32, Reg<u32, _AHB2ENR>>[src]

pub fn otgfsen(&mut self) -> OTGFSEN_W<'_>[src]

Bit 7 - USB OTG FS clock enable

pub fn rngen(&mut self) -> RNGEN_W<'_>[src]

Bit 6 - Random number generator clock enable

pub fn aesen(&mut self) -> AESEN_W<'_>[src]

Bit 4 - AES module clock enable

impl W<u32, Reg<u32, _AHB3ENR>>[src]

pub fn fmcen(&mut self) -> FMCEN_W<'_>[src]

Bit 0 - Flexible memory controller module clock enable

pub fn qspien(&mut self) -> QSPIEN_W<'_>[src]

Bit 1 - Quad SPI memory controller clock enable

impl W<u32, Reg<u32, _APB1ENR>>[src]

pub fn tim2en(&mut self) -> TIM2EN_W<'_>[src]

Bit 0 - TIM2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>[src]

Bit 1 - TIM3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>[src]

Bit 2 - TIM4 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>[src]

Bit 3 - TIM5 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>[src]

Bit 4 - TIM6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>[src]

Bit 5 - TIM7 clock enable

pub fn tim12en(&mut self) -> TIM12EN_W<'_>[src]

Bit 6 - TIM12 clock enable

pub fn tim13en(&mut self) -> TIM13EN_W<'_>[src]

Bit 7 - TIM13 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>[src]

Bit 8 - TIM14 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>[src]

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>[src]

Bit 14 - SPI2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>[src]

Bit 15 - SPI3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>[src]

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>[src]

Bit 18 - USART3 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>[src]

Bit 19 - UART4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>[src]

Bit 20 - UART5 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>[src]

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>[src]

Bit 22 - I2C2 clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>[src]

Bit 23 - I2C3 clock enable

pub fn can1en(&mut self) -> CAN1EN_W<'_>[src]

Bit 25 - CAN 1 clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>[src]

Bit 28 - Power interface clock enable

pub fn dacen(&mut self) -> DACEN_W<'_>[src]

Bit 29 - DAC interface clock enable

pub fn uart7en(&mut self) -> UART7EN_W<'_>[src]

Bit 30 - UART7 clock enable

pub fn uart8en(&mut self) -> UART8EN_W<'_>[src]

Bit 31 - UART8 clock enable

pub fn lptim1en(&mut self) -> LPTIM1EN_W<'_>[src]

Bit 9 - Low power timer 1 clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>[src]

Bit 10 - RTCAPB clock enable

impl W<u32, Reg<u32, _APB2ENR>>[src]

pub fn tim1en(&mut self) -> TIM1EN_W<'_>[src]

Bit 0 - TIM1 clock enable

pub fn tim8en(&mut self) -> TIM8EN_W<'_>[src]

Bit 1 - TIM8 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>[src]

Bit 4 - USART1 clock enable

pub fn usart6en(&mut self) -> USART6EN_W<'_>[src]

Bit 5 - USART6 clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>[src]

Bit 8 - ADC1 clock enable

pub fn adc2en(&mut self) -> ADC2EN_W<'_>[src]

Bit 9 - ADC2 clock enable

pub fn adc3en(&mut self) -> ADC3EN_W<'_>[src]

Bit 10 - ADC3 clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>[src]

Bit 12 - SPI1 clock enable

pub fn spi4en(&mut self) -> SPI4EN_W<'_>[src]

Bit 13 - SPI4 clock enable

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>[src]

Bit 14 - System configuration controller clock enable

pub fn tim9en(&mut self) -> TIM9EN_W<'_>[src]

Bit 16 - TIM9 clock enable

pub fn tim10en(&mut self) -> TIM10EN_W<'_>[src]

Bit 17 - TIM10 clock enable

pub fn tim11en(&mut self) -> TIM11EN_W<'_>[src]

Bit 18 - TIM11 clock enable

pub fn spi5en(&mut self) -> SPI5EN_W<'_>[src]

Bit 20 - SPI5 clock enable

pub fn sai1en(&mut self) -> SAI1EN_W<'_>[src]

Bit 22 - SAI1 clock enable

pub fn sai2en(&mut self) -> SAI2EN_W<'_>[src]

Bit 23 - SAI2 clock enable

pub fn sdmmc1en(&mut self) -> SDMMC1EN_W<'_>[src]

Bit 11 - SDMMC1 clock enable

pub fn sdmmc2en(&mut self) -> SDMMC2EN_W<'_>[src]

Bit 7 - SDMMC2 clock enable

pub fn usbphycen(&mut self) -> USBPHYCEN_W<'_>[src]

Bit 31 - USB OTG HS PHY controller clock enable

impl W<u32, Reg<u32, _AHB1LPENR>>[src]

pub fn gpioalpen(&mut self) -> GPIOALPEN_W<'_>[src]

Bit 0 - IO port A clock enable during sleep mode

pub fn gpioblpen(&mut self) -> GPIOBLPEN_W<'_>[src]

Bit 1 - IO port B clock enable during Sleep mode

pub fn gpioclpen(&mut self) -> GPIOCLPEN_W<'_>[src]

Bit 2 - IO port C clock enable during Sleep mode

pub fn gpiodlpen(&mut self) -> GPIODLPEN_W<'_>[src]

Bit 3 - IO port D clock enable during Sleep mode

pub fn gpioelpen(&mut self) -> GPIOELPEN_W<'_>[src]

Bit 4 - IO port E clock enable during Sleep mode

pub fn gpioflpen(&mut self) -> GPIOFLPEN_W<'_>[src]

Bit 5 - IO port F clock enable during Sleep mode

pub fn gpioglpen(&mut self) -> GPIOGLPEN_W<'_>[src]

Bit 6 - IO port G clock enable during Sleep mode

pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W<'_>[src]

Bit 7 - IO port H clock enable during Sleep mode

pub fn gpioilpen(&mut self) -> GPIOILPEN_W<'_>[src]

Bit 8 - IO port I clock enable during Sleep mode

pub fn gpiojlpen(&mut self) -> GPIOJLPEN_W<'_>[src]

Bit 9 - IO port J clock enable during Sleep mode

pub fn gpioklpen(&mut self) -> GPIOKLPEN_W<'_>[src]

Bit 10 - IO port K clock enable during Sleep mode

pub fn crclpen(&mut self) -> CRCLPEN_W<'_>[src]

Bit 12 - CRC clock enable during Sleep mode

pub fn flitflpen(&mut self) -> FLITFLPEN_W<'_>[src]

Bit 15 - Flash interface clock enable during Sleep mode

pub fn sram1lpen(&mut self) -> SRAM1LPEN_W<'_>[src]

Bit 16 - SRAM 1interface clock enable during Sleep mode

pub fn sram2lpen(&mut self) -> SRAM2LPEN_W<'_>[src]

Bit 17 - SRAM 2 interface clock enable during Sleep mode

pub fn bkpsramlpen(&mut self) -> BKPSRAMLPEN_W<'_>[src]

Bit 18 - Backup SRAM interface clock enable during Sleep mode

pub fn sram3lpen(&mut self) -> SRAM3LPEN_W<'_>[src]

Bit 19 - SRAM 3 interface clock enable during Sleep mode

pub fn dma1lpen(&mut self) -> DMA1LPEN_W<'_>[src]

Bit 21 - DMA1 clock enable during Sleep mode

pub fn dma2lpen(&mut self) -> DMA2LPEN_W<'_>[src]

Bit 22 - DMA2 clock enable during Sleep mode

pub fn dma2dlpen(&mut self) -> DMA2DLPEN_W<'_>[src]

Bit 23 - DMA2D clock enable during Sleep mode

pub fn ethmaclpen(&mut self) -> ETHMACLPEN_W<'_>[src]

Bit 25 - Ethernet MAC clock enable during Sleep mode

pub fn ethmactxlpen(&mut self) -> ETHMACTXLPEN_W<'_>[src]

Bit 26 - Ethernet transmission clock enable during Sleep mode

pub fn ethmacrxlpen(&mut self) -> ETHMACRXLPEN_W<'_>[src]

Bit 27 - Ethernet reception clock enable during Sleep mode

pub fn ethmacptplpen(&mut self) -> ETHMACPTPLPEN_W<'_>[src]

Bit 28 - Ethernet PTP clock enable during Sleep mode

pub fn otghslpen(&mut self) -> OTGHSLPEN_W<'_>[src]

Bit 29 - USB OTG HS clock enable during Sleep mode

pub fn otghsulpilpen(&mut self) -> OTGHSULPILPEN_W<'_>[src]

Bit 30 - USB OTG HS ULPI clock enable during Sleep mode

pub fn axilpen(&mut self) -> AXILPEN_W<'_>[src]

Bit 13 - AXI to AHB bridge clock enable during Sleep mode

pub fn dtcmlpen(&mut self) -> DTCMLPEN_W<'_>[src]

Bit 20 - DTCM RAM interface clock enable during Sleep mode

impl W<u32, Reg<u32, _AHB2LPENR>>[src]

pub fn otgfslpen(&mut self) -> OTGFSLPEN_W<'_>[src]

Bit 7 - USB OTG FS clock enable during Sleep mode

pub fn rnglpen(&mut self) -> RNGLPEN_W<'_>[src]

Bit 6 - Random number generator clock enable during Sleep mode

pub fn aeslpen(&mut self) -> AESLPEN_W<'_>[src]

Bit 4 - AES module clock enable during Sleep mode

impl W<u32, Reg<u32, _AHB3LPENR>>[src]

pub fn fmclpen(&mut self) -> FMCLPEN_W<'_>[src]

Bit 0 - Flexible memory controller module clock enable during Sleep mode

pub fn qspilpen(&mut self) -> QSPILPEN_W<'_>[src]

Bit 1 - Quand SPI memory controller clock enable during Sleep mode

impl W<u32, Reg<u32, _APB1LPENR>>[src]

pub fn tim2lpen(&mut self) -> TIM2LPEN_W<'_>[src]

Bit 0 - TIM2 clock enable during Sleep mode

pub fn tim3lpen(&mut self) -> TIM3LPEN_W<'_>[src]

Bit 1 - TIM3 clock enable during Sleep mode

pub fn tim4lpen(&mut self) -> TIM4LPEN_W<'_>[src]

Bit 2 - TIM4 clock enable during Sleep mode

pub fn tim5lpen(&mut self) -> TIM5LPEN_W<'_>[src]

Bit 3 - TIM5 clock enable during Sleep mode

pub fn tim6lpen(&mut self) -> TIM6LPEN_W<'_>[src]

Bit 4 - TIM6 clock enable during Sleep mode

pub fn tim7lpen(&mut self) -> TIM7LPEN_W<'_>[src]

Bit 5 - TIM7 clock enable during Sleep mode

pub fn tim12lpen(&mut self) -> TIM12LPEN_W<'_>[src]

Bit 6 - TIM12 clock enable during Sleep mode

pub fn tim13lpen(&mut self) -> TIM13LPEN_W<'_>[src]

Bit 7 - TIM13 clock enable during Sleep mode

pub fn tim14lpen(&mut self) -> TIM14LPEN_W<'_>[src]

Bit 8 - TIM14 clock enable during Sleep mode

pub fn wwdglpen(&mut self) -> WWDGLPEN_W<'_>[src]

Bit 11 - Window watchdog clock enable during Sleep mode

pub fn spi2lpen(&mut self) -> SPI2LPEN_W<'_>[src]

Bit 14 - SPI2 clock enable during Sleep mode

pub fn spi3lpen(&mut self) -> SPI3LPEN_W<'_>[src]

Bit 15 - SPI3 clock enable during Sleep mode

pub fn usart2lpen(&mut self) -> USART2LPEN_W<'_>[src]

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3lpen(&mut self) -> USART3LPEN_W<'_>[src]

Bit 18 - USART3 clock enable during Sleep mode

pub fn uart4lpen(&mut self) -> UART4LPEN_W<'_>[src]

Bit 19 - UART4 clock enable during Sleep mode

pub fn uart5lpen(&mut self) -> UART5LPEN_W<'_>[src]

Bit 20 - UART5 clock enable during Sleep mode

pub fn i2c1lpen(&mut self) -> I2C1LPEN_W<'_>[src]

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2lpen(&mut self) -> I2C2LPEN_W<'_>[src]

Bit 22 - I2C2 clock enable during Sleep mode

pub fn i2c3lpen(&mut self) -> I2C3LPEN_W<'_>[src]

Bit 23 - I2C3 clock enable during Sleep mode

pub fn can1lpen(&mut self) -> CAN1LPEN_W<'_>[src]

Bit 25 - CAN 1 clock enable during Sleep mode

pub fn can2lpen(&mut self) -> CAN2LPEN_W<'_>[src]

Bit 26 - CAN 2 clock enable during Sleep mode

pub fn pwrlpen(&mut self) -> PWRLPEN_W<'_>[src]

Bit 28 - Power interface clock enable during Sleep mode

pub fn daclpen(&mut self) -> DACLPEN_W<'_>[src]

Bit 29 - DAC interface clock enable during Sleep mode

pub fn uart7lpen(&mut self) -> UART7LPEN_W<'_>[src]

Bit 30 - UART7 clock enable during Sleep mode

pub fn uart8lpen(&mut self) -> UART8LPEN_W<'_>[src]

Bit 31 - UART8 clock enable during Sleep mode

pub fn lptim1lpen(&mut self) -> LPTIM1LPEN_W<'_>[src]

Bit 9 - low power timer 1 clock enable during Sleep mode

impl W<u32, Reg<u32, _APB2LPENR>>[src]

pub fn tim1lpen(&mut self) -> TIM1LPEN_W<'_>[src]

Bit 0 - TIM1 clock enable during Sleep mode

pub fn tim8lpen(&mut self) -> TIM8LPEN_W<'_>[src]

Bit 1 - TIM8 clock enable during Sleep mode

pub fn usart1lpen(&mut self) -> USART1LPEN_W<'_>[src]

Bit 4 - USART1 clock enable during Sleep mode

pub fn usart6lpen(&mut self) -> USART6LPEN_W<'_>[src]

Bit 5 - USART6 clock enable during Sleep mode

pub fn adc1lpen(&mut self) -> ADC1LPEN_W<'_>[src]

Bit 8 - ADC1 clock enable during Sleep mode

pub fn adc2lpen(&mut self) -> ADC2LPEN_W<'_>[src]

Bit 9 - ADC2 clock enable during Sleep mode

pub fn adc3lpen(&mut self) -> ADC3LPEN_W<'_>[src]

Bit 10 - ADC 3 clock enable during Sleep mode

pub fn spi1lpen(&mut self) -> SPI1LPEN_W<'_>[src]

Bit 12 - SPI 1 clock enable during Sleep mode

pub fn spi4lpen(&mut self) -> SPI4LPEN_W<'_>[src]

Bit 13 - SPI 4 clock enable during Sleep mode

pub fn syscfglpen(&mut self) -> SYSCFGLPEN_W<'_>[src]

Bit 14 - System configuration controller clock enable during Sleep mode

pub fn tim9lpen(&mut self) -> TIM9LPEN_W<'_>[src]

Bit 16 - TIM9 clock enable during sleep mode

pub fn tim10lpen(&mut self) -> TIM10LPEN_W<'_>[src]

Bit 17 - TIM10 clock enable during Sleep mode

pub fn tim11lpen(&mut self) -> TIM11LPEN_W<'_>[src]

Bit 18 - TIM11 clock enable during Sleep mode

pub fn spi5lpen(&mut self) -> SPI5LPEN_W<'_>[src]

Bit 20 - SPI 5 clock enable during Sleep mode

pub fn sai1lpen(&mut self) -> SAI1LPEN_W<'_>[src]

Bit 22 - SAI1 clock enable during sleep mode

pub fn sai2lpen(&mut self) -> SAI2LPEN_W<'_>[src]

Bit 23 - SAI2 clock enable during sleep mode

pub fn sdmmc1lpen(&mut self) -> SDMMC1LPEN_W<'_>[src]

Bit 11 - SDMMC1 clock enable during Sleep mode

pub fn sdmmc2lpen(&mut self) -> SDMMC2LPEN_W<'_>[src]

Bit 7 - SDMMC2 clock enable during Sleep mode

impl W<u32, Reg<u32, _BDCR>>[src]

pub fn bdrst(&mut self) -> BDRST_W<'_>[src]

Bit 16 - Backup domain software reset

pub fn rtcen(&mut self) -> RTCEN_W<'_>[src]

Bit 15 - RTC clock enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>[src]

Bit 2 - External low-speed oscillator bypass

pub fn lseon(&mut self) -> LSEON_W<'_>[src]

Bit 0 - External low-speed oscillator enable

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>[src]

Bits 3:4 - LSE oscillator drive capability

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>[src]

Bits 8:9 - RTC clock source selection

impl W<u32, Reg<u32, _CSR>>[src]

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>[src]

Bit 31 - Low-power reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>[src]

Bit 30 - Window watchdog reset flag

pub fn wdgrstf(&mut self) -> WDGRSTF_W<'_>[src]

Bit 29 - Independent watchdog reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>[src]

Bit 28 - Software reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>[src]

Bit 27 - POR/PDR reset flag

pub fn padrstf(&mut self) -> PADRSTF_W<'_>[src]

Bit 26 - PIN reset flag

pub fn borrstf(&mut self) -> BORRSTF_W<'_>[src]

Bit 25 - BOR reset flag

pub fn rmvf(&mut self) -> RMVF_W<'_>[src]

Bit 24 - Remove reset flag

pub fn lsion(&mut self) -> LSION_W<'_>[src]

Bit 0 - Internal low-speed oscillator enable

impl W<u32, Reg<u32, _SSCGR>>[src]

pub fn sscgen(&mut self) -> SSCGEN_W<'_>[src]

Bit 31 - Spread spectrum modulation enable

pub fn spreadsel(&mut self) -> SPREADSEL_W<'_>[src]

Bit 30 - Spread Select

pub fn incstep(&mut self) -> INCSTEP_W<'_>[src]

Bits 13:27 - Incrementation step

pub fn modper(&mut self) -> MODPER_W<'_>[src]

Bits 0:12 - Modulation period

impl W<u32, Reg<u32, _PLLI2SCFGR>>[src]

pub fn plli2sr(&mut self) -> PLLI2SR_W<'_>[src]

Bits 28:30 - PLLI2S division factor for I2S clocks

pub fn plli2sq(&mut self) -> PLLI2SQ_W<'_>[src]

Bits 24:27 - PLLI2S division factor for SAI1 clock

pub fn plli2sn(&mut self) -> PLLI2SN_W<'_>[src]

Bits 6:14 - PLLI2S multiplication factor for VCO

impl W<u32, Reg<u32, _PLLSAICFGR>>[src]

pub fn pllsain(&mut self) -> PLLSAIN_W<'_>[src]

Bits 6:14 - PLLSAI division factor for VCO

pub fn pllsaip(&mut self) -> PLLSAIP_W<'_>[src]

Bits 16:17 - PLLSAI division factor for 48MHz clock

pub fn pllsaiq(&mut self) -> PLLSAIQ_W<'_>[src]

Bits 24:27 - PLLSAI division factor for SAI clock

impl W<u32, Reg<u32, _DCKCFGR1>>[src]

pub fn plli2sdivq(&mut self) -> PLLI2SDIVQ_W<'_>[src]

Bits 0:4 - PLLI2S division factor for SAI1 clock

pub fn pllsaidivq(&mut self) -> PLLSAIDIVQ_W<'_>[src]

Bits 8:12 - PLLSAI division factor for SAI1 clock

pub fn sai1sel(&mut self) -> SAI1SEL_W<'_>[src]

Bits 20:21 - SAI1 clock source selection

pub fn sai2sel(&mut self) -> SAI2SEL_W<'_>[src]

Bits 22:23 - SAI2 clock source selection

pub fn timpre(&mut self) -> TIMPRE_W<'_>[src]

Bit 24 - Timers clocks prescalers selection

impl W<u32, Reg<u32, _DCKCFGR2>>[src]

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>[src]

Bits 0:1 - USART 1 clock source selection

pub fn usart2sel(&mut self) -> USART2SEL_W<'_>[src]

Bits 2:3 - USART 2 clock source selection

pub fn usart3sel(&mut self) -> USART3SEL_W<'_>[src]

Bits 4:5 - USART 3 clock source selection

pub fn uart4sel(&mut self) -> UART4SEL_W<'_>[src]

Bits 6:7 - UART 4 clock source selection

pub fn uart5sel(&mut self) -> UART5SEL_W<'_>[src]

Bits 8:9 - UART 5 clock source selection

pub fn usart6sel(&mut self) -> USART6SEL_W<'_>[src]

Bits 10:11 - USART 6 clock source selection

pub fn uart7sel(&mut self) -> UART7SEL_W<'_>[src]

Bits 12:13 - UART 7 clock source selection

pub fn uart8sel(&mut self) -> UART8SEL_W<'_>[src]

Bits 14:15 - UART 8 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>[src]

Bits 16:17 - I2C1 clock source selection

pub fn i2c2sel(&mut self) -> I2C2SEL_W<'_>[src]

Bits 18:19 - I2C2 clock source selection

pub fn i2c3sel(&mut self) -> I2C3SEL_W<'_>[src]

Bits 20:21 - I2C3 clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>[src]

Bits 24:25 - Low power timer 1 clock source selection

pub fn ck48msel(&mut self) -> CK48MSEL_W<'_>[src]

Bit 27 - 48MHz clock source selection

pub fn sdmmc1sel(&mut self) -> SDMMC1SEL_W<'_>[src]

Bit 28 - SDMMC1 clock source selection

pub fn sdmmc2sel(&mut self) -> SDMMC2SEL_W<'_>[src]

Bit 29 - SDMMC2 clock source selection

impl W<u32, Reg<u32, _POWER>>[src]

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>[src]

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>[src]

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>[src]

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>[src]

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>[src]

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>[src]

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>[src]

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>[src]

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>[src]

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>[src]

pub fn cmdarg(&mut self) -> CMDARG_W<'_>[src]

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>[src]

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>[src]

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>[src]

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>[src]

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)

pub fn waitint(&mut self) -> WAITINT_W<'_>[src]

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>[src]

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>[src]

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>[src]

pub fn datatime(&mut self) -> DATATIME_W<'_>[src]

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>[src]

pub fn datalength(&mut self) -> DATALENGTH_W<'_>[src]

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>[src]

pub fn sdioen(&mut self) -> SDIOEN_W<'_>[src]

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>[src]

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>[src]

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>[src]

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>[src]

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>[src]

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer

pub fn dtdir(&mut self) -> DTDIR_W<'_>[src]

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>[src]

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>[src]

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>[src]

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>[src]

Bit 10 - DBCKEND flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>[src]

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>[src]

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>[src]

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>[src]

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>[src]

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>[src]

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>[src]

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>[src]

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>[src]

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>[src]

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>[src]

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>[src]

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>[src]

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>[src]

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>[src]

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>[src]

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>[src]

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>[src]

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>[src]

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>[src]

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>[src]

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>[src]

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>[src]

Bit 10 - Data block end interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>[src]

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>[src]

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>[src]

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>[src]

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>[src]

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>[src]

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>[src]

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>[src]

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>[src]

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>[src]

pub fn fifodata(&mut self) -> FIFODATA_W<'_>[src]

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _CR1>>[src]

pub fn mckdiv(&mut self) -> MCKDIV_W<'_>[src]

Bits 20:23 - Master clock divider

pub fn nodiv(&mut self) -> NODIV_W<'_>[src]

Bit 19 - No divider

pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]

Bit 17 - DMA enable

pub fn saien(&mut self) -> SAIEN_W<'_>[src]

Bit 16 - Audio block A enable

pub fn outdriv(&mut self) -> OUTDRIV_W<'_>[src]

Bit 13 - Output drive

pub fn mono(&mut self) -> MONO_W<'_>[src]

Bit 12 - Mono mode

pub fn syncen(&mut self) -> SYNCEN_W<'_>[src]

Bits 10:11 - Synchronization enable

pub fn ckstr(&mut self) -> CKSTR_W<'_>[src]

Bit 9 - Clock strobing edge

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>[src]

Bit 8 - Least significant bit first

pub fn ds(&mut self) -> DS_W<'_>[src]

Bits 5:7 - Data size

pub fn prtcfg(&mut self) -> PRTCFG_W<'_>[src]

Bits 2:3 - Protocol configuration

pub fn mode(&mut self) -> MODE_W<'_>[src]

Bits 0:1 - Audio block mode

impl W<u32, Reg<u32, _CR2>>[src]

pub fn comp(&mut self) -> COMP_W<'_>[src]

Bits 14:15 - Companding mode

pub fn cpl(&mut self) -> CPL_W<'_>[src]

Bit 13 - Complement bit

pub fn mutecn(&mut self) -> MUTECN_W<'_>[src]

Bits 7:12 - Mute counter

pub fn muteval(&mut self) -> MUTEVAL_W<'_>[src]

Bit 6 - Mute value

pub fn mute(&mut self) -> MUTE_W<'_>[src]

Bit 5 - Mute

pub fn tris(&mut self) -> TRIS_W<'_>[src]

Bit 4 - Tristate management on data line

pub fn fflush(&mut self) -> FFLUSH_W<'_>[src]

Bit 3 - FIFO flush

pub fn fth(&mut self) -> FTH_W<'_>[src]

Bits 0:2 - FIFO threshold

impl W<u32, Reg<u32, _FRCR>>[src]

pub fn fsoff(&mut self) -> FSOFF_W<'_>[src]

Bit 18 - Frame synchronization offset

pub fn fspol(&mut self) -> FSPOL_W<'_>[src]

Bit 17 - Frame synchronization polarity

pub fn fsdef(&mut self) -> FSDEF_W<'_>[src]

Bit 16 - Frame synchronization definition

pub fn fsall(&mut self) -> FSALL_W<'_>[src]

Bits 8:14 - Frame synchronization active level length

pub fn frl(&mut self) -> FRL_W<'_>[src]

Bits 0:7 - Frame length

impl W<u32, Reg<u32, _SLOTR>>[src]

pub fn sloten(&mut self) -> SLOTEN_W<'_>[src]

Bits 16:31 - Slot enable

pub fn nbslot(&mut self) -> NBSLOT_W<'_>[src]

Bits 8:11 - Number of slots in an audio frame

pub fn slotsz(&mut self) -> SLOTSZ_W<'_>[src]

Bits 6:7 - Slot size

pub fn fboff(&mut self) -> FBOFF_W<'_>[src]

Bits 0:4 - First bit offset

impl W<u32, Reg<u32, _IM>>[src]

pub fn lfsdetie(&mut self) -> LFSDETIE_W<'_>[src]

Bit 6 - Late frame synchronization detection interrupt enable

pub fn afsdetie(&mut self) -> AFSDETIE_W<'_>[src]

Bit 5 - Anticipated frame synchronization detection interrupt enable

pub fn cnrdyie(&mut self) -> CNRDYIE_W<'_>[src]

Bit 4 - Codec not ready interrupt enable

pub fn freqie(&mut self) -> FREQIE_W<'_>[src]

Bit 3 - FIFO request interrupt enable

pub fn wckcfgie(&mut self) -> WCKCFGIE_W<'_>[src]

Bit 2 - Wrong clock configuration interrupt enable

pub fn mutedetie(&mut self) -> MUTEDETIE_W<'_>[src]

Bit 1 - Mute detection interrupt enable

pub fn ovrudrie(&mut self) -> OVRUDRIE_W<'_>[src]

Bit 0 - Overrun/underrun interrupt enable

impl W<u32, Reg<u32, _CLRFR>>[src]

pub fn clfsdet(&mut self) -> CLFSDET_W<'_>[src]

Bit 6 - Clear late frame synchronization detection flag

pub fn cafsdet(&mut self) -> CAFSDET_W<'_>[src]

Bit 5 - Clear anticipated frame synchronization detection flag.

pub fn ccnrdy(&mut self) -> CCNRDY_W<'_>[src]

Bit 4 - Clear codec not ready flag

pub fn cwckcfg(&mut self) -> CWCKCFG_W<'_>[src]

Bit 2 - Clear wrong clock configuration flag

pub fn cmutedet(&mut self) -> CMUTEDET_W<'_>[src]

Bit 1 - Mute detection flag

pub fn covrudr(&mut self) -> COVRUDR_W<'_>[src]

Bit 0 - Clear overrun / underrun

impl W<u32, Reg<u32, _DR>>[src]

pub fn data(&mut self) -> DATA_W<'_>[src]

Bits 0:31 - Data

impl W<u32, Reg<u32, _GCR>>[src]

pub fn syncin(&mut self) -> SYNCIN_W<'_>[src]

Bits 0:1 - Synchronization inputs

pub fn syncout(&mut self) -> SYNCOUT_W<'_>[src]

Bits 4:5 - Synchronization outputs

impl W<u32, Reg<u32, _CR1>>[src]

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>[src]

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>[src]

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>[src]

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>[src]

Bit 12 - CRC transfer next

pub fn crcl(&mut self) -> CRCL_W<'_>[src]

Bit 11 - CRC length

pub fn rxonly(&mut self) -> RXONLY_W<'_>[src]

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>[src]

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>[src]

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>[src]

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>[src]

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>[src]

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>[src]

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>[src]

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>[src]

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>[src]

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>[src]

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>[src]

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>[src]

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>[src]

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>[src]

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>[src]

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>[src]

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>[src]

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>[src]

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>[src]

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>[src]

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>[src]

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>[src]

pub fn crcerr(&mut self) -> CRCERR_W<'_>[src]

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>[src]

pub fn dr(&mut self) -> DR_W<'_>[src]

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>[src]

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>[src]

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>[src]

pub fn i2smod(&mut self) -> I2SMOD_W<'_>[src]

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>[src]

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>[src]

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>[src]

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>[src]

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>[src]

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>[src]

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>[src]

Bit 0 - Channel length (number of bits per audio channel)

pub fn astrten(&mut self) -> ASTRTEN_W<'_>[src]

Bit 12 - Asynchronous start enable

impl W<u32, Reg<u32, _I2SPR>>[src]

pub fn mckoe(&mut self) -> MCKOE_W<'_>[src]

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>[src]

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>[src]

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _MEMRMP>>[src]

pub fn mem_boot(&mut self) -> MEM_BOOT_W<'_>[src]

Bit 0 - Memory boot mapping

pub fn swp_fmc(&mut self) -> SWP_FMC_W<'_>[src]

Bits 10:11 - FMC memory mapping swap

impl W<u32, Reg<u32, _PMC>>[src]

pub fn pb7_fmp(&mut self) -> PB7_FMP_W<'_>[src]

Bit 5 - PB7_FMP Fast Mode + Enable

pub fn pb8_fmp(&mut self) -> PB8_FMP_W<'_>[src]

Bit 6 - PB8_FMP Fast Mode + Enable

pub fn pb9_fmp(&mut self) -> PB9_FMP_W<'_>[src]

Bit 7 - Fast Mode + Enable

pub fn adcdc2(&mut self) -> ADCDC2_W<'_>[src]

Bits 16:18 - ADC3DC2

pub fn pb6_fmp(&mut self) -> PB6_FMP_W<'_>[src]

Bit 4 - PB6_FMP Fast Mode

pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W<'_>[src]

Bit 2 - I2C3_FMP I2C3 Fast Mode + Enable

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>[src]

Bit 1 - I2C2_FMP I2C2 Fast Mode + Enable

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>[src]

Bit 0 - I2C1_FMP I2C1 Fast Mode + Enable

impl W<u32, Reg<u32, _EXTICR1>>[src]

pub fn exti3(&mut self) -> EXTI3_W<'_>[src]

Bits 12:15 - EXTI x configuration (x = 0 to 3)

pub fn exti2(&mut self) -> EXTI2_W<'_>[src]

Bits 8:11 - EXTI x configuration (x = 0 to 3)

pub fn exti1(&mut self) -> EXTI1_W<'_>[src]

Bits 4:7 - EXTI x configuration (x = 0 to 3)

pub fn exti0(&mut self) -> EXTI0_W<'_>[src]

Bits 0:3 - EXTI x configuration (x = 0 to 3)

impl W<u32, Reg<u32, _EXTICR2>>[src]

pub fn exti7(&mut self) -> EXTI7_W<'_>[src]

Bits 12:15 - EXTI x configuration (x = 4 to 7)

pub fn exti6(&mut self) -> EXTI6_W<'_>[src]

Bits 8:11 - EXTI x configuration (x = 4 to 7)

pub fn exti5(&mut self) -> EXTI5_W<'_>[src]

Bits 4:7 - EXTI x configuration (x = 4 to 7)

pub fn exti4(&mut self) -> EXTI4_W<'_>[src]

Bits 0:3 - EXTI x configuration (x = 4 to 7)

impl W<u32, Reg<u32, _EXTICR3>>[src]

pub fn exti11(&mut self) -> EXTI11_W<'_>[src]

Bits 12:15 - EXTI x configuration (x = 8 to 11)

pub fn exti10(&mut self) -> EXTI10_W<'_>[src]

Bits 8:11 - EXTI10

pub fn exti9(&mut self) -> EXTI9_W<'_>[src]

Bits 4:7 - EXTI x configuration (x = 8 to 11)

pub fn exti8(&mut self) -> EXTI8_W<'_>[src]

Bits 0:3 - EXTI x configuration (x = 8 to 11)

impl W<u32, Reg<u32, _EXTICR4>>[src]

pub fn exti15(&mut self) -> EXTI15_W<'_>[src]

Bits 12:15 - EXTI x configuration (x = 12 to 15)

pub fn exti14(&mut self) -> EXTI14_W<'_>[src]

Bits 8:11 - EXTI x configuration (x = 12 to 15)

pub fn exti13(&mut self) -> EXTI13_W<'_>[src]

Bits 4:7 - EXTI x configuration (x = 12 to 15)

pub fn exti12(&mut self) -> EXTI12_W<'_>[src]

Bits 0:3 - EXTI x configuration (x = 12 to 15)

impl W<u32, Reg<u32, _CR1>>[src]

pub fn m1(&mut self) -> M1_W<'_>[src]

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>[src]

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>[src]

Bit 26 - Receiver timeout interrupt enable

pub fn over8(&mut self) -> OVER8_W<'_>[src]

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>[src]

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>[src]

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>[src]

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>[src]

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>[src]

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>[src]

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>[src]

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>[src]

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>[src]

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>[src]

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>[src]

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>[src]

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>[src]

Bit 2 - Receiver enable

pub fn ue(&mut self) -> UE_W<'_>[src]

Bit 0 - USART enable

pub fn deat(&mut self) -> DEAT_W<'_>[src]

Bits 21:25 - Driver Enable assertion time

pub fn dedt(&mut self) -> DEDT_W<'_>[src]

Bits 16:20 - Driver Enable de-assertion time

impl W<u32, Reg<u32, _CR2>>[src]

pub fn rtoen(&mut self) -> RTOEN_W<'_>[src]

Bit 23 - Receiver timeout enable

pub fn abren(&mut self) -> ABREN_W<'_>[src]

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>[src]

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>[src]

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>[src]

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>[src]

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>[src]

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>[src]

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>[src]

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>[src]

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>[src]

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>[src]

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>[src]

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>[src]

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>[src]

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>[src]

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn add(&mut self) -> ADD_W<'_>[src]

Bits 24:31 - Address of the USART node

pub fn abrmod(&mut self) -> ABRMOD_W<'_>[src]

Bits 21:22 - Auto baud rate mode

impl W<u32, Reg<u32, _CR3>>[src]

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>[src]

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>[src]

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>[src]

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>[src]

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>[src]

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>[src]

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>[src]

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>[src]

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>[src]

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>[src]

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>[src]

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>[src]

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>[src]

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>[src]

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>[src]

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>[src]

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>[src]

Bit 0 - Error interrupt enable

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>[src]

Bit 24 - Transmission complete before guard time interrupt enable

impl W<u32, Reg<u32, _BRR>>[src]

pub fn brr(&mut self) -> BRR_W<'_>[src]

Bits 0:15 - USARTDIV

impl W<u32, Reg<u32, _GTPR>>[src]

pub fn gt(&mut self) -> GT_W<'_>[src]

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>[src]

pub fn blen(&mut self) -> BLEN_W<'_>[src]

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>[src]

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>[src]

pub fn txfrq(&mut self) -> TXFRQ_W<'_>[src]

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>[src]

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>[src]

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>[src]

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>[src]

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>[src]

pub fn cmcf(&mut self) -> CMCF_W<'_>[src]

Bit 17 - Character match clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>[src]

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>[src]

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>[src]

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>[src]

Bit 8 - LIN break detection clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>[src]

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>[src]

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>[src]

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>[src]

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>[src]

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>[src]

Bit 0 - Parity error clear flag

pub fn tcbgtcf(&mut self) -> TCBGTCF_W<'_>[src]

Bit 7 - Transmission completed before guard time clear flag

impl W<u32, Reg<u32, _TDR>>[src]

pub fn tdr(&mut self) -> TDR_W<'_>[src]

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _OTG_FS_GOTGCTL>>[src]

pub fn srq(&mut self) -> SRQ_W<'_>[src]

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>[src]

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>[src]

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>[src]

Bit 11 - Device HNP enabled

pub fn vbvaloen(&mut self) -> VBVALOEN_W<'_>[src]

Bit 2 - VBUS valid override enable

pub fn vbvaloval(&mut self) -> VBVALOVAL_W<'_>[src]

Bit 3 - VBUS valid override value

pub fn avaloen(&mut self) -> AVALOEN_W<'_>[src]

Bit 4 - A-peripheral session valid override enable

pub fn avaloval(&mut self) -> AVALOVAL_W<'_>[src]

Bit 5 - A-peripheral session valid override value

pub fn bvaloen(&mut self) -> BVALOEN_W<'_>[src]

Bit 6 - B-peripheral session valid override enable

pub fn bvaloval(&mut self) -> BVALOVAL_W<'_>[src]

Bit 7 - B-peripheral session valid override value

pub fn ehen(&mut self) -> EHEN_W<'_>[src]

Bit 12 - Embedded host enable

pub fn otgver(&mut self) -> OTGVER_W<'_>[src]

Bit 20 - OTG version

impl W<u32, Reg<u32, _OTG_FS_GOTGINT>>[src]

pub fn sedet(&mut self) -> SEDET_W<'_>[src]

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>[src]

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>[src]

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>[src]

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>[src]

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>[src]

Bit 19 - Debounce done

pub fn idchng(&mut self) -> IDCHNG_W<'_>[src]

Bit 20 - ID input pin changed

impl W<u32, Reg<u32, _OTG_FS_GAHBCFG>>[src]

pub fn gint(&mut self) -> GINT_W<'_>[src]

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>[src]

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>[src]

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _OTG_FS_GUSBCFG>>[src]

pub fn tocal(&mut self) -> TOCAL_W<'_>[src]

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>[src]

Bit 6 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>[src]

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>[src]

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>[src]

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>[src]

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>[src]

Bit 30 - Force device mode

impl W<u32, Reg<u32, _OTG_FS_GRSTCTL>>[src]

pub fn csrst(&mut self) -> CSRST_W<'_>[src]

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>[src]

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>[src]

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>[src]

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>[src]

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _OTG_FS_GINTSTS>>[src]

pub fn mmis(&mut self) -> MMIS_W<'_>[src]

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>[src]

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>[src]

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>[src]

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>[src]

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>[src]

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>[src]

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>[src]

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>[src]

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>[src]

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>[src]

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>[src]

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>[src]

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>[src]

Bit 31 - Resume/remote wakeup detected interrupt

pub fn rstdet(&mut self) -> RSTDET_W<'_>[src]

Bit 23 - Reset detected interrupt

impl W<u32, Reg<u32, _OTG_FS_GINTMSK>>[src]

pub fn mmism(&mut self) -> MMISM_W<'_>[src]

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>[src]

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>[src]

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>[src]

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>[src]

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>[src]

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>[src]

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>[src]

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>[src]

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>[src]

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>[src]

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>[src]

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>[src]

Bit 15 - End of periodic frame interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>[src]

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>[src]

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>[src]

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>[src]

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>[src]

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>[src]

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>[src]

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>[src]

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>[src]

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>[src]

Bit 31 - Resume/remote wakeup detected interrupt mask

pub fn rstdetm(&mut self) -> RSTDETM_W<'_>[src]

Bit 23 - Reset detected interrupt mask

pub fn lpmin(&mut self) -> LPMIN_W<'_>[src]

Bit 27 - LPM interrupt mask

impl W<u32, Reg<u32, _OTG_FS_GRXFSIZ>>[src]

pub fn rxfd(&mut self) -> RXFD_W<'_>[src]

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF0_DEVICE>>[src]

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>[src]

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>[src]

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_HNPTXFSIZ_HOST>>[src]

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>[src]

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>[src]

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_GCCFG>>[src]

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>[src]

Bit 16 - Power down

pub fn bcden(&mut self) -> BCDEN_W<'_>[src]

Bit 17 - Battery charging detector (BCD) enable

pub fn dcden(&mut self) -> DCDEN_W<'_>[src]

Bit 18 - Data contact detection (DCD) mode enable

pub fn pden(&mut self) -> PDEN_W<'_>[src]

Bit 19 - Primary detection (PD) mode enable

pub fn sden(&mut self) -> SDEN_W<'_>[src]

Bit 20 - Secondary detection (SD) mode enable

pub fn vbden(&mut self) -> VBDEN_W<'_>[src]

Bit 21 - USB VBUS detection enable

pub fn dcdet(&mut self) -> DCDET_W<'_>[src]

Bit 0 - Data contact detection (DCD) status

pub fn pdet(&mut self) -> PDET_W<'_>[src]

Bit 1 - Primary detection (PD) status

pub fn sdet(&mut self) -> SDET_W<'_>[src]

Bit 2 - Secondary detection (SD) status

pub fn ps2det(&mut self) -> PS2DET_W<'_>[src]

Bit 3 - DM pull-up detection status

impl W<u32, Reg<u32, _OTG_FS_CID>>[src]

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>[src]

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _OTG_FS_HPTXFSIZ>>[src]

pub fn ptxsa(&mut self) -> PTXSA_W<'_>[src]

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>[src]

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF1>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF2>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF3>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_GI2CCTL>>[src]

pub fn rwdata(&mut self) -> RWDATA_W<'_>[src]

Bits 0:7 - I2C Read/Write Data

pub fn regaddr(&mut self) -> REGADDR_W<'_>[src]

Bits 8:15 - I2C Register Address

pub fn addr(&mut self) -> ADDR_W<'_>[src]

Bits 16:22 - I2C Address

pub fn i2cen(&mut self) -> I2CEN_W<'_>[src]

Bit 23 - I2C Enable

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 24 - I2C ACK

pub fn i2cdevadr(&mut self) -> I2CDEVADR_W<'_>[src]

Bits 26:27 - I2C Device Address

pub fn i2cdatse0(&mut self) -> I2CDATSE0_W<'_>[src]

Bit 28 - I2C DatSe0 USB mode

pub fn rw(&mut self) -> RW_W<'_>[src]

Bit 30 - Read/Write Indicator

pub fn bsydne(&mut self) -> BSYDNE_W<'_>[src]

Bit 31 - I2C Busy/Done

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF4>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint Tx FIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF5>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint Tx FIFO depth

impl W<u32, Reg<u32, _OTG_FS_GLPMCFG>>[src]

pub fn lpmen(&mut self) -> LPMEN_W<'_>[src]

Bit 0 - LPM support enable

pub fn lpmack(&mut self) -> LPMACK_W<'_>[src]

Bit 1 - LPM token acknowledge enable

pub fn besl(&mut self) -> BESL_W<'_>[src]

Bits 2:5 - Best effort service latency

pub fn remwake(&mut self) -> REMWAKE_W<'_>[src]

Bit 6 - bRemoteWake value

pub fn l1ssen(&mut self) -> L1SSEN_W<'_>[src]

Bit 7 - L1 Shallow Sleep enable

pub fn beslthrs(&mut self) -> BESLTHRS_W<'_>[src]

Bits 8:11 - BESL threshold

pub fn l1dsen(&mut self) -> L1DSEN_W<'_>[src]

Bit 12 - L1 deep sleep enable

pub fn lpmchidx(&mut self) -> LPMCHIDX_W<'_>[src]

Bits 17:20 - LPM Channel Index

pub fn lpmrcnt(&mut self) -> LPMRCNT_W<'_>[src]

Bits 21:23 - LPM retry count

pub fn sndlpm(&mut self) -> SNDLPM_W<'_>[src]

Bit 24 - Send LPM transaction

pub fn enbesl(&mut self) -> ENBESL_W<'_>[src]

Bit 28 - Enable best effort service latency

impl W<u32, Reg<u32, _OTG_FS_HCFG>>[src]

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>[src]

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _OTG_FS_HFIR>>[src]

pub fn frivl(&mut self) -> FRIVL_W<'_>[src]

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _OTG_FS_HPTXSTS>>[src]

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>[src]

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _OTG_FS_HAINTMSK>>[src]

pub fn haintm(&mut self) -> HAINTM_W<'_>[src]

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _OTG_FS_HPRT>>[src]

pub fn pcdet(&mut self) -> PCDET_W<'_>[src]

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>[src]

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>[src]

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>[src]

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>[src]

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>[src]

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>[src]

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>[src]

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>[src]

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _OTG_FS_HCCHAR0>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR1>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR2>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR3>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR4>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR5>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR6>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR7>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT0>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT1>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT2>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT3>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT4>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT5>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT6>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT7>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK0>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK1>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK2>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK3>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK4>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK5>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK6>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK7>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ0>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ1>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ2>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ3>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ4>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ5>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ6>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ7>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCCHAR8>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT8>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK8>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ8>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCCHAR9>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT9>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK9>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ9>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCCHAR10>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT10>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK10>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ10>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCCHAR11>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT11>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK11>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ11>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_DCFG>>[src]

pub fn dspd(&mut self) -> DSPD_W<'_>[src]

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>[src]

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>[src]

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _OTG_FS_DCTL>>[src]

pub fn rwusig(&mut self) -> RWUSIG_W<'_>[src]

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>[src]

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>[src]

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>[src]

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>[src]

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>[src]

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>[src]

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>[src]

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _OTG_FS_DIEPMSK>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>[src]

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>[src]

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>[src]

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>[src]

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>[src]

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _OTG_FS_DOEPMSK>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>[src]

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>[src]

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _OTG_FS_DAINTMSK>>[src]

pub fn iepm(&mut self) -> IEPM_W<'_>[src]

Bits 0:15 - IN EP interrupt mask bits

pub fn oepint(&mut self) -> OEPINT_W<'_>[src]

Bits 16:31 - OUT endpoint interrupt bits

impl W<u32, Reg<u32, _OTG_FS_DVBUSDIS>>[src]

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>[src]

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _OTG_FS_DVBUSPULSE>>[src]

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>[src]

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _OTG_FS_DIEPEMPMSK>>[src]

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>[src]

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL0>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL1>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>[src]

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL2>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL3>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL0>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL1>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL2>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL3>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPINT0>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPINT1>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPINT2>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPINT3>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPINT0>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPINT1>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPINT2>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPINT3>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ0>>[src]

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ0>>[src]

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>[src]

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ1>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ2>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ3>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ1>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ2>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ3>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL4>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPINT4>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ4>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DTXFSTS4>>[src]

pub fn ineptfsav(&mut self) -> INEPTFSAV_W<'_>[src]

Bits 0:15 - IN endpoint TxFIFO space available

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL5>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPINT5>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ5>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DTXFSTS5>>[src]

pub fn ineptfsav(&mut self) -> INEPTFSAV_W<'_>[src]

Bits 0:15 - IN endpoint TxFIFO space available

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL4>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPINT4>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ4>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL5>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPINT5>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ5>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_PCGCCTL>>[src]

pub fn stppclk(&mut self) -> STPPCLK_W<'_>[src]

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>[src]

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>[src]

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _OTG_HS_HCFG>>[src]

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>[src]

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _OTG_HS_HFIR>>[src]

pub fn frivl(&mut self) -> FRIVL_W<'_>[src]

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _OTG_HS_HPTXSTS>>[src]

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>[src]

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _OTG_HS_HAINTMSK>>[src]

pub fn haintm(&mut self) -> HAINTM_W<'_>[src]

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _OTG_HS_HPRT>>[src]

pub fn pcdet(&mut self) -> PCDET_W<'_>[src]

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>[src]

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>[src]

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>[src]

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>[src]

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>[src]

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>[src]

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>[src]

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>[src]

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _OTG_HS_HCCHAR0>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR1>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR2>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR3>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR4>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR5>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR6>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR7>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR8>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR9>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR10>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR11>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT0>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT1>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT2>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT3>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT4>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT5>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT6>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT7>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT8>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT9>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT10>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT11>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT0>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT1>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT2>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT3>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT4>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT5>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT6>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT7>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT8>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT9>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT10>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT11>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK0>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK1>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK2>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK3>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK4>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK5>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK6>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK7>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK8>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK9>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK10>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK11>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ0>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ1>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ2>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ3>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ4>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ5>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ6>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ7>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ8>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ9>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ10>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ11>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA0>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA1>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA2>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA3>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA4>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA5>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA6>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA7>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA8>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA9>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA10>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA11>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCCHAR12>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT12>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT12>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK12>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ12>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA12>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCCHAR13>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT13>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT13>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK13>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALLM response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ13>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA13>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCCHAR14>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT14>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT14>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK14>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAKM response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACKM response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ14>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA14>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCCHAR15>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT15>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT15>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK15>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ15>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA15>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_GOTGCTL>>[src]

pub fn srq(&mut self) -> SRQ_W<'_>[src]

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>[src]

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>[src]

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>[src]

Bit 11 - Device HNP enabled

pub fn ehen(&mut self) -> EHEN_W<'_>[src]

Bit 12 - Embedded host enable

impl W<u32, Reg<u32, _OTG_HS_GOTGINT>>[src]

pub fn sedet(&mut self) -> SEDET_W<'_>[src]

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>[src]

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>[src]

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>[src]

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>[src]

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>[src]

Bit 19 - Debounce done

pub fn idchng(&mut self) -> IDCHNG_W<'_>[src]

Bit 20 - ID input pin changed

impl W<u32, Reg<u32, _OTG_HS_GAHBCFG>>[src]

pub fn gint(&mut self) -> GINT_W<'_>[src]

Bit 0 - Global interrupt mask

pub fn hbstlen(&mut self) -> HBSTLEN_W<'_>[src]

Bits 1:4 - Burst length/type

pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]

Bit 5 - DMA enable

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>[src]

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>[src]

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _OTG_HS_GUSBCFG>>[src]

pub fn tocal(&mut self) -> TOCAL_W<'_>[src]

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>[src]

Bit 6 - USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>[src]

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>[src]

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>[src]

Bits 10:13 - USB turnaround time

pub fn phylpcs(&mut self) -> PHYLPCS_W<'_>[src]

Bit 15 - PHY Low-power clock select

pub fn ulpifsls(&mut self) -> ULPIFSLS_W<'_>[src]

Bit 17 - ULPI FS/LS select

pub fn ulpiar(&mut self) -> ULPIAR_W<'_>[src]

Bit 18 - ULPI Auto-resume

pub fn ulpicsm(&mut self) -> ULPICSM_W<'_>[src]

Bit 19 - ULPI Clock SuspendM

pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<'_>[src]

Bit 20 - ULPI External VBUS Drive

pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<'_>[src]

Bit 21 - ULPI external VBUS indicator

pub fn tsdps(&mut self) -> TSDPS_W<'_>[src]

Bit 22 - TermSel DLine pulsing selection

pub fn pcci(&mut self) -> PCCI_W<'_>[src]

Bit 23 - Indicator complement

pub fn ptci(&mut self) -> PTCI_W<'_>[src]

Bit 24 - Indicator pass through

pub fn ulpiipd(&mut self) -> ULPIIPD_W<'_>[src]

Bit 25 - ULPI interface protect disable

pub fn fhmod(&mut self) -> FHMOD_W<'_>[src]

Bit 29 - Forced host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>[src]

Bit 30 - Forced peripheral mode

impl W<u32, Reg<u32, _OTG_HS_GRSTCTL>>[src]

pub fn csrst(&mut self) -> CSRST_W<'_>[src]

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>[src]

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>[src]

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>[src]

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>[src]

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _OTG_HS_GINTSTS>>[src]

pub fn mmis(&mut self) -> MMIS_W<'_>[src]

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>[src]

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>[src]

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>[src]

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>[src]

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>[src]

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>[src]

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>[src]

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>[src]

Bit 20 - Incomplete isochronous IN transfer

pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<'_>[src]

Bit 21 - Incomplete periodic transfer

pub fn datafsusp(&mut self) -> DATAFSUSP_W<'_>[src]

Bit 22 - Data fetch suspended

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>[src]

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>[src]

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>[src]

Bit 30 - Session request/new session detected interrupt

pub fn wkuint(&mut self) -> WKUINT_W<'_>[src]

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _OTG_HS_GINTMSK>>[src]

pub fn mmism(&mut self) -> MMISM_W<'_>[src]

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>[src]

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>[src]

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>[src]

Bit 4 - Receive FIFO nonempty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>[src]

Bit 5 - Nonperiodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>[src]

Bit 6 - Global nonperiodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>[src]

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>[src]

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>[src]

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>[src]

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>[src]

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>[src]

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>[src]

Bit 15 - End of periodic frame interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>[src]

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>[src]

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>[src]

Bit 20 - Incomplete isochronous IN transfer mask

pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<'_>[src]

Bit 21 - Incomplete periodic transfer mask

pub fn fsuspm(&mut self) -> FSUSPM_W<'_>[src]

Bit 22 - Data fetch suspended mask

pub fn hcim(&mut self) -> HCIM_W<'_>[src]

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>[src]

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>[src]

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>[src]

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>[src]

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>[src]

Bit 31 - Resume/remote wakeup detected interrupt mask

pub fn rstde(&mut self) -> RSTDE_W<'_>[src]

Bit 23 - Reset detected interrupt mask

pub fn lpmintm(&mut self) -> LPMINTM_W<'_>[src]

Bit 27 - LPM interrupt mask

impl W<u32, Reg<u32, _OTG_HS_GRXFSIZ>>[src]

pub fn rxfd(&mut self) -> RXFD_W<'_>[src]

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_HNPTXFSIZ_HOST>>[src]

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>[src]

Bits 0:15 - Nonperiodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>[src]

Bits 16:31 - Nonperiodic TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF0_DEVICE>>[src]

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>[src]

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>[src]

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_GCCFG>>[src]

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>[src]

Bit 16 - Power down

pub fn bcden(&mut self) -> BCDEN_W<'_>[src]

Bit 17 - Battery charging detector (BCD) enable

pub fn dcden(&mut self) -> DCDEN_W<'_>[src]

Bit 18 - Data contact detection (DCD) mode enable

pub fn pden(&mut self) -> PDEN_W<'_>[src]

Bit 19 - Primary detection (PD) mode enable

pub fn sden(&mut self) -> SDEN_W<'_>[src]

Bit 20 - Secondary detection (SD) mode enable

pub fn vbden(&mut self) -> VBDEN_W<'_>[src]

Bit 21 - USB VBUS detection enable

pub fn dcdet(&mut self) -> DCDET_W<'_>[src]

Bit 0 - Data contact detection (DCD) status

pub fn pdet(&mut self) -> PDET_W<'_>[src]

Bit 1 - Primary detection (PD) status

pub fn sdet(&mut self) -> SDET_W<'_>[src]

Bit 2 - Secondary detection (SD) status

pub fn ps2det(&mut self) -> PS2DET_W<'_>[src]

Bit 3 - DM pull-up detection status

impl W<u32, Reg<u32, _OTG_HS_CID>>[src]

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>[src]

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _OTG_HS_HPTXFSIZ>>[src]

pub fn ptxsa(&mut self) -> PTXSA_W<'_>[src]

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfd(&mut self) -> PTXFD_W<'_>[src]

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF1>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF2>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF3>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF4>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF5>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF6>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF7>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_GLPMCFG>>[src]

pub fn lpmen(&mut self) -> LPMEN_W<'_>[src]

Bit 0 - LPM support enable

pub fn lpmack(&mut self) -> LPMACK_W<'_>[src]

Bit 1 - LPM token acknowledge enable

pub fn l1ssen(&mut self) -> L1SSEN_W<'_>[src]

Bit 7 - L1 Shallow Sleep enable

pub fn beslthrs(&mut self) -> BESLTHRS_W<'_>[src]

Bits 8:11 - BESL threshold

pub fn l1dsen(&mut self) -> L1DSEN_W<'_>[src]

Bit 12 - L1 deep sleep enable

pub fn lpmchidx(&mut self) -> LPMCHIDX_W<'_>[src]

Bits 17:20 - LPM Channel Index

pub fn lpmrcnt(&mut self) -> LPMRCNT_W<'_>[src]

Bits 21:23 - LPM retry count

pub fn sndlpm(&mut self) -> SNDLPM_W<'_>[src]

Bit 24 - Send LPM transaction

pub fn enbesl(&mut self) -> ENBESL_W<'_>[src]

Bit 28 - Enable best effort service latency

impl W<u32, Reg<u32, _OTG_HS_GI2CCTL>>[src]

pub fn bsydne(&mut self) -> BSYDNE_W<'_>[src]

Bit 31 - I2C Busy/Done

pub fn rw(&mut self) -> RW_W<'_>[src]

Bit 30 - Read/Write Indicator

pub fn i2cdatse0(&mut self) -> I2CDATSE0_W<'_>[src]

Bit 28 - I2C DatSe0 USB mode

pub fn i2cdevadr(&mut self) -> I2CDEVADR_W<'_>[src]

Bits 26:27 - I2C Device Address

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 24 - I2C ACK

pub fn i2cen(&mut self) -> I2CEN_W<'_>[src]

Bit 23 - I2C Enable

pub fn addr(&mut self) -> ADDR_W<'_>[src]

Bits 16:22 - I2C Address

pub fn regaddr(&mut self) -> REGADDR_W<'_>[src]

Bits 8:15 - I2C Register Address

pub fn rwdata(&mut self) -> RWDATA_W<'_>[src]

Bits 0:7 - I2C Read/Write Data

impl W<u32, Reg<u32, _OTG_HS_PCGCR>>[src]

pub fn stppclk(&mut self) -> STPPCLK_W<'_>[src]

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>[src]

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>[src]

Bit 4 - PHY suspended

impl W<u32, Reg<u32, _OTG_HS_DCFG>>[src]

pub fn dspd(&mut self) -> DSPD_W<'_>[src]

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>[src]

Bit 2 - Nonzero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>[src]

Bits 11:12 - Periodic (micro)frame interval

pub fn perschivl(&mut self) -> PERSCHIVL_W<'_>[src]

Bits 24:25 - Periodic scheduling interval

impl W<u32, Reg<u32, _OTG_HS_DCTL>>[src]

pub fn rwusig(&mut self) -> RWUSIG_W<'_>[src]

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>[src]

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>[src]

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>[src]

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>[src]

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>[src]

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>[src]

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>[src]

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _OTG_HS_DIEPMSK>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>[src]

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>[src]

Bit 3 - Timeout condition mask (nonisochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>[src]

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>[src]

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>[src]

Bit 6 - IN endpoint NAK effective mask

pub fn txfurm(&mut self) -> TXFURM_W<'_>[src]

Bit 8 - FIFO underrun mask

pub fn bim(&mut self) -> BIM_W<'_>[src]

Bit 9 - BNA interrupt mask

impl W<u32, Reg<u32, _OTG_HS_DOEPMSK>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>[src]

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>[src]

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled mask

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received mask

pub fn opem(&mut self) -> OPEM_W<'_>[src]

Bit 8 - OUT packet error mask

pub fn boim(&mut self) -> BOIM_W<'_>[src]

Bit 9 - BNA interrupt mask

impl W<u32, Reg<u32, _OTG_HS_DAINTMSK>>[src]

pub fn iepm(&mut self) -> IEPM_W<'_>[src]

Bits 0:15 - IN EP interrupt mask bits

pub fn oepm(&mut self) -> OEPM_W<'_>[src]

Bits 16:31 - OUT EP interrupt mask bits

impl W<u32, Reg<u32, _OTG_HS_DVBUSDIS>>[src]

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>[src]

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _OTG_HS_DVBUSPULSE>>[src]

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>[src]

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _OTG_HS_DTHRCTL>>[src]

pub fn nonisothren(&mut self) -> NONISOTHREN_W<'_>[src]

Bit 0 - Nonisochronous IN endpoints threshold enable

pub fn isothren(&mut self) -> ISOTHREN_W<'_>[src]

Bit 1 - ISO IN endpoint threshold enable

pub fn txthrlen(&mut self) -> TXTHRLEN_W<'_>[src]

Bits 2:10 - Transmit threshold length

pub fn rxthren(&mut self) -> RXTHREN_W<'_>[src]

Bit 16 - Receive threshold enable

pub fn rxthrlen(&mut self) -> RXTHRLEN_W<'_>[src]

Bits 17:25 - Receive threshold length

pub fn arpen(&mut self) -> ARPEN_W<'_>[src]

Bit 27 - Arbiter parking enable

impl W<u32, Reg<u32, _OTG_HS_DIEPEMPMSK>>[src]

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>[src]

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _OTG_HS_DEACHINT>>[src]

pub fn iep1int(&mut self) -> IEP1INT_W<'_>[src]

Bit 1 - IN endpoint 1interrupt bit

pub fn oep1int(&mut self) -> OEP1INT_W<'_>[src]

Bit 17 - OUT endpoint 1 interrupt bit

impl W<u32, Reg<u32, _OTG_HS_DEACHINTMSK>>[src]

pub fn iep1intm(&mut self) -> IEP1INTM_W<'_>[src]

Bit 1 - IN Endpoint 1 interrupt mask bit

pub fn oep1intm(&mut self) -> OEP1INTM_W<'_>[src]

Bit 17 - OUT Endpoint 1 interrupt mask bit

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL0>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL1>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL2>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL3>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL4>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL5>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL6>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL7>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPINT0>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT1>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT2>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT3>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT4>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT5>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT6>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT7>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ0>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:6 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:20 - Packet count

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA0>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA1>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA2>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA3>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA4>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ1>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ2>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ3>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ4>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ5>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL0>>[src]

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL1>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL2>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL3>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPINT0>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT1>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT2>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT3>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT4>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT5>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT6>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT7>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ0>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:6 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bit 19 - Packet count

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>[src]

Bits 29:30 - SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ1>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ2>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ3>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ4>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ6>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DTXFSTS6>>[src]

pub fn ineptfsav(&mut self) -> INEPTFSAV_W<'_>[src]

Bits 0:15 - IN endpoint TxFIFO space avail

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ7>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DTXFSTS7>>[src]

pub fn ineptfsav(&mut self) -> INEPTFSAV_W<'_>[src]

Bits 0:15 - IN endpoint TxFIFO space avail

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL4>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL5>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL6>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL7>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ5>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ6>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ7>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _CR>>[src]

pub fn wdga(&mut self) -> WDGA_W<'_>[src]

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>[src]

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>[src]

pub fn ewi(&mut self) -> EWI_W<'_>[src]

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>[src]

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>[src]

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>[src]

pub fn ewif(&mut self) -> EWIF_W<'_>[src]

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _CSR>>[src]

pub fn enable(&mut self) -> ENABLE_W<'_>[src]

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>[src]

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>[src]

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>[src]

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _RVR>>[src]

pub fn reload(&mut self) -> RELOAD_W<'_>[src]

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _CVR>>[src]

pub fn current(&mut self) -> CURRENT_W<'_>[src]

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>[src]

pub fn tenms(&mut self) -> TENMS_W<'_>[src]

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>[src]

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>[src]

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>[src]

pub fn intid(&mut self) -> INTID_W<'_>[src]

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>[src]

pub fn cp(&mut self) -> CP_W<'_>[src]

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>[src]

pub fn disfold(&mut self) -> DISFOLD_W<'_>[src]

Bit 2 - DISFOLD

pub fn fpexcodis(&mut self) -> FPEXCODIS_W<'_>[src]

Bit 10 - FPEXCODIS

pub fn disramode(&mut self) -> DISRAMODE_W<'_>[src]

Bit 11 - DISRAMODE

pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W<'_>[src]

Bit 12 - DISITMATBFLUSH

impl W<u32, Reg<u32, _ITCMCR>>[src]

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - EN

pub fn rmw(&mut self) -> RMW_W<'_>[src]

Bit 1 - RMW

pub fn reten(&mut self) -> RETEN_W<'_>[src]

Bit 2 - RETEN

pub fn sz(&mut self) -> SZ_W<'_>[src]

Bits 3:6 - SZ

impl W<u32, Reg<u32, _DTCMCR>>[src]

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - EN

pub fn rmw(&mut self) -> RMW_W<'_>[src]

Bit 1 - RMW

pub fn reten(&mut self) -> RETEN_W<'_>[src]

Bit 2 - RETEN

pub fn sz(&mut self) -> SZ_W<'_>[src]

Bits 3:6 - SZ

impl W<u32, Reg<u32, _AHBPCR>>[src]

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - EN

pub fn sz(&mut self) -> SZ_W<'_>[src]

Bits 1:3 - SZ

impl W<u32, Reg<u32, _CACR>>[src]

pub fn siwt(&mut self) -> SIWT_W<'_>[src]

Bit 0 - SIWT

pub fn eccen(&mut self) -> ECCEN_W<'_>[src]

Bit 1 - ECCEN

pub fn forcewt(&mut self) -> FORCEWT_W<'_>[src]

Bit 2 - FORCEWT

impl W<u32, Reg<u32, _AHBSCR>>[src]

pub fn ctl(&mut self) -> CTL_W<'_>[src]

Bits 0:1 - CTL

pub fn tpri(&mut self) -> TPRI_W<'_>[src]

Bits 2:10 - TPRI

pub fn initcount(&mut self) -> INITCOUNT_W<'_>[src]

Bits 11:15 - INITCOUNT

impl W<u32, Reg<u32, _ABFSR>>[src]

pub fn itcm(&mut self) -> ITCM_W<'_>[src]

Bit 0 - ITCM

pub fn dtcm(&mut self) -> DTCM_W<'_>[src]

Bit 1 - DTCM

pub fn ahbp(&mut self) -> AHBP_W<'_>[src]

Bit 2 - AHBP

pub fn axim(&mut self) -> AXIM_W<'_>[src]

Bit 3 - AXIM

pub fn eppb(&mut self) -> EPPB_W<'_>[src]

Bit 4 - EPPB

pub fn aximtype(&mut self) -> AXIMTYPE_W<'_>[src]

Bits 8:9 - AXIMTYPE

impl W<u32, Reg<u32, _CR>>[src]

pub fn keysize(&mut self) -> KEYSIZE_W<'_>[src]

Bit 18 - Key size selection

pub fn chmod2(&mut self) -> CHMOD2_W<'_>[src]

Bit 16 - AES chaining mode Bit2

pub fn gcmph(&mut self) -> GCMPH_W<'_>[src]

Bits 13:14 - Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected

pub fn dmaouten(&mut self) -> DMAOUTEN_W<'_>[src]

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&mut self) -> DMAINEN_W<'_>[src]

Bit 11 - Enable DMA management of data input phase

pub fn errie(&mut self) -> ERRIE_W<'_>[src]

Bit 10 - Error interrupt enable

pub fn ccfie(&mut self) -> CCFIE_W<'_>[src]

Bit 9 - CCF flag interrupt enable

pub fn errc(&mut self) -> ERRC_W<'_>[src]

Bit 8 - Error clear

pub fn ccfc(&mut self) -> CCFC_W<'_>[src]

Bit 7 - Computation Complete Flag Clear

pub fn chmod10(&mut self) -> CHMOD10_W<'_>[src]

Bits 5:6 - AES chaining mode Bit1 Bit0

pub fn mode(&mut self) -> MODE_W<'_>[src]

Bits 3:4 - AES operating mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>[src]

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - AES enable

impl W<u32, Reg<u32, _DINR>>[src]

pub fn aes_dinr(&mut self) -> AES_DINR_W<'_>[src]

Bits 0:31 - Data Input Register

impl W<u32, Reg<u32, _KEYR0>>[src]

pub fn aes_keyr0(&mut self) -> AES_KEYR0_W<'_>[src]

Bits 0:31 - Data Output Register (LSB key [31:0])

impl W<u32, Reg<u32, _KEYR1>>[src]

pub fn aes_keyr1(&mut self) -> AES_KEYR1_W<'_>[src]

Bits 0:31 - AES key register (key [63:32])

impl W<u32, Reg<u32, _KEYR2>>[src]

pub fn aes_keyr2(&mut self) -> AES_KEYR2_W<'_>[src]

Bits 0:31 - AES key register (key [95:64])

impl W<u32, Reg<u32, _KEYR3>>[src]

pub fn aes_keyr3(&mut self) -> AES_KEYR3_W<'_>[src]

Bits 0:31 - AES key register (MSB key [127:96])

impl W<u32, Reg<u32, _IVR0>>[src]

pub fn aes_ivr0(&mut self) -> AES_IVR0_W<'_>[src]

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl W<u32, Reg<u32, _IVR1>>[src]

pub fn aes_ivr1(&mut self) -> AES_IVR1_W<'_>[src]

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl W<u32, Reg<u32, _IVR2>>[src]

pub fn aes_ivr2(&mut self) -> AES_IVR2_W<'_>[src]

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl W<u32, Reg<u32, _IVR3>>[src]

pub fn aes_ivr3(&mut self) -> AES_IVR3_W<'_>[src]

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl W<u32, Reg<u32, _KEYR4>>[src]

pub fn aes_keyr4(&mut self) -> AES_KEYR4_W<'_>[src]

Bits 0:31 - AES key register (MSB key [159:128])

impl W<u32, Reg<u32, _KEYR5>>[src]

pub fn aes_keyr5(&mut self) -> AES_KEYR5_W<'_>[src]

Bits 0:31 - AES key register (MSB key [191:160])

impl W<u32, Reg<u32, _KEYR6>>[src]

pub fn aes_keyr6(&mut self) -> AES_KEYR6_W<'_>[src]

Bits 0:31 - AES key register (MSB key [223:192])

impl W<u32, Reg<u32, _KEYR7>>[src]

pub fn aes_keyr7(&mut self) -> AES_KEYR7_W<'_>[src]

Bits 0:31 - AES key register (MSB key [255:224])

impl W<u32, Reg<u32, _SUSP0R>>[src]

pub fn aes_susp0r(&mut self) -> AES_SUSP0R_W<'_>[src]

Bits 0:31 - AES suspend register 0

impl W<u32, Reg<u32, _SUSP1R>>[src]

pub fn aes_susp1r(&mut self) -> AES_SUSP1R_W<'_>[src]

Bits 0:31 - AES suspend register 1

impl W<u32, Reg<u32, _SUSP2R>>[src]

pub fn aes_susp2r(&mut self) -> AES_SUSP2R_W<'_>[src]

Bits 0:31 - AES suspend register 2

impl W<u32, Reg<u32, _SUSP3R>>[src]

pub fn aes_susp3r(&mut self) -> AES_SUSP3R_W<'_>[src]

Bits 0:31 - AES suspend register 3

impl W<u32, Reg<u32, _SUSP4R>>[src]

pub fn aes_susp4r(&mut self) -> AES_SUSP4R_W<'_>[src]

Bits 0:31 - AES suspend register 4

impl W<u32, Reg<u32, _SUSP5R>>[src]

pub fn aes_susp5r(&mut self) -> AES_SUSP5R_W<'_>[src]

Bits 0:31 - AES suspend register 5

impl W<u32, Reg<u32, _SUSP6R>>[src]

pub fn aes_susp6r(&mut self) -> AES_SUSP6R_W<'_>[src]

Bits 0:31 - AES suspend register 6

impl W<u32, Reg<u32, _SUSP7R>>[src]

pub fn aes_susp7r(&mut self) -> AES_SUSP7R_W<'_>[src]

Bits 0:31 - AES suspend register 7

impl W<u32, Reg<u32, _PLL1>>[src]

pub fn pll1en(&mut self) -> PLL1EN_W<'_>[src]

Bit 0 - Enable the PLL1 inside PHY

pub fn pll1sel(&mut self) -> PLL1SEL_W<'_>[src]

Bits 1:3 - : Controls the PHY PLL1 input clock frequency selection

impl W<u32, Reg<u32, _TUNE>>[src]

pub fn incurren(&mut self) -> INCURREN_W<'_>[src]

Bit 0 - Controls the current boosting function

pub fn incurrint(&mut self) -> INCURRINT_W<'_>[src]

Bit 1 - Controls PHY current boosting

pub fn lfscapen(&mut self) -> LFSCAPEN_W<'_>[src]

Bit 2 - : Enables the Low Full Speed feedback capacitor

pub fn hsdrvslew(&mut self) -> HSDRVSLEW_W<'_>[src]

Bit 3 - Controls the HS driver slew rate

pub fn hsdrvdccur(&mut self) -> HSDRVDCCUR_W<'_>[src]

Bit 4 - Decreases the HS driver DC level

pub fn hsdrvdclev(&mut self) -> HSDRVDCLEV_W<'_>[src]

Bit 5 - Increases the HS Driver DC level. Not applicable during the HS Test J and Test K data transfer

pub fn hsdrvcurincr(&mut self) -> HSDRVCURINCR_W<'_>[src]

Bit 6 - Enable the HS driver current increase feature

pub fn fsdrvrfadj(&mut self) -> FSDRVRFADJ_W<'_>[src]

Bit 7 - Tuning pin to adjust the full speed rise/fall time

pub fn hsdrvrfred(&mut self) -> HSDRVRFRED_W<'_>[src]

Bit 8 - High Speed rise-fall reduction enable

pub fn hsdrvchkitrm(&mut self) -> HSDRVCHKITRM_W<'_>[src]

Bits 9:12 - HS Driver current trimming pins for choke compensation

pub fn hsdrvchkztrm(&mut self) -> HSDRVCHKZTRM_W<'_>[src]

Bits 13:14 - Controls the PHY bus HS driver impedance tuning for choke compensation

pub fn sqlchctl(&mut self) -> SQLCHCTL_W<'_>[src]

Bits 15:16 - Adjust the squelch DC threshold value

pub fn hdrxgneqen(&mut self) -> HDRXGNEQEN_W<'_>[src]

Bit 17 - Enables the HS Rx Gain Equalizer

pub fn stagsel(&mut self) -> STAGSEL_W<'_>[src]

Bit 18 - HS Tx staggering enable

pub fn hsfallpreem(&mut self) -> HSFALLPREEM_W<'_>[src]

Bit 19 - HS Fall time control of single ended signals during pre-emphasis

pub fn hsrxoff(&mut self) -> HSRXOFF_W<'_>[src]

Bits 20:21 - : HS Receiver Offset adjustment

pub fn shtcctctlprot(&mut self) -> SHTCCTCTLPROT_W<'_>[src]

Bit 22 - Enables the short circuit protection circuitry in LS/FS driver

pub fn sqlbyp(&mut self) -> SQLBYP_W<'_>[src]

Bit 23 - This pin is used to bypass the squelch inter-locking circuitry

impl W<u32, Reg<u32, _LDO>>[src]

pub fn ldo_disable(&mut self) -> LDO_DISABLE_W<'_>[src]

Bit 2 - Controls disable of the High Speed PHY's LDO

impl W<u32, Reg<u32, _CR>>[src]

pub fn ie(&mut self) -> IE_W<'_>[src]

Bit 3 - Interrupt enable

pub fn rngen(&mut self) -> RNGEN_W<'_>[src]

Bit 2 - Random number generator enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn seis(&mut self) -> SEIS_W<'_>[src]

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>[src]

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _CR>>[src]

pub fn init(&mut self) -> INIT_W<'_>[src]

Bit 2 - Initialize message digest calculation

pub fn dmae(&mut self) -> DMAE_W<'_>[src]

Bit 3 - DMA enable

pub fn datatype(&mut self) -> DATATYPE_W<'_>[src]

Bits 4:5 - Data type selection

pub fn mode(&mut self) -> MODE_W<'_>[src]

Bit 6 - Mode selection

pub fn algo0(&mut self) -> ALGO0_W<'_>[src]

Bit 7 - Algorithm selection

pub fn mdmat(&mut self) -> MDMAT_W<'_>[src]

Bit 13 - Multiple DMA Transfers

pub fn lkey(&mut self) -> LKEY_W<'_>[src]

Bit 16 - Long key selection

pub fn algo1(&mut self) -> ALGO1_W<'_>[src]

Bit 18 - ALGO

impl W<u32, Reg<u32, _DIN>>[src]

pub fn datain(&mut self) -> DATAIN_W<'_>[src]

Bits 0:31 - Data input

impl W<u32, Reg<u32, _STR>>[src]

pub fn dcal(&mut self) -> DCAL_W<'_>[src]

Bit 8 - Digest calculation

pub fn nblw(&mut self) -> NBLW_W<'_>[src]

Bits 0:4 - Number of valid bits in the last word of the message

impl W<u32, Reg<u32, _IMR>>[src]

pub fn dcie(&mut self) -> DCIE_W<'_>[src]

Bit 1 - Digest calculation completion interrupt enable

pub fn dinie(&mut self) -> DINIE_W<'_>[src]

Bit 0 - Data input interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn dcis(&mut self) -> DCIS_W<'_>[src]

Bit 1 - Digest calculation completion interrupt status

pub fn dinis(&mut self) -> DINIS_W<'_>[src]

Bit 0 - Data input interrupt status

impl W<u32, Reg<u32, _CSR>>[src]

pub fn csr(&mut self) -> CSR_W<'_>[src]

Bits 0:31 - CSR0

impl W<u32, Reg<u32, _KLR>>[src]

pub fn b2(&mut self) -> B2_W<'_>[src]

Bits 0:31 - b224

impl W<u32, Reg<u32, _KRR>>[src]

pub fn b(&mut self) -> B_W<'_>[src]

Bits 0:31 - b192

impl W<u32, Reg<u32, _IVLR>>[src]

pub fn iv(&mut self) -> IV_W<'_>[src]

Bits 0:31 - IV31

impl W<u32, Reg<u32, _IVRR>>[src]

pub fn iv(&mut self) -> IV_W<'_>[src]

Bits 0:31 - IV63

impl W<u32, Reg<u32, _CR>>[src]

pub fn algodir(&mut self) -> ALGODIR_W<'_>[src]

Bit 2 - Algorithm direction

pub fn algomode0(&mut self) -> ALGOMODE0_W<'_>[src]

Bits 3:5 - Algorithm mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>[src]

Bits 6:7 - Data type selection

pub fn keysize(&mut self) -> KEYSIZE_W<'_>[src]

Bits 8:9 - Key size selection (AES mode only)

pub fn fflush(&mut self) -> FFLUSH_W<'_>[src]

Bit 14 - FIFO flush

pub fn crypen(&mut self) -> CRYPEN_W<'_>[src]

Bit 15 - Cryptographic processor enable

pub fn gcm_ccmph(&mut self) -> GCM_CCMPH_W<'_>[src]

Bits 16:17 - GCM_CCMPH

pub fn algomode3(&mut self) -> ALGOMODE3_W<'_>[src]

Bit 19 - ALGOMODE

impl W<u32, Reg<u32, _DIN>>[src]

pub fn datain(&mut self) -> DATAIN_W<'_>[src]

Bits 0:31 - Data input

impl W<u32, Reg<u32, _DMACR>>[src]

pub fn doen(&mut self) -> DOEN_W<'_>[src]

Bit 1 - DMA output enable

pub fn dien(&mut self) -> DIEN_W<'_>[src]

Bit 0 - DMA input enable

impl W<u32, Reg<u32, _IMSCR>>[src]

pub fn outim(&mut self) -> OUTIM_W<'_>[src]

Bit 1 - Output FIFO service interrupt mask

pub fn inim(&mut self) -> INIM_W<'_>[src]

Bit 0 - Input FIFO service interrupt mask

impl W<u32, Reg<u32, _CSGCMCCMR>>[src]

pub fn csgcmccm0r(&mut self) -> CSGCMCCM0R_W<'_>[src]

Bits 0:31 - CSGCMCCM0R

impl W<u32, Reg<u32, _CSGCMR>>[src]

pub fn csgcmr(&mut self) -> CSGCMR_W<'_>[src]

Bits 0:31 - CSGCM0R

impl W<u32, Reg<u32, _CR>>[src]

pub fn enable(&mut self) -> ENABLE_W<'_>[src]

Bit 14 - DCMI enable

pub fn edm(&mut self) -> EDM_W<'_>[src]

Bits 10:11 - Extended data mode

pub fn fcrc(&mut self) -> FCRC_W<'_>[src]

Bits 8:9 - Frame capture rate control

pub fn vspol(&mut self) -> VSPOL_W<'_>[src]

Bit 7 - Vertical synchronization polarity

pub fn hspol(&mut self) -> HSPOL_W<'_>[src]

Bit 6 - Horizontal synchronization polarity

pub fn pckpol(&mut self) -> PCKPOL_W<'_>[src]

Bit 5 - Pixel clock polarity

pub fn ess(&mut self) -> ESS_W<'_>[src]

Bit 4 - Embedded synchronization select

pub fn jpeg(&mut self) -> JPEG_W<'_>[src]

Bit 3 - JPEG format

pub fn crop(&mut self) -> CROP_W<'_>[src]

Bit 2 - Crop feature

pub fn cm(&mut self) -> CM_W<'_>[src]

Bit 1 - Capture mode

pub fn capture(&mut self) -> CAPTURE_W<'_>[src]

Bit 0 - Capture enable

impl W<u32, Reg<u32, _IER>>[src]

pub fn line_ie(&mut self) -> LINE_IE_W<'_>[src]

Bit 4 - Line interrupt enable

pub fn vsync_ie(&mut self) -> VSYNC_IE_W<'_>[src]

Bit 3 - VSYNC interrupt enable

pub fn err_ie(&mut self) -> ERR_IE_W<'_>[src]

Bit 2 - Synchronization error interrupt enable

pub fn ovr_ie(&mut self) -> OVR_IE_W<'_>[src]

Bit 1 - Overrun interrupt enable

pub fn frame_ie(&mut self) -> FRAME_IE_W<'_>[src]

Bit 0 - Capture complete interrupt enable

impl W<u32, Reg<u32, _ICR>>[src]

pub fn line_isc(&mut self) -> LINE_ISC_W<'_>[src]

Bit 4 - line interrupt status clear

pub fn vsync_isc(&mut self) -> VSYNC_ISC_W<'_>[src]

Bit 3 - Vertical synch interrupt status clear

pub fn err_isc(&mut self) -> ERR_ISC_W<'_>[src]

Bit 2 - Synchronization error interrupt status clear

pub fn ovr_isc(&mut self) -> OVR_ISC_W<'_>[src]

Bit 1 - Overrun interrupt status clear

pub fn frame_isc(&mut self) -> FRAME_ISC_W<'_>[src]

Bit 0 - Capture complete interrupt status clear

impl W<u32, Reg<u32, _ESCR>>[src]

pub fn fec(&mut self) -> FEC_W<'_>[src]

Bits 24:31 - Frame end delimiter code

pub fn lec(&mut self) -> LEC_W<'_>[src]

Bits 16:23 - Line end delimiter code

pub fn lsc(&mut self) -> LSC_W<'_>[src]

Bits 8:15 - Line start delimiter code

pub fn fsc(&mut self) -> FSC_W<'_>[src]

Bits 0:7 - Frame start delimiter code

impl W<u32, Reg<u32, _ESUR>>[src]

pub fn feu(&mut self) -> FEU_W<'_>[src]

Bits 24:31 - Frame end delimiter unmask

pub fn leu(&mut self) -> LEU_W<'_>[src]

Bits 16:23 - Line end delimiter unmask

pub fn lsu(&mut self) -> LSU_W<'_>[src]

Bits 8:15 - Line start delimiter unmask

pub fn fsu(&mut self) -> FSU_W<'_>[src]

Bits 0:7 - Frame start delimiter unmask

impl W<u32, Reg<u32, _CWSTRT>>[src]

pub fn vst(&mut self) -> VST_W<'_>[src]

Bits 16:28 - Vertical start line count

pub fn hoffcnt(&mut self) -> HOFFCNT_W<'_>[src]

Bits 0:13 - Horizontal offset count

impl W<u32, Reg<u32, _CWSIZE>>[src]

pub fn vline(&mut self) -> VLINE_W<'_>[src]

Bits 16:29 - Vertical line count

pub fn capcnt(&mut self) -> CAPCNT_W<'_>[src]

Bits 0:13 - Capture count

impl W<u32, Reg<u32, _BCR1>>[src]

pub fn cclken(&mut self) -> CCLKEN_W<'_>[src]

Bit 20 - CCLKEN

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>[src]

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>[src]

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>[src]

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>[src]

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>[src]

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>[src]

Bit 11 - WAITCFG

pub fn waitpol(&mut self) -> WAITPOL_W<'_>[src]

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>[src]

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>[src]

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>[src]

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>[src]

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>[src]

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>[src]

Bit 0 - MBKEN

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>[src]

Bit 10 - WRAPMOD

pub fn wfdis(&mut self) -> WFDIS_W<'_>[src]

Bit 21 - Write FIFO disable

pub fn cpsize(&mut self) -> CPSIZE_W<'_>[src]

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BTR>>[src]

pub fn accmod(&mut self) -> ACCMOD_W<'_>[src]

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>[src]

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>[src]

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>[src]

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>[src]

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>[src]

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>[src]

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR>>[src]

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>[src]

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>[src]

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>[src]

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>[src]

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>[src]

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>[src]

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>[src]

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>[src]

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>[src]

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>[src]

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>[src]

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>[src]

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>[src]

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>[src]

Bit 0 - MBKEN

pub fn cpsize(&mut self) -> CPSIZE_W<'_>[src]

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _PCR>>[src]

pub fn eccps(&mut self) -> ECCPS_W<'_>[src]

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>[src]

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>[src]

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>[src]

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>[src]

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>[src]

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>[src]

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>[src]

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR>>[src]

pub fn ifen(&mut self) -> IFEN_W<'_>[src]

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>[src]

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>[src]

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>[src]

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>[src]

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>[src]

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM>>[src]

pub fn memhiz(&mut self) -> MEMHIZ_W<'_>[src]

Bits 24:31 - MEMHIZx

pub fn memhold(&mut self) -> MEMHOLD_W<'_>[src]

Bits 16:23 - MEMHOLDx

pub fn memwait(&mut self) -> MEMWAIT_W<'_>[src]

Bits 8:15 - MEMWAITx

pub fn memset(&mut self) -> MEMSET_W<'_>[src]

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT>>[src]

pub fn atthiz(&mut self) -> ATTHIZ_W<'_>[src]

Bits 24:31 - ATTHIZx

pub fn atthold(&mut self) -> ATTHOLD_W<'_>[src]

Bits 16:23 - ATTHOLDx

pub fn attwait(&mut self) -> ATTWAIT_W<'_>[src]

Bits 8:15 - ATTWAITx

pub fn attset(&mut self) -> ATTSET_W<'_>[src]

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _BWTR>>[src]

pub fn accmod(&mut self) -> ACCMOD_W<'_>[src]

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>[src]

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>[src]

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>[src]

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>[src]

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>[src]

Bits 0:3 - ADDSET

pub fn busturn(&mut self) -> BUSTURN_W<'_>[src]

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _SDCR>>[src]

pub fn nc(&mut self) -> NC_W<'_>[src]

Bits 0:1 - Number of column address bits

pub fn nr(&mut self) -> NR_W<'_>[src]

Bits 2:3 - Number of row address bits

pub fn mwid(&mut self) -> MWID_W<'_>[src]

Bits 4:5 - Memory data bus width

pub fn nb(&mut self) -> NB_W<'_>[src]

Bit 6 - Number of internal banks

pub fn cas(&mut self) -> CAS_W<'_>[src]

Bits 7:8 - CAS latency

pub fn wp(&mut self) -> WP_W<'_>[src]

Bit 9 - Write protection

pub fn sdclk(&mut self) -> SDCLK_W<'_>[src]

Bits 10:11 - SDRAM clock configuration

pub fn rburst(&mut self) -> RBURST_W<'_>[src]

Bit 12 - Burst read

pub fn rpipe(&mut self) -> RPIPE_W<'_>[src]

Bits 13:14 - Read pipe

impl W<u32, Reg<u32, _SDTR>>[src]

pub fn tmrd(&mut self) -> TMRD_W<'_>[src]

Bits 0:3 - Load Mode Register to Active

pub fn txsr(&mut self) -> TXSR_W<'_>[src]

Bits 4:7 - Exit self-refresh delay

pub fn tras(&mut self) -> TRAS_W<'_>[src]

Bits 8:11 - Self refresh time

pub fn trc(&mut self) -> TRC_W<'_>[src]

Bits 12:15 - Row cycle delay

pub fn twr(&mut self) -> TWR_W<'_>[src]

Bits 16:19 - Recovery delay

pub fn trp(&mut self) -> TRP_W<'_>[src]

Bits 20:23 - Row precharge delay

pub fn trcd(&mut self) -> TRCD_W<'_>[src]

Bits 24:27 - Row to column delay

impl W<u32, Reg<u32, _SDCMR>>[src]

pub fn mode(&mut self) -> MODE_W<'_>[src]

Bits 0:2 - Command mode

pub fn ctb2(&mut self) -> CTB2_W<'_>[src]

Bit 3 - Command target bank 2

pub fn ctb1(&mut self) -> CTB1_W<'_>[src]

Bit 4 - Command target bank 1

pub fn nrfs(&mut self) -> NRFS_W<'_>[src]

Bits 5:8 - Number of Auto-refresh

pub fn mrd(&mut self) -> MRD_W<'_>[src]

Bits 9:21 - Mode Register definition

impl W<u32, Reg<u32, _SDRTR>>[src]

pub fn cre(&mut self) -> CRE_W<'_>[src]

Bit 0 - Clear Refresh error flag

pub fn count(&mut self) -> COUNT_W<'_>[src]

Bits 1:13 - Refresh Timer Count

pub fn reie(&mut self) -> REIE_W<'_>[src]

Bit 14 - RES Interrupt Enable

impl W<u32, Reg<u32, _CR>>[src]

pub fn chsel(&mut self) -> CHSEL_W<'_>[src]

Bits 25:28 - Channel selection

pub fn mburst(&mut self) -> MBURST_W<'_>[src]

Bits 23:24 - Memory burst transfer configuration

pub fn pburst(&mut self) -> PBURST_W<'_>[src]

Bits 21:22 - Peripheral burst transfer configuration

pub fn ct(&mut self) -> CT_W<'_>[src]

Bit 19 - Current target (only in double buffer mode)

pub fn dbm(&mut self) -> DBM_W<'_>[src]

Bit 18 - Double buffer mode

pub fn pl(&mut self) -> PL_W<'_>[src]

Bits 16:17 - Priority level

pub fn pincos(&mut self) -> PINCOS_W<'_>[src]

Bit 15 - Peripheral increment offset size

pub fn msize(&mut self) -> MSIZE_W<'_>[src]

Bits 13:14 - Memory data size

pub fn psize(&mut self) -> PSIZE_W<'_>[src]

Bits 11:12 - Peripheral data size

pub fn minc(&mut self) -> MINC_W<'_>[src]

Bit 10 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>[src]

Bit 9 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>[src]

Bit 8 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bits 6:7 - Data transfer direction

pub fn pfctrl(&mut self) -> PFCTRL_W<'_>[src]

Bit 5 - Peripheral flow controller

pub fn tcie(&mut self) -> TCIE_W<'_>[src]

Bit 4 - Transfer complete interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>[src]

Bit 3 - Half transfer interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>[src]

Bit 2 - Transfer error interrupt enable

pub fn dmeie(&mut self) -> DMEIE_W<'_>[src]

Bit 1 - Direct mode error interrupt enable

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - Stream enable / flag stream ready when read low

impl W<u32, Reg<u32, _NDTR>>[src]

pub fn ndt(&mut self) -> NDT_W<'_>[src]

Bits 0:15 - Number of data items to transfer

impl W<u32, Reg<u32, _PAR>>[src]

pub fn pa(&mut self) -> PA_W<'_>[src]

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _M0AR>>[src]

pub fn m0a(&mut self) -> M0A_W<'_>[src]

Bits 0:31 - Memory 0 address

impl W<u32, Reg<u32, _M1AR>>[src]

pub fn m1a(&mut self) -> M1A_W<'_>[src]

Bits 0:31 - Memory 1 address (used in case of Double buffer mode)

impl W<u32, Reg<u32, _FCR>>[src]

pub fn feie(&mut self) -> FEIE_W<'_>[src]

Bit 7 - FIFO error interrupt enable

pub fn dmdis(&mut self) -> DMDIS_W<'_>[src]

Bit 2 - Direct mode disable

pub fn fth(&mut self) -> FTH_W<'_>[src]

Bits 0:1 - FIFO threshold selection

impl W<u32, Reg<u32, _LIFCR>>[src]

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>[src]

Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>[src]

Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>[src]

Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif3(&mut self) -> CDMEIF3_W<'_>[src]

Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif3(&mut self) -> CFEIF3_W<'_>[src]

Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>[src]

Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>[src]

Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>[src]

Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif2(&mut self) -> CDMEIF2_W<'_>[src]

Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif2(&mut self) -> CFEIF2_W<'_>[src]

Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>[src]

Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>[src]

Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>[src]

Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif1(&mut self) -> CDMEIF1_W<'_>[src]

Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif1(&mut self) -> CFEIF1_W<'_>[src]

Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)

pub fn ctcif0(&mut self) -> CTCIF0_W<'_>[src]

Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)

pub fn chtif0(&mut self) -> CHTIF0_W<'_>[src]

Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)

pub fn cteif0(&mut self) -> CTEIF0_W<'_>[src]

Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)

pub fn cdmeif0(&mut self) -> CDMEIF0_W<'_>[src]

Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)

pub fn cfeif0(&mut self) -> CFEIF0_W<'_>[src]

Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)

impl W<u32, Reg<u32, _HIFCR>>[src]

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>[src]

Bit 27 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>[src]

Bit 26 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif7(&mut self) -> CTEIF7_W<'_>[src]

Bit 25 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif7(&mut self) -> CDMEIF7_W<'_>[src]

Bit 24 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif7(&mut self) -> CFEIF7_W<'_>[src]

Bit 22 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>[src]

Bit 21 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>[src]

Bit 20 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>[src]

Bit 19 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif6(&mut self) -> CDMEIF6_W<'_>[src]

Bit 18 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif6(&mut self) -> CFEIF6_W<'_>[src]

Bit 16 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>[src]

Bit 11 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>[src]

Bit 10 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>[src]

Bit 9 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif5(&mut self) -> CDMEIF5_W<'_>[src]

Bit 8 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif5(&mut self) -> CFEIF5_W<'_>[src]

Bit 6 - Stream x clear FIFO error interrupt flag (x = 7..4)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>[src]

Bit 5 - Stream x clear transfer complete interrupt flag (x = 7..4)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>[src]

Bit 4 - Stream x clear half transfer interrupt flag (x = 7..4)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>[src]

Bit 3 - Stream x clear transfer error interrupt flag (x = 7..4)

pub fn cdmeif4(&mut self) -> CDMEIF4_W<'_>[src]

Bit 2 - Stream x clear direct mode error interrupt flag (x = 7..4)

pub fn cfeif4(&mut self) -> CFEIF4_W<'_>[src]

Bit 0 - Stream x clear FIFO error interrupt flag (x = 7..4)

impl W<u32, Reg<u32, _CR>>[src]

pub fn plli2son(&mut self) -> PLLI2SON_W<'_>[src]

Bit 26 - PLLI2S enable

pub fn pllon(&mut self) -> PLLON_W<'_>[src]

Bit 24 - Main PLL (PLL) enable

pub fn csson(&mut self) -> CSSON_W<'_>[src]

Bit 19 - Clock security system enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>[src]

Bit 18 - HSE clock bypass

pub fn hseon(&mut self) -> HSEON_W<'_>[src]

Bit 16 - HSE clock enable

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>[src]

Bits 3:7 - Internal high-speed clock trimming

pub fn hsion(&mut self) -> HSION_W<'_>[src]

Bit 0 - Internal high-speed clock enable

pub fn pllsaion(&mut self) -> PLLSAION_W<'_>[src]

Bit 28 - PLLSAI enable

impl W<u32, Reg<u32, _PLLCFGR>>[src]

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>[src]

Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source

pub fn pllr(&mut self) -> PLLR_W<'_>[src]

Bits 28:30 - PLL division factor for DSI clock

pub fn pllm(&mut self) -> PLLM_W<'_>[src]

Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock

pub fn plln(&mut self) -> PLLN_W<'_>[src]

Bits 6:14 - Main PLL (PLL) multiplication factor for VCO

pub fn pllp(&mut self) -> PLLP_W<'_>[src]

Bits 16:17 - Main PLL (PLL) division factor for main system clock

pub fn pllq(&mut self) -> PLLQ_W<'_>[src]

Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks

impl W<u32, Reg<u32, _CFGR>>[src]

pub fn mco2(&mut self) -> MCO2_W<'_>[src]

Bits 30:31 - Microcontroller clock output 2

pub fn mco2pre(&mut self) -> MCO2PRE_W<'_>[src]

Bits 27:29 - MCO2 prescaler

pub fn mco1pre(&mut self) -> MCO1PRE_W<'_>[src]

Bits 24:26 - MCO1 prescaler

pub fn i2ssrc(&mut self) -> I2SSRC_W<'_>[src]

Bit 23 - I2S clock selection

pub fn mco1(&mut self) -> MCO1_W<'_>[src]

Bits 21:22 - Microcontroller clock output 1

pub fn rtcpre(&mut self) -> RTCPRE_W<'_>[src]

Bits 16:20 - HSE division factor for RTC clock

pub fn ppre2(&mut self) -> PPRE2_W<'_>[src]

Bits 13:15 - APB high-speed prescaler (APB2)

pub fn ppre1(&mut self) -> PPRE1_W<'_>[src]

Bits 10:12 - APB Low speed prescaler (APB1)

pub fn hpre(&mut self) -> HPRE_W<'_>[src]

Bits 4:7 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>[src]

Bits 0:1 - System clock switch

pub fn sws(&mut self) -> SWS_W<'_>[src]

Bits 2:3 - System clock switch status

impl W<u32, Reg<u32, _CIR>>[src]

pub fn cssc(&mut self) -> CSSC_W<'_>[src]

Bit 23 - Clock security system interrupt clear

pub fn pllsairdyc(&mut self) -> PLLSAIRDYC_W<'_>[src]

Bit 22 - PLLSAI Ready Interrupt Clear

pub fn plli2srdyc(&mut self) -> PLLI2SRDYC_W<'_>[src]

Bit 21 - PLLI2S ready interrupt clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>[src]

Bit 20 - Main PLL(PLL) ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>[src]

Bit 19 - HSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>[src]

Bit 18 - HSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>[src]

Bit 17 - LSE ready interrupt clear

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>[src]

Bit 16 - LSI ready interrupt clear

pub fn pllsairdyie(&mut self) -> PLLSAIRDYIE_W<'_>[src]

Bit 14 - PLLSAI Ready Interrupt Enable

pub fn plli2srdyie(&mut self) -> PLLI2SRDYIE_W<'_>[src]

Bit 13 - PLLI2S ready interrupt enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>[src]

Bit 12 - Main PLL (PLL) ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>[src]

Bit 11 - HSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>[src]

Bit 10 - HSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>[src]

Bit 9 - LSE ready interrupt enable

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>[src]

Bit 8 - LSI ready interrupt enable

impl W<u32, Reg<u32, _AHB1RSTR>>[src]

pub fn otghsrst(&mut self) -> OTGHSRST_W<'_>[src]

Bit 29 - USB OTG HS module reset

pub fn ethmacrst(&mut self) -> ETHMACRST_W<'_>[src]

Bit 25 - Ethernet MAC reset

pub fn dma2drst(&mut self) -> DMA2DRST_W<'_>[src]

Bit 23 - DMA2D reset

pub fn dma2rst(&mut self) -> DMA2RST_W<'_>[src]

Bit 22 - DMA2 reset

pub fn dma1rst(&mut self) -> DMA1RST_W<'_>[src]

Bit 21 - DMA2 reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>[src]

Bit 12 - CRC reset

pub fn gpiokrst(&mut self) -> GPIOKRST_W<'_>[src]

Bit 10 - IO port K reset

pub fn gpiojrst(&mut self) -> GPIOJRST_W<'_>[src]

Bit 9 - IO port J reset

pub fn gpioirst(&mut self) -> GPIOIRST_W<'_>[src]

Bit 8 - IO port I reset

pub fn gpiohrst(&mut self) -> GPIOHRST_W<'_>[src]

Bit 7 - IO port H reset

pub fn gpiogrst(&mut self) -> GPIOGRST_W<'_>[src]

Bit 6 - IO port G reset

pub fn gpiofrst(&mut self) -> GPIOFRST_W<'_>[src]

Bit 5 - IO port F reset

pub fn gpioerst(&mut self) -> GPIOERST_W<'_>[src]

Bit 4 - IO port E reset

pub fn gpiodrst(&mut self) -> GPIODRST_W<'_>[src]

Bit 3 - IO port D reset

pub fn gpiocrst(&mut self) -> GPIOCRST_W<'_>[src]

Bit 2 - IO port C reset

pub fn gpiobrst(&mut self) -> GPIOBRST_W<'_>[src]

Bit 1 - IO port B reset

pub fn gpioarst(&mut self) -> GPIOARST_W<'_>[src]

Bit 0 - IO port A reset

impl W<u32, Reg<u32, _AHB2RSTR>>[src]

pub fn otgfsrst(&mut self) -> OTGFSRST_W<'_>[src]

Bit 7 - USB OTG FS module reset

pub fn rngrst(&mut self) -> RNGRST_W<'_>[src]

Bit 6 - Random number generator module reset

pub fn hsahrst(&mut self) -> HSAHRST_W<'_>[src]

Bit 5 - Hash module reset

pub fn cryprst(&mut self) -> CRYPRST_W<'_>[src]

Bit 4 - Cryptographic module reset

pub fn dcmirst(&mut self) -> DCMIRST_W<'_>[src]

Bit 0 - Camera interface reset

impl W<u32, Reg<u32, _AHB3RSTR>>[src]

pub fn fmcrst(&mut self) -> FMCRST_W<'_>[src]

Bit 0 - Flexible memory controller module reset

pub fn qspirst(&mut self) -> QSPIRST_W<'_>[src]

Bit 1 - Quad SPI memory controller reset

impl W<u32, Reg<u32, _APB1RSTR>>[src]

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>[src]

Bit 0 - TIM2 reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>[src]

Bit 1 - TIM3 reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>[src]

Bit 2 - TIM4 reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>[src]

Bit 3 - TIM5 reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>[src]

Bit 4 - TIM6 reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>[src]

Bit 5 - TIM7 reset

pub fn tim12rst(&mut self) -> TIM12RST_W<'_>[src]

Bit 6 - TIM12 reset

pub fn tim13rst(&mut self) -> TIM13RST_W<'_>[src]

Bit 7 - TIM13 reset

pub fn tim14rst(&mut self) -> TIM14RST_W<'_>[src]

Bit 8 - TIM14 reset

pub fn wwdgrst(&mut self) -> WWDGRST_W<'_>[src]

Bit 11 - Window watchdog reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>[src]

Bit 14 - SPI 2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>[src]

Bit 15 - SPI 3 reset

pub fn uart2rst(&mut self) -> UART2RST_W<'_>[src]

Bit 17 - USART 2 reset

pub fn uart3rst(&mut self) -> UART3RST_W<'_>[src]

Bit 18 - USART 3 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>[src]

Bit 19 - USART 4 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>[src]

Bit 20 - USART 5 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>[src]

Bit 21 - I2C 1 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>[src]

Bit 22 - I2C 2 reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>[src]

Bit 23 - I2C3 reset

pub fn can1rst(&mut self) -> CAN1RST_W<'_>[src]

Bit 25 - CAN1 reset

pub fn can2rst(&mut self) -> CAN2RST_W<'_>[src]

Bit 26 - CAN2 reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>[src]

Bit 28 - Power interface reset

pub fn dacrst(&mut self) -> DACRST_W<'_>[src]

Bit 29 - DAC reset

pub fn uart7rst(&mut self) -> UART7RST_W<'_>[src]

Bit 30 - UART7 reset

pub fn uart8rst(&mut self) -> UART8RST_W<'_>[src]

Bit 31 - UART8 reset

pub fn spdifrxrst(&mut self) -> SPDIFRXRST_W<'_>[src]

Bit 16 - SPDIF-RX reset

pub fn cecrst(&mut self) -> CECRST_W<'_>[src]

Bit 27 - HDMI-CEC reset

pub fn lptim1rst(&mut self) -> LPTIM1RST_W<'_>[src]

Bit 9 - Low power timer 1 reset

pub fn i2c4rst(&mut self) -> I2C4RST_W<'_>[src]

Bit 24 - I2C 4 reset

impl W<u32, Reg<u32, _APB2RSTR>>[src]

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>[src]

Bit 0 - TIM1 reset

pub fn tim8rst(&mut self) -> TIM8RST_W<'_>[src]

Bit 1 - TIM8 reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>[src]

Bit 4 - USART1 reset

pub fn usart6rst(&mut self) -> USART6RST_W<'_>[src]

Bit 5 - USART6 reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>[src]

Bit 8 - ADC interface reset (common to all ADCs)

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>[src]

Bit 12 - SPI 1 reset

pub fn spi4rst(&mut self) -> SPI4RST_W<'_>[src]

Bit 13 - SPI4 reset

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>[src]

Bit 14 - System configuration controller reset

pub fn tim9rst(&mut self) -> TIM9RST_W<'_>[src]

Bit 16 - TIM9 reset

pub fn tim10rst(&mut self) -> TIM10RST_W<'_>[src]

Bit 17 - TIM10 reset

pub fn tim11rst(&mut self) -> TIM11RST_W<'_>[src]

Bit 18 - TIM11 reset

pub fn spi5rst(&mut self) -> SPI5RST_W<'_>[src]

Bit 20 - SPI5 reset

pub fn spi6rst(&mut self) -> SPI6RST_W<'_>[src]

Bit 21 - SPI6 reset

pub fn sai1rst(&mut self) -> SAI1RST_W<'_>[src]

Bit 22 - SAI1 reset

pub fn ltdcrst(&mut self) -> LTDCRST_W<'_>[src]

Bit 26 - LTDC reset

pub fn sai2rst(&mut self) -> SAI2RST_W<'_>[src]

Bit 23 - SAI2 reset

pub fn sdmmc1rst(&mut self) -> SDMMC1RST_W<'_>[src]

Bit 11 - SDMMC1 reset

impl W<u32, Reg<u32, _AHB1ENR>>[src]

pub fn otghsulpien(&mut self) -> OTGHSULPIEN_W<'_>[src]

Bit 30 - USB OTG HSULPI clock enable

pub fn otghsen(&mut self) -> OTGHSEN_W<'_>[src]

Bit 29 - USB OTG HS clock enable

pub fn ethmacptpen(&mut self) -> ETHMACPTPEN_W<'_>[src]

Bit 28 - Ethernet PTP clock enable

pub fn ethmacrxen(&mut self) -> ETHMACRXEN_W<'_>[src]

Bit 27 - Ethernet Reception clock enable

pub fn ethmactxen(&mut self) -> ETHMACTXEN_W<'_>[src]

Bit 26 - Ethernet Transmission clock enable

pub fn ethmacen(&mut self) -> ETHMACEN_W<'_>[src]

Bit 25 - Ethernet MAC clock enable

pub fn dma2den(&mut self) -> DMA2DEN_W<'_>[src]

Bit 23 - DMA2D clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>[src]

Bit 22 - DMA2 clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>[src]

Bit 21 - DMA1 clock enable

pub fn ccmdataramen(&mut self) -> CCMDATARAMEN_W<'_>[src]

Bit 20 - CCM data RAM clock enable

pub fn bkpsramen(&mut self) -> BKPSRAMEN_W<'_>[src]

Bit 18 - Backup SRAM interface clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>[src]

Bit 12 - CRC clock enable

pub fn gpioken(&mut self) -> GPIOKEN_W<'_>[src]

Bit 10 - IO port K clock enable

pub fn gpiojen(&mut self) -> GPIOJEN_W<'_>[src]

Bit 9 - IO port J clock enable

pub fn gpioien(&mut self) -> GPIOIEN_W<'_>[src]

Bit 8 - IO port I clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>[src]

Bit 7 - IO port H clock enable

pub fn gpiogen(&mut self) -> GPIOGEN_W<'_>[src]

Bit 6 - IO port G clock enable

pub fn gpiofen(&mut self) -> GPIOFEN_W<'_>[src]

Bit 5 - IO port F clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>[src]

Bit 4 - IO port E clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>[src]

Bit 3 - IO port D clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>[src]

Bit 2 - IO port C clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>[src]

Bit 1 - IO port B clock enable

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>[src]

Bit 0 - IO port A clock enable

impl W<u32, Reg<u32, _AHB2ENR>>[src]

pub fn otgfsen(&mut self) -> OTGFSEN_W<'_>[src]

Bit 7 - USB OTG FS clock enable

pub fn rngen(&mut self) -> RNGEN_W<'_>[src]

Bit 6 - Random number generator clock enable

pub fn hashen(&mut self) -> HASHEN_W<'_>[src]

Bit 5 - Hash modules clock enable

pub fn crypen(&mut self) -> CRYPEN_W<'_>[src]

Bit 4 - Cryptographic modules clock enable

pub fn dcmien(&mut self) -> DCMIEN_W<'_>[src]

Bit 0 - Camera interface enable

impl W<u32, Reg<u32, _AHB3ENR>>[src]

pub fn fmcen(&mut self) -> FMCEN_W<'_>[src]

Bit 0 - Flexible memory controller module clock enable

pub fn qspien(&mut self) -> QSPIEN_W<'_>[src]

Bit 1 - Quad SPI memory controller clock enable

impl W<u32, Reg<u32, _APB1ENR>>[src]

pub fn tim2en(&mut self) -> TIM2EN_W<'_>[src]

Bit 0 - TIM2 clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>[src]

Bit 1 - TIM3 clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>[src]

Bit 2 - TIM4 clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>[src]

Bit 3 - TIM5 clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>[src]

Bit 4 - TIM6 clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>[src]

Bit 5 - TIM7 clock enable

pub fn tim12en(&mut self) -> TIM12EN_W<'_>[src]

Bit 6 - TIM12 clock enable

pub fn tim13en(&mut self) -> TIM13EN_W<'_>[src]

Bit 7 - TIM13 clock enable

pub fn tim14en(&mut self) -> TIM14EN_W<'_>[src]

Bit 8 - TIM14 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>[src]

Bit 11 - Window watchdog clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>[src]

Bit 14 - SPI2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>[src]

Bit 15 - SPI3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>[src]

Bit 17 - USART 2 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>[src]

Bit 18 - USART3 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>[src]

Bit 19 - UART4 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>[src]

Bit 20 - UART5 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>[src]

Bit 21 - I2C1 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>[src]

Bit 22 - I2C2 clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>[src]

Bit 23 - I2C3 clock enable

pub fn can1en(&mut self) -> CAN1EN_W<'_>[src]

Bit 25 - CAN 1 clock enable

pub fn can2en(&mut self) -> CAN2EN_W<'_>[src]

Bit 26 - CAN 2 clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>[src]

Bit 28 - Power interface clock enable

pub fn dacen(&mut self) -> DACEN_W<'_>[src]

Bit 29 - DAC interface clock enable

pub fn uart7en(&mut self) -> UART7EN_W<'_>[src]

Bit 30 - UART7 clock enable

pub fn uart8en(&mut self) -> UART8EN_W<'_>[src]

Bit 31 - UART8 clock enable

pub fn spdifrxen(&mut self) -> SPDIFRXEN_W<'_>[src]

Bit 16 - SPDIF-RX clock enable

pub fn cecen(&mut self) -> CECEN_W<'_>[src]

Bit 27 - HDMI-CEN clock enable

pub fn lptmi1en(&mut self) -> LPTMI1EN_W<'_>[src]

Bit 9 - Low power timer 1 clock enable

pub fn i2c4en(&mut self) -> I2C4EN_W<'_>[src]

Bit 24 - I2C4 clock enable

impl W<u32, Reg<u32, _APB2ENR>>[src]

pub fn tim1en(&mut self) -> TIM1EN_W<'_>[src]

Bit 0 - TIM1 clock enable

pub fn tim8en(&mut self) -> TIM8EN_W<'_>[src]

Bit 1 - TIM8 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>[src]

Bit 4 - USART1 clock enable

pub fn usart6en(&mut self) -> USART6EN_W<'_>[src]

Bit 5 - USART6 clock enable

pub fn adc1en(&mut self) -> ADC1EN_W<'_>[src]

Bit 8 - ADC1 clock enable

pub fn adc2en(&mut self) -> ADC2EN_W<'_>[src]

Bit 9 - ADC2 clock enable

pub fn adc3en(&mut self) -> ADC3EN_W<'_>[src]

Bit 10 - ADC3 clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>[src]

Bit 12 - SPI1 clock enable

pub fn spi4en(&mut self) -> SPI4EN_W<'_>[src]

Bit 13 - SPI4 clock enable

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>[src]

Bit 14 - System configuration controller clock enable

pub fn tim9en(&mut self) -> TIM9EN_W<'_>[src]

Bit 16 - TIM9 clock enable

pub fn tim10en(&mut self) -> TIM10EN_W<'_>[src]

Bit 17 - TIM10 clock enable

pub fn tim11en(&mut self) -> TIM11EN_W<'_>[src]

Bit 18 - TIM11 clock enable

pub fn spi5en(&mut self) -> SPI5EN_W<'_>[src]

Bit 20 - SPI5 clock enable

pub fn spi6en(&mut self) -> SPI6EN_W<'_>[src]

Bit 21 - SPI6 clock enable

pub fn sai1en(&mut self) -> SAI1EN_W<'_>[src]

Bit 22 - SAI1 clock enable

pub fn ltdcen(&mut self) -> LTDCEN_W<'_>[src]

Bit 26 - LTDC clock enable

pub fn sai2en(&mut self) -> SAI2EN_W<'_>[src]

Bit 23 - SAI2 clock enable

pub fn sdmmc1en(&mut self) -> SDMMC1EN_W<'_>[src]

Bit 11 - SDMMC1 clock enable

impl W<u32, Reg<u32, _AHB1LPENR>>[src]

pub fn gpioalpen(&mut self) -> GPIOALPEN_W<'_>[src]

Bit 0 - IO port A clock enable during sleep mode

pub fn gpioblpen(&mut self) -> GPIOBLPEN_W<'_>[src]

Bit 1 - IO port B clock enable during Sleep mode

pub fn gpioclpen(&mut self) -> GPIOCLPEN_W<'_>[src]

Bit 2 - IO port C clock enable during Sleep mode

pub fn gpiodlpen(&mut self) -> GPIODLPEN_W<'_>[src]

Bit 3 - IO port D clock enable during Sleep mode

pub fn gpioelpen(&mut self) -> GPIOELPEN_W<'_>[src]

Bit 4 - IO port E clock enable during Sleep mode

pub fn gpioflpen(&mut self) -> GPIOFLPEN_W<'_>[src]

Bit 5 - IO port F clock enable during Sleep mode

pub fn gpioglpen(&mut self) -> GPIOGLPEN_W<'_>[src]

Bit 6 - IO port G clock enable during Sleep mode

pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W<'_>[src]

Bit 7 - IO port H clock enable during Sleep mode

pub fn gpioilpen(&mut self) -> GPIOILPEN_W<'_>[src]

Bit 8 - IO port I clock enable during Sleep mode

pub fn gpiojlpen(&mut self) -> GPIOJLPEN_W<'_>[src]

Bit 9 - IO port J clock enable during Sleep mode

pub fn gpioklpen(&mut self) -> GPIOKLPEN_W<'_>[src]

Bit 10 - IO port K clock enable during Sleep mode

pub fn crclpen(&mut self) -> CRCLPEN_W<'_>[src]

Bit 12 - CRC clock enable during Sleep mode

pub fn flitflpen(&mut self) -> FLITFLPEN_W<'_>[src]

Bit 15 - Flash interface clock enable during Sleep mode

pub fn sram1lpen(&mut self) -> SRAM1LPEN_W<'_>[src]

Bit 16 - SRAM 1interface clock enable during Sleep mode

pub fn sram2lpen(&mut self) -> SRAM2LPEN_W<'_>[src]

Bit 17 - SRAM 2 interface clock enable during Sleep mode

pub fn bkpsramlpen(&mut self) -> BKPSRAMLPEN_W<'_>[src]

Bit 18 - Backup SRAM interface clock enable during Sleep mode

pub fn sram3lpen(&mut self) -> SRAM3LPEN_W<'_>[src]

Bit 19 - SRAM 3 interface clock enable during Sleep mode

pub fn dma1lpen(&mut self) -> DMA1LPEN_W<'_>[src]

Bit 21 - DMA1 clock enable during Sleep mode

pub fn dma2lpen(&mut self) -> DMA2LPEN_W<'_>[src]

Bit 22 - DMA2 clock enable during Sleep mode

pub fn dma2dlpen(&mut self) -> DMA2DLPEN_W<'_>[src]

Bit 23 - DMA2D clock enable during Sleep mode

pub fn ethmaclpen(&mut self) -> ETHMACLPEN_W<'_>[src]

Bit 25 - Ethernet MAC clock enable during Sleep mode

pub fn ethmactxlpen(&mut self) -> ETHMACTXLPEN_W<'_>[src]

Bit 26 - Ethernet transmission clock enable during Sleep mode

pub fn ethmacrxlpen(&mut self) -> ETHMACRXLPEN_W<'_>[src]

Bit 27 - Ethernet reception clock enable during Sleep mode

pub fn ethmacptplpen(&mut self) -> ETHMACPTPLPEN_W<'_>[src]

Bit 28 - Ethernet PTP clock enable during Sleep mode

pub fn otghslpen(&mut self) -> OTGHSLPEN_W<'_>[src]

Bit 29 - USB OTG HS clock enable during Sleep mode

pub fn otghsulpilpen(&mut self) -> OTGHSULPILPEN_W<'_>[src]

Bit 30 - USB OTG HS ULPI clock enable during Sleep mode

impl W<u32, Reg<u32, _AHB2LPENR>>[src]

pub fn otgfslpen(&mut self) -> OTGFSLPEN_W<'_>[src]

Bit 7 - USB OTG FS clock enable during Sleep mode

pub fn rnglpen(&mut self) -> RNGLPEN_W<'_>[src]

Bit 6 - Random number generator clock enable during Sleep mode

pub fn hashlpen(&mut self) -> HASHLPEN_W<'_>[src]

Bit 5 - Hash modules clock enable during Sleep mode

pub fn cryplpen(&mut self) -> CRYPLPEN_W<'_>[src]

Bit 4 - Cryptography modules clock enable during Sleep mode

pub fn dcmilpen(&mut self) -> DCMILPEN_W<'_>[src]

Bit 0 - Camera interface enable during Sleep mode

impl W<u32, Reg<u32, _AHB3LPENR>>[src]

pub fn fmclpen(&mut self) -> FMCLPEN_W<'_>[src]

Bit 0 - Flexible memory controller module clock enable during Sleep mode

pub fn qspilpen(&mut self) -> QSPILPEN_W<'_>[src]

Bit 1 - Quand SPI memory controller clock enable during Sleep mode

impl W<u32, Reg<u32, _APB1LPENR>>[src]

pub fn tim2lpen(&mut self) -> TIM2LPEN_W<'_>[src]

Bit 0 - TIM2 clock enable during Sleep mode

pub fn tim3lpen(&mut self) -> TIM3LPEN_W<'_>[src]

Bit 1 - TIM3 clock enable during Sleep mode

pub fn tim4lpen(&mut self) -> TIM4LPEN_W<'_>[src]

Bit 2 - TIM4 clock enable during Sleep mode

pub fn tim5lpen(&mut self) -> TIM5LPEN_W<'_>[src]

Bit 3 - TIM5 clock enable during Sleep mode

pub fn tim6lpen(&mut self) -> TIM6LPEN_W<'_>[src]

Bit 4 - TIM6 clock enable during Sleep mode

pub fn tim7lpen(&mut self) -> TIM7LPEN_W<'_>[src]

Bit 5 - TIM7 clock enable during Sleep mode

pub fn tim12lpen(&mut self) -> TIM12LPEN_W<'_>[src]

Bit 6 - TIM12 clock enable during Sleep mode

pub fn tim13lpen(&mut self) -> TIM13LPEN_W<'_>[src]

Bit 7 - TIM13 clock enable during Sleep mode

pub fn tim14lpen(&mut self) -> TIM14LPEN_W<'_>[src]

Bit 8 - TIM14 clock enable during Sleep mode

pub fn wwdglpen(&mut self) -> WWDGLPEN_W<'_>[src]

Bit 11 - Window watchdog clock enable during Sleep mode

pub fn spi2lpen(&mut self) -> SPI2LPEN_W<'_>[src]

Bit 14 - SPI2 clock enable during Sleep mode

pub fn spi3lpen(&mut self) -> SPI3LPEN_W<'_>[src]

Bit 15 - SPI3 clock enable during Sleep mode

pub fn usart2lpen(&mut self) -> USART2LPEN_W<'_>[src]

Bit 17 - USART2 clock enable during Sleep mode

pub fn usart3lpen(&mut self) -> USART3LPEN_W<'_>[src]

Bit 18 - USART3 clock enable during Sleep mode

pub fn uart4lpen(&mut self) -> UART4LPEN_W<'_>[src]

Bit 19 - UART4 clock enable during Sleep mode

pub fn uart5lpen(&mut self) -> UART5LPEN_W<'_>[src]

Bit 20 - UART5 clock enable during Sleep mode

pub fn i2c1lpen(&mut self) -> I2C1LPEN_W<'_>[src]

Bit 21 - I2C1 clock enable during Sleep mode

pub fn i2c2lpen(&mut self) -> I2C2LPEN_W<'_>[src]

Bit 22 - I2C2 clock enable during Sleep mode

pub fn i2c3lpen(&mut self) -> I2C3LPEN_W<'_>[src]

Bit 23 - I2C3 clock enable during Sleep mode

pub fn can1lpen(&mut self) -> CAN1LPEN_W<'_>[src]

Bit 25 - CAN 1 clock enable during Sleep mode

pub fn can2lpen(&mut self) -> CAN2LPEN_W<'_>[src]

Bit 26 - CAN 2 clock enable during Sleep mode

pub fn pwrlpen(&mut self) -> PWRLPEN_W<'_>[src]

Bit 28 - Power interface clock enable during Sleep mode

pub fn daclpen(&mut self) -> DACLPEN_W<'_>[src]

Bit 29 - DAC interface clock enable during Sleep mode

pub fn uart7lpen(&mut self) -> UART7LPEN_W<'_>[src]

Bit 30 - UART7 clock enable during Sleep mode

pub fn uart8lpen(&mut self) -> UART8LPEN_W<'_>[src]

Bit 31 - UART8 clock enable during Sleep mode

pub fn spdifrxlpen(&mut self) -> SPDIFRXLPEN_W<'_>[src]

Bit 16 - SPDIF-RX clock enable during sleep mode

pub fn ceclpen(&mut self) -> CECLPEN_W<'_>[src]

Bit 27 - HDMI-CEN clock enable during Sleep mode

pub fn lptim1lpen(&mut self) -> LPTIM1LPEN_W<'_>[src]

Bit 9 - low power timer 1 clock enable during Sleep mode

pub fn i2c4lpen(&mut self) -> I2C4LPEN_W<'_>[src]

Bit 24 - I2C4 clock enable during Sleep mode

impl W<u32, Reg<u32, _APB2LPENR>>[src]

pub fn tim1lpen(&mut self) -> TIM1LPEN_W<'_>[src]

Bit 0 - TIM1 clock enable during Sleep mode

pub fn tim8lpen(&mut self) -> TIM8LPEN_W<'_>[src]

Bit 1 - TIM8 clock enable during Sleep mode

pub fn usart1lpen(&mut self) -> USART1LPEN_W<'_>[src]

Bit 4 - USART1 clock enable during Sleep mode

pub fn usart6lpen(&mut self) -> USART6LPEN_W<'_>[src]

Bit 5 - USART6 clock enable during Sleep mode

pub fn adc1lpen(&mut self) -> ADC1LPEN_W<'_>[src]

Bit 8 - ADC1 clock enable during Sleep mode

pub fn adc2lpen(&mut self) -> ADC2LPEN_W<'_>[src]

Bit 9 - ADC2 clock enable during Sleep mode

pub fn adc3lpen(&mut self) -> ADC3LPEN_W<'_>[src]

Bit 10 - ADC 3 clock enable during Sleep mode

pub fn spi1lpen(&mut self) -> SPI1LPEN_W<'_>[src]

Bit 12 - SPI 1 clock enable during Sleep mode

pub fn spi4lpen(&mut self) -> SPI4LPEN_W<'_>[src]

Bit 13 - SPI 4 clock enable during Sleep mode

pub fn syscfglpen(&mut self) -> SYSCFGLPEN_W<'_>[src]

Bit 14 - System configuration controller clock enable during Sleep mode

pub fn tim9lpen(&mut self) -> TIM9LPEN_W<'_>[src]

Bit 16 - TIM9 clock enable during sleep mode

pub fn tim10lpen(&mut self) -> TIM10LPEN_W<'_>[src]

Bit 17 - TIM10 clock enable during Sleep mode

pub fn tim11lpen(&mut self) -> TIM11LPEN_W<'_>[src]

Bit 18 - TIM11 clock enable during Sleep mode

pub fn spi5lpen(&mut self) -> SPI5LPEN_W<'_>[src]

Bit 20 - SPI 5 clock enable during Sleep mode

pub fn spi6lpen(&mut self) -> SPI6LPEN_W<'_>[src]

Bit 21 - SPI 6 clock enable during Sleep mode

pub fn sai1lpen(&mut self) -> SAI1LPEN_W<'_>[src]

Bit 22 - SAI1 clock enable during sleep mode

pub fn ltdclpen(&mut self) -> LTDCLPEN_W<'_>[src]

Bit 26 - LTDC clock enable during sleep mode

pub fn sai2lpen(&mut self) -> SAI2LPEN_W<'_>[src]

Bit 23 - SAI2 clock enable during sleep mode

pub fn sdmmc1lpen(&mut self) -> SDMMC1LPEN_W<'_>[src]

Bit 11 - SDMMC1 clock enable during Sleep mode

impl W<u32, Reg<u32, _BDCR>>[src]

pub fn bdrst(&mut self) -> BDRST_W<'_>[src]

Bit 16 - Backup domain software reset

pub fn rtcen(&mut self) -> RTCEN_W<'_>[src]

Bit 15 - RTC clock enable

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>[src]

Bit 2 - External low-speed oscillator bypass

pub fn lseon(&mut self) -> LSEON_W<'_>[src]

Bit 0 - External low-speed oscillator enable

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>[src]

Bits 3:4 - LSE oscillator drive capability

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>[src]

Bits 8:9 - RTC clock source selection

impl W<u32, Reg<u32, _CSR>>[src]

pub fn lpwrrstf(&mut self) -> LPWRRSTF_W<'_>[src]

Bit 31 - Low-power reset flag

pub fn wwdgrstf(&mut self) -> WWDGRSTF_W<'_>[src]

Bit 30 - Window watchdog reset flag

pub fn wdgrstf(&mut self) -> WDGRSTF_W<'_>[src]

Bit 29 - Independent watchdog reset flag

pub fn sftrstf(&mut self) -> SFTRSTF_W<'_>[src]

Bit 28 - Software reset flag

pub fn porrstf(&mut self) -> PORRSTF_W<'_>[src]

Bit 27 - POR/PDR reset flag

pub fn padrstf(&mut self) -> PADRSTF_W<'_>[src]

Bit 26 - PIN reset flag

pub fn borrstf(&mut self) -> BORRSTF_W<'_>[src]

Bit 25 - BOR reset flag

pub fn rmvf(&mut self) -> RMVF_W<'_>[src]

Bit 24 - Remove reset flag

pub fn lsion(&mut self) -> LSION_W<'_>[src]

Bit 0 - Internal low-speed oscillator enable

impl W<u32, Reg<u32, _SSCGR>>[src]

pub fn sscgen(&mut self) -> SSCGEN_W<'_>[src]

Bit 31 - Spread spectrum modulation enable

pub fn spreadsel(&mut self) -> SPREADSEL_W<'_>[src]

Bit 30 - Spread Select

pub fn incstep(&mut self) -> INCSTEP_W<'_>[src]

Bits 13:27 - Incrementation step

pub fn modper(&mut self) -> MODPER_W<'_>[src]

Bits 0:12 - Modulation period

impl W<u32, Reg<u32, _PLLI2SCFGR>>[src]

pub fn plli2sr(&mut self) -> PLLI2SR_W<'_>[src]

Bits 28:30 - PLLI2S division factor for I2S clocks

pub fn plli2sq(&mut self) -> PLLI2SQ_W<'_>[src]

Bits 24:27 - PLLI2S division factor for SAI1 clock

pub fn plli2sn(&mut self) -> PLLI2SN_W<'_>[src]

Bits 6:14 - PLLI2S multiplication factor for VCO

pub fn plli2sp(&mut self) -> PLLI2SP_W<'_>[src]

Bits 16:17 - PLLI2S division factor for SPDIFRX clock

impl W<u32, Reg<u32, _PLLSAICFGR>>[src]

pub fn pllsain(&mut self) -> PLLSAIN_W<'_>[src]

Bits 6:14 - PLLSAI division factor for VCO

pub fn pllsaip(&mut self) -> PLLSAIP_W<'_>[src]

Bits 16:17 - PLLSAI division factor for 48MHz clock

pub fn pllsaiq(&mut self) -> PLLSAIQ_W<'_>[src]

Bits 24:27 - PLLSAI division factor for SAI clock

pub fn pllsair(&mut self) -> PLLSAIR_W<'_>[src]

Bits 28:30 - PLLSAI division factor for LCD clock

impl W<u32, Reg<u32, _DCKCFGR1>>[src]

pub fn plli2sdivq(&mut self) -> PLLI2SDIVQ_W<'_>[src]

Bits 0:4 - PLLI2S division factor for SAI1 clock

pub fn pllsaidivq(&mut self) -> PLLSAIDIVQ_W<'_>[src]

Bits 8:12 - PLLSAI division factor for SAI1 clock

pub fn pllsaidivr(&mut self) -> PLLSAIDIVR_W<'_>[src]

Bits 16:17 - division factor for LCD_CLK

pub fn sai1sel(&mut self) -> SAI1SEL_W<'_>[src]

Bits 20:21 - SAI1 clock source selection

pub fn sai2sel(&mut self) -> SAI2SEL_W<'_>[src]

Bits 22:23 - SAI2 clock source selection

pub fn timpre(&mut self) -> TIMPRE_W<'_>[src]

Bit 24 - Timers clocks prescalers selection

pub fn dfsdm1sel(&mut self) -> DFSDM1SEL_W<'_>[src]

Bit 25 - DFSDM1 clock source selection

pub fn adfsdm1sel(&mut self) -> ADFSDM1SEL_W<'_>[src]

Bit 26 - DFSDM1 AUDIO clock source selection

impl W<u32, Reg<u32, _DCKCFGR2>>[src]

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>[src]

Bits 0:1 - USART 1 clock source selection

pub fn usart2sel(&mut self) -> USART2SEL_W<'_>[src]

Bits 2:3 - USART 2 clock source selection

pub fn usart3sel(&mut self) -> USART3SEL_W<'_>[src]

Bits 4:5 - USART 3 clock source selection

pub fn uart4sel(&mut self) -> UART4SEL_W<'_>[src]

Bits 6:7 - UART 4 clock source selection

pub fn uart5sel(&mut self) -> UART5SEL_W<'_>[src]

Bits 8:9 - UART 5 clock source selection

pub fn usart6sel(&mut self) -> USART6SEL_W<'_>[src]

Bits 10:11 - USART 6 clock source selection

pub fn uart7sel(&mut self) -> UART7SEL_W<'_>[src]

Bits 12:13 - UART 7 clock source selection

pub fn uart8sel(&mut self) -> UART8SEL_W<'_>[src]

Bits 14:15 - UART 8 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>[src]

Bits 16:17 - I2C1 clock source selection

pub fn i2c2sel(&mut self) -> I2C2SEL_W<'_>[src]

Bits 18:19 - I2C2 clock source selection

pub fn i2c3sel(&mut self) -> I2C3SEL_W<'_>[src]

Bits 20:21 - I2C3 clock source selection

pub fn i2c4sel(&mut self) -> I2C4SEL_W<'_>[src]

Bits 22:23 - I2C4 clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>[src]

Bits 24:25 - Low power timer 1 clock source selection

pub fn cecsel(&mut self) -> CECSEL_W<'_>[src]

Bit 26 - HDMI-CEC clock source selection

pub fn ck48msel(&mut self) -> CK48MSEL_W<'_>[src]

Bit 27 - 48MHz clock source selection

pub fn sdmmc1sel(&mut self) -> SDMMC1SEL_W<'_>[src]

Bit 28 - SDMMC clock source selection

pub fn sdmmc2sel(&mut self) -> SDMMC2SEL_W<'_>[src]

Bit 29 - SDMMC2 clock source selection

pub fn dsisel(&mut self) -> DSISEL_W<'_>[src]

Bit 30 - DSI clock source selection

impl W<u32, Reg<u32, _MODER>>[src]

pub fn moder15(&mut self) -> MODER15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>[src]

pub fn ot15(&mut self) -> OT15_W<'_>[src]

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>[src]

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>[src]

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>[src]

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>[src]

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>[src]

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>[src]

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>[src]

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>[src]

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>[src]

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>[src]

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>[src]

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>[src]

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>[src]

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>[src]

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>[src]

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>[src]

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>[src]

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>[src]

pub fn odr15(&mut self) -> ODR15_W<'_>[src]

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>[src]

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>[src]

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>[src]

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>[src]

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>[src]

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>[src]

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>[src]

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>[src]

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>[src]

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>[src]

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>[src]

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>[src]

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>[src]

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>[src]

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>[src]

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>[src]

pub fn br15(&mut self) -> BR15_W<'_>[src]

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>[src]

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>[src]

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>[src]

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>[src]

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>[src]

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>[src]

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>[src]

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>[src]

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>[src]

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>[src]

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>[src]

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>[src]

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>[src]

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>[src]

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>[src]

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>[src]

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>[src]

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>[src]

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>[src]

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>[src]

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>[src]

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>[src]

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>[src]

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>[src]

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>[src]

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>[src]

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>[src]

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>[src]

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>[src]

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>[src]

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>[src]

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>[src]

pub fn lckk(&mut self) -> LCKK_W<'_>[src]

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>[src]

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>[src]

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>[src]

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>[src]

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>[src]

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>[src]

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>[src]

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>[src]

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>[src]

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>[src]

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>[src]

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>[src]

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>[src]

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>[src]

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>[src]

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>[src]

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>[src]

pub fn afrl7(&mut self) -> AFRL7_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>[src]

pub fn afrh15(&mut self) -> AFRH15_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>[src]

pub fn br0(&mut self) -> BR0_W<'_>[src]

Bit 0 - Port D Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>[src]

Bit 1 - Port D Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>[src]

Bit 2 - Port D Reset bit 2

pub fn br3(&mut self) -> BR3_W<'_>[src]

Bit 3 - Port D Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>[src]

Bit 4 - Port D Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>[src]

Bit 5 - Port D Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>[src]

Bit 6 - Port D Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>[src]

Bit 7 - Port D Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>[src]

Bit 8 - Port D Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>[src]

Bit 9 - Port D Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>[src]

Bit 10 - Port D Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>[src]

Bit 11 - Port D Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>[src]

Bit 12 - Port D Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>[src]

Bit 13 - Port D Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>[src]

Bit 14 - Port D Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>[src]

Bit 15 - Port D Reset bit 15

impl W<u32, Reg<u32, _MODER>>[src]

pub fn moder15(&mut self) -> MODER15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>[src]

pub fn ot15(&mut self) -> OT15_W<'_>[src]

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>[src]

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>[src]

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>[src]

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>[src]

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>[src]

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>[src]

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>[src]

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>[src]

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>[src]

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>[src]

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>[src]

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>[src]

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>[src]

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>[src]

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>[src]

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>[src]

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>[src]

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>[src]

pub fn odr15(&mut self) -> ODR15_W<'_>[src]

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>[src]

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>[src]

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>[src]

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>[src]

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>[src]

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>[src]

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>[src]

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>[src]

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>[src]

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>[src]

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>[src]

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>[src]

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>[src]

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>[src]

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>[src]

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>[src]

pub fn br15(&mut self) -> BR15_W<'_>[src]

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>[src]

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>[src]

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>[src]

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>[src]

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>[src]

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>[src]

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>[src]

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>[src]

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>[src]

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>[src]

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>[src]

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>[src]

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>[src]

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>[src]

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>[src]

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>[src]

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>[src]

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>[src]

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>[src]

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>[src]

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>[src]

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>[src]

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>[src]

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>[src]

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>[src]

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>[src]

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>[src]

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>[src]

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>[src]

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>[src]

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>[src]

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>[src]

pub fn lckk(&mut self) -> LCKK_W<'_>[src]

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>[src]

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>[src]

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>[src]

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>[src]

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>[src]

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>[src]

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>[src]

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>[src]

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>[src]

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>[src]

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>[src]

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>[src]

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>[src]

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>[src]

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>[src]

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>[src]

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>[src]

pub fn afrl7(&mut self) -> AFRL7_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>[src]

pub fn afrh15(&mut self) -> AFRH15_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>[src]

pub fn br0(&mut self) -> BR0_W<'_>[src]

Bit 0 - Port B Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>[src]

Bit 1 - Port B Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>[src]

Bit 2 - Port B Reset bit 2

pub fn br3(&mut self) -> BR3_W<'_>[src]

Bit 3 - Port B Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>[src]

Bit 4 - Port B Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>[src]

Bit 5 - Port B Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>[src]

Bit 6 - Port B Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>[src]

Bit 7 - Port B Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>[src]

Bit 8 - Port B Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>[src]

Bit 9 - Port B Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>[src]

Bit 10 - Port B Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>[src]

Bit 11 - Port B Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>[src]

Bit 12 - Port B Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>[src]

Bit 13 - Port B Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>[src]

Bit 14 - Port B Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>[src]

Bit 15 - Port B Reset bit 15

impl W<u32, Reg<u32, _MODER>>[src]

pub fn moder15(&mut self) -> MODER15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>[src]

pub fn ot15(&mut self) -> OT15_W<'_>[src]

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>[src]

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>[src]

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>[src]

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>[src]

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>[src]

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>[src]

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>[src]

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>[src]

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>[src]

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>[src]

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>[src]

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>[src]

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>[src]

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>[src]

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>[src]

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>[src]

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>[src]

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>[src]

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>[src]

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>[src]

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>[src]

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>[src]

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>[src]

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>[src]

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>[src]

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>[src]

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>[src]

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>[src]

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>[src]

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>[src]

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>[src]

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>[src]

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>[src]

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>[src]

pub fn odr15(&mut self) -> ODR15_W<'_>[src]

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>[src]

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>[src]

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>[src]

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>[src]

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>[src]

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>[src]

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>[src]

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>[src]

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>[src]

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>[src]

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>[src]

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>[src]

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>[src]

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>[src]

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>[src]

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>[src]

pub fn br15(&mut self) -> BR15_W<'_>[src]

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>[src]

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>[src]

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>[src]

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>[src]

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>[src]

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>[src]

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>[src]

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>[src]

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>[src]

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>[src]

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>[src]

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>[src]

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>[src]

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>[src]

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>[src]

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>[src]

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>[src]

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>[src]

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>[src]

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>[src]

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>[src]

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>[src]

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>[src]

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>[src]

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>[src]

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>[src]

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>[src]

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>[src]

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>[src]

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>[src]

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>[src]

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>[src]

pub fn lckk(&mut self) -> LCKK_W<'_>[src]

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>[src]

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>[src]

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>[src]

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>[src]

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>[src]

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>[src]

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>[src]

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>[src]

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>[src]

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>[src]

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>[src]

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>[src]

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>[src]

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>[src]

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>[src]

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>[src]

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>[src]

pub fn afrl7(&mut self) -> AFRL7_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>[src]

pub fn afrh15(&mut self) -> AFRH15_W<'_>[src]

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>[src]

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>[src]

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>[src]

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>[src]

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>[src]

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>[src]

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>[src]

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _BRR>>[src]

pub fn br0(&mut self) -> BR0_W<'_>[src]

Bit 0 - Port A Reset bit 0

pub fn br1(&mut self) -> BR1_W<'_>[src]

Bit 1 - Port A Reset bit 1

pub fn br2(&mut self) -> BR2_W<'_>[src]

Bit 2 - Port A Reset bit 2

pub fn br3(&mut self) -> BR3_W<'_>[src]

Bit 3 - Port A Reset bit 3

pub fn br4(&mut self) -> BR4_W<'_>[src]

Bit 4 - Port A Reset bit 4

pub fn br5(&mut self) -> BR5_W<'_>[src]

Bit 5 - Port A Reset bit 5

pub fn br6(&mut self) -> BR6_W<'_>[src]

Bit 6 - Port A Reset bit 6

pub fn br7(&mut self) -> BR7_W<'_>[src]

Bit 7 - Port A Reset bit 7

pub fn br8(&mut self) -> BR8_W<'_>[src]

Bit 8 - Port A Reset bit 8

pub fn br9(&mut self) -> BR9_W<'_>[src]

Bit 9 - Port A Reset bit 9

pub fn br10(&mut self) -> BR10_W<'_>[src]

Bit 10 - Port A Reset bit 10

pub fn br11(&mut self) -> BR11_W<'_>[src]

Bit 11 - Port A Reset bit 11

pub fn br12(&mut self) -> BR12_W<'_>[src]

Bit 12 - Port A Reset bit 12

pub fn br13(&mut self) -> BR13_W<'_>[src]

Bit 13 - Port A Reset bit 13

pub fn br14(&mut self) -> BR14_W<'_>[src]

Bit 14 - Port A Reset bit 14

pub fn br15(&mut self) -> BR15_W<'_>[src]

Bit 15 - Port A Reset bit 15

impl W<u32, Reg<u32, _MEMRM>>[src]

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>[src]

Bits 0:2 - Memory mapping selection

pub fn fb_mode(&mut self) -> FB_MODE_W<'_>[src]

Bit 8 - Flash bank mode selection

pub fn swp_fmc(&mut self) -> SWP_FMC_W<'_>[src]

Bits 10:11 - FMC memory mapping swap

impl W<u32, Reg<u32, _PMC>>[src]

pub fn mii_rmii_sel(&mut self) -> MII_RMII_SEL_W<'_>[src]

Bit 23 - Ethernet PHY interface selection

pub fn adc1dc2(&mut self) -> ADC1DC2_W<'_>[src]

Bit 16 - ADC1DC2

pub fn adc2dc2(&mut self) -> ADC2DC2_W<'_>[src]

Bit 17 - ADC2DC2

pub fn adc3dc2(&mut self) -> ADC3DC2_W<'_>[src]

Bit 18 - ADC3DC2

impl W<u32, Reg<u32, _EXTICR1>>[src]

pub fn exti3(&mut self) -> EXTI3_W<'_>[src]

Bits 12:15 - EXTI x configuration (x = 0 to 3)

pub fn exti2(&mut self) -> EXTI2_W<'_>[src]

Bits 8:11 - EXTI x configuration (x = 0 to 3)

pub fn exti1(&mut self) -> EXTI1_W<'_>[src]

Bits 4:7 - EXTI x configuration (x = 0 to 3)

pub fn exti0(&mut self) -> EXTI0_W<'_>[src]

Bits 0:3 - EXTI x configuration (x = 0 to 3)

impl W<u32, Reg<u32, _EXTICR2>>[src]

pub fn exti7(&mut self) -> EXTI7_W<'_>[src]

Bits 12:15 - EXTI x configuration (x = 4 to 7)

pub fn exti6(&mut self) -> EXTI6_W<'_>[src]

Bits 8:11 - EXTI x configuration (x = 4 to 7)

pub fn exti5(&mut self) -> EXTI5_W<'_>[src]

Bits 4:7 - EXTI x configuration (x = 4 to 7)

pub fn exti4(&mut self) -> EXTI4_W<'_>[src]

Bits 0:3 - EXTI x configuration (x = 4 to 7)

impl W<u32, Reg<u32, _EXTICR3>>[src]

pub fn exti11(&mut self) -> EXTI11_W<'_>[src]

Bits 12:15 - EXTI x configuration (x = 8 to 11)

pub fn exti10(&mut self) -> EXTI10_W<'_>[src]

Bits 8:11 - EXTI10

pub fn exti9(&mut self) -> EXTI9_W<'_>[src]

Bits 4:7 - EXTI x configuration (x = 8 to 11)

pub fn exti8(&mut self) -> EXTI8_W<'_>[src]

Bits 0:3 - EXTI x configuration (x = 8 to 11)

impl W<u32, Reg<u32, _EXTICR4>>[src]

pub fn exti15(&mut self) -> EXTI15_W<'_>[src]

Bits 12:15 - EXTI x configuration (x = 12 to 15)

pub fn exti14(&mut self) -> EXTI14_W<'_>[src]

Bits 8:11 - EXTI x configuration (x = 12 to 15)

pub fn exti13(&mut self) -> EXTI13_W<'_>[src]

Bits 4:7 - EXTI x configuration (x = 12 to 15)

pub fn exti12(&mut self) -> EXTI12_W<'_>[src]

Bits 0:3 - EXTI x configuration (x = 12 to 15)

impl W<u32, Reg<u32, _CR1>>[src]

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>[src]

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>[src]

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>[src]

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>[src]

Bit 12 - CRC transfer next

pub fn crcl(&mut self) -> CRCL_W<'_>[src]

Bit 11 - CRC length

pub fn rxonly(&mut self) -> RXONLY_W<'_>[src]

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>[src]

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>[src]

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>[src]

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>[src]

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>[src]

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>[src]

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>[src]

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>[src]

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>[src]

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>[src]

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>[src]

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>[src]

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>[src]

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>[src]

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>[src]

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>[src]

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>[src]

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>[src]

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>[src]

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>[src]

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>[src]

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>[src]

pub fn crcerr(&mut self) -> CRCERR_W<'_>[src]

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>[src]

pub fn dr(&mut self) -> DR_W<'_>[src]

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>[src]

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>[src]

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _I2SCFGR>>[src]

pub fn i2smod(&mut self) -> I2SMOD_W<'_>[src]

Bit 11 - I2S mode selection

pub fn i2se(&mut self) -> I2SE_W<'_>[src]

Bit 10 - I2S Enable

pub fn i2scfg(&mut self) -> I2SCFG_W<'_>[src]

Bits 8:9 - I2S configuration mode

pub fn pcmsync(&mut self) -> PCMSYNC_W<'_>[src]

Bit 7 - PCM frame synchronization

pub fn i2sstd(&mut self) -> I2SSTD_W<'_>[src]

Bits 4:5 - I2S standard selection

pub fn ckpol(&mut self) -> CKPOL_W<'_>[src]

Bit 3 - Steady state clock polarity

pub fn datlen(&mut self) -> DATLEN_W<'_>[src]

Bits 1:2 - Data length to be transferred

pub fn chlen(&mut self) -> CHLEN_W<'_>[src]

Bit 0 - Channel length (number of bits per audio channel)

pub fn astrten(&mut self) -> ASTRTEN_W<'_>[src]

Bit 12 - Asynchronous start enable

impl W<u32, Reg<u32, _I2SPR>>[src]

pub fn mckoe(&mut self) -> MCKOE_W<'_>[src]

Bit 9 - Master clock output enable

pub fn odd(&mut self) -> ODD_W<'_>[src]

Bit 8 - Odd factor for the prescaler

pub fn i2sdiv(&mut self) -> I2SDIV_W<'_>[src]

Bits 0:7 - I2S Linear prescaler

impl W<u32, Reg<u32, _SR>>[src]

pub fn ovr(&mut self) -> OVR_W<'_>[src]

Bit 5 - Overrun

pub fn strt(&mut self) -> STRT_W<'_>[src]

Bit 4 - Regular channel start flag

pub fn jstrt(&mut self) -> JSTRT_W<'_>[src]

Bit 3 - Injected channel start flag

pub fn jeoc(&mut self) -> JEOC_W<'_>[src]

Bit 2 - Injected channel end of conversion

pub fn eoc(&mut self) -> EOC_W<'_>[src]

Bit 1 - Regular channel end of conversion

pub fn awd(&mut self) -> AWD_W<'_>[src]

Bit 0 - Analog watchdog flag

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ovrie(&mut self) -> OVRIE_W<'_>[src]

Bit 26 - Overrun interrupt enable

pub fn res(&mut self) -> RES_W<'_>[src]

Bits 24:25 - Resolution

pub fn awden(&mut self) -> AWDEN_W<'_>[src]

Bit 23 - Analog watchdog enable on regular channels

pub fn jawden(&mut self) -> JAWDEN_W<'_>[src]

Bit 22 - Analog watchdog enable on injected channels

pub fn discnum(&mut self) -> DISCNUM_W<'_>[src]

Bits 13:15 - Discontinuous mode channel count

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>[src]

Bit 12 - Discontinuous mode on injected channels

pub fn discen(&mut self) -> DISCEN_W<'_>[src]

Bit 11 - Discontinuous mode on regular channels

pub fn jauto(&mut self) -> JAUTO_W<'_>[src]

Bit 10 - Automatic injected group conversion

pub fn awdsgl(&mut self) -> AWDSGL_W<'_>[src]

Bit 9 - Enable the watchdog on a single channel in scan mode

pub fn scan(&mut self) -> SCAN_W<'_>[src]

Bit 8 - Scan mode

pub fn jeocie(&mut self) -> JEOCIE_W<'_>[src]

Bit 7 - Interrupt enable for injected channels

pub fn awdie(&mut self) -> AWDIE_W<'_>[src]

Bit 6 - Analog watchdog interrupt enable

pub fn eocie(&mut self) -> EOCIE_W<'_>[src]

Bit 5 - Interrupt enable for EOC

pub fn awdch(&mut self) -> AWDCH_W<'_>[src]

Bits 0:4 - Analog watchdog channel select bits

impl W<u32, Reg<u32, _CR2>>[src]

pub fn swstart(&mut self) -> SWSTART_W<'_>[src]

Bit 30 - Start conversion of regular channels

pub fn exten(&mut self) -> EXTEN_W<'_>[src]

Bits 28:29 - External trigger enable for regular channels

pub fn extsel(&mut self) -> EXTSEL_W<'_>[src]

Bits 24:27 - External event select for regular group

pub fn jswstart(&mut self) -> JSWSTART_W<'_>[src]

Bit 22 - Start conversion of injected channels

pub fn jexten(&mut self) -> JEXTEN_W<'_>[src]

Bits 20:21 - External trigger enable for injected channels

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>[src]

Bits 16:19 - External event select for injected group

pub fn align(&mut self) -> ALIGN_W<'_>[src]

Bit 11 - Data alignment

pub fn eocs(&mut self) -> EOCS_W<'_>[src]

Bit 10 - End of conversion selection

pub fn dds(&mut self) -> DDS_W<'_>[src]

Bit 9 - DMA disable selection (for single ADC mode)

pub fn dma(&mut self) -> DMA_W<'_>[src]

Bit 8 - Direct memory access mode (for single ADC mode)

pub fn cont(&mut self) -> CONT_W<'_>[src]

Bit 1 - Continuous conversion

pub fn adon(&mut self) -> ADON_W<'_>[src]

Bit 0 - A/D Converter ON / OFF

impl W<u32, Reg<u32, _SMPR1>>[src]

pub fn smpx_x(&mut self) -> SMPX_X_W<'_>[src]

Bits 0:31 - Sample time bits

impl W<u32, Reg<u32, _SMPR2>>[src]

pub fn smpx_x(&mut self) -> SMPX_X_W<'_>[src]

Bits 0:31 - Sample time bits

impl W<u32, Reg<u32, _JOFR>>[src]

pub fn joffset(&mut self) -> JOFFSET_W<'_>[src]

Bits 0:11 - Data offset for injected channel x

impl W<u32, Reg<u32, _HTR>>[src]

pub fn ht(&mut self) -> HT_W<'_>[src]

Bits 0:11 - Analog watchdog higher threshold

impl W<u32, Reg<u32, _LTR>>[src]

pub fn lt(&mut self) -> LT_W<'_>[src]

Bits 0:11 - Analog watchdog lower threshold

impl W<u32, Reg<u32, _SQR1>>[src]

pub fn l(&mut self) -> L_W<'_>[src]

Bits 20:23 - Regular channel sequence length

pub fn sq16(&mut self) -> SQ16_W<'_>[src]

Bits 15:19 - 16th conversion in regular sequence

pub fn sq15(&mut self) -> SQ15_W<'_>[src]

Bits 10:14 - 15th conversion in regular sequence

pub fn sq14(&mut self) -> SQ14_W<'_>[src]

Bits 5:9 - 14th conversion in regular sequence

pub fn sq13(&mut self) -> SQ13_W<'_>[src]

Bits 0:4 - 13th conversion in regular sequence

impl W<u32, Reg<u32, _SQR2>>[src]

pub fn sq12(&mut self) -> SQ12_W<'_>[src]

Bits 25:29 - 12th conversion in regular sequence

pub fn sq11(&mut self) -> SQ11_W<'_>[src]

Bits 20:24 - 11th conversion in regular sequence

pub fn sq10(&mut self) -> SQ10_W<'_>[src]

Bits 15:19 - 10th conversion in regular sequence

pub fn sq9(&mut self) -> SQ9_W<'_>[src]

Bits 10:14 - 9th conversion in regular sequence

pub fn sq8(&mut self) -> SQ8_W<'_>[src]

Bits 5:9 - 8th conversion in regular sequence

pub fn sq7(&mut self) -> SQ7_W<'_>[src]

Bits 0:4 - 7th conversion in regular sequence

impl W<u32, Reg<u32, _SQR3>>[src]

pub fn sq6(&mut self) -> SQ6_W<'_>[src]

Bits 25:29 - 6th conversion in regular sequence

pub fn sq5(&mut self) -> SQ5_W<'_>[src]

Bits 20:24 - 5th conversion in regular sequence

pub fn sq4(&mut self) -> SQ4_W<'_>[src]

Bits 15:19 - 4th conversion in regular sequence

pub fn sq3(&mut self) -> SQ3_W<'_>[src]

Bits 10:14 - 3rd conversion in regular sequence

pub fn sq2(&mut self) -> SQ2_W<'_>[src]

Bits 5:9 - 2nd conversion in regular sequence

pub fn sq1(&mut self) -> SQ1_W<'_>[src]

Bits 0:4 - 1st conversion in regular sequence

impl W<u32, Reg<u32, _JSQR>>[src]

pub fn jl(&mut self) -> JL_W<'_>[src]

Bits 20:21 - Injected sequence length

pub fn jsq4(&mut self) -> JSQ4_W<'_>[src]

Bits 15:19 - 4th conversion in injected sequence

pub fn jsq3(&mut self) -> JSQ3_W<'_>[src]

Bits 10:14 - 3rd conversion in injected sequence

pub fn jsq2(&mut self) -> JSQ2_W<'_>[src]

Bits 5:9 - 2nd conversion in injected sequence

pub fn jsq1(&mut self) -> JSQ1_W<'_>[src]

Bits 0:4 - 1st conversion in injected sequence

impl W<u32, Reg<u32, _CR>>[src]

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>[src]

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>[src]

Bit 28 - DAC channel2 DMA enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>[src]

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn wave2(&mut self) -> WAVE2_W<'_>[src]

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>[src]

Bits 19:21 - DAC channel2 trigger selection

pub fn ten2(&mut self) -> TEN2_W<'_>[src]

Bit 18 - DAC channel2 trigger enable

pub fn boff2(&mut self) -> BOFF2_W<'_>[src]

Bit 17 - DAC channel2 output buffer disable

pub fn en2(&mut self) -> EN2_W<'_>[src]

Bit 16 - DAC channel2 enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>[src]

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>[src]

Bit 12 - DAC channel1 DMA enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>[src]

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn wave1(&mut self) -> WAVE1_W<'_>[src]

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>[src]

Bits 3:5 - DAC channel1 trigger selection

pub fn ten1(&mut self) -> TEN1_W<'_>[src]

Bit 2 - DAC channel1 trigger enable

pub fn boff1(&mut self) -> BOFF1_W<'_>[src]

Bit 1 - DAC channel1 output buffer disable

pub fn en1(&mut self) -> EN1_W<'_>[src]

Bit 0 - DAC channel1 enable

impl W<u32, Reg<u32, _SWTRIGR>>[src]

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>[src]

Bit 1 - DAC channel2 software trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>[src]

Bit 0 - DAC channel1 software trigger

impl W<u32, Reg<u32, _DHR12R1>>[src]

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>[src]

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>[src]

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 16:27 - DAC channel2 12-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 20:31 - DAC channel2 12-bit left-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>[src]

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>[src]

Bits 8:15 - DAC channel2 8-bit right-aligned data

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>[src]

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>[src]

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>[src]

Bit 29 - DAC channel2 DMA underrun flag

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>[src]

Bit 13 - DAC channel1 DMA underrun flag

impl W<u32, Reg<u32, _CR1>>[src]

pub fn lpds(&mut self) -> LPDS_W<'_>[src]

Bit 0 - Low-power deep sleep

pub fn pdds(&mut self) -> PDDS_W<'_>[src]

Bit 1 - Power down deepsleep

pub fn csbf(&mut self) -> CSBF_W<'_>[src]

Bit 3 - Clear standby flag

pub fn pvde(&mut self) -> PVDE_W<'_>[src]

Bit 4 - Power voltage detector enable

pub fn pls(&mut self) -> PLS_W<'_>[src]

Bits 5:7 - PVD level selection

pub fn dbp(&mut self) -> DBP_W<'_>[src]

Bit 8 - Disable backup domain write protection

pub fn fpds(&mut self) -> FPDS_W<'_>[src]

Bit 9 - Flash power down in Stop mode

pub fn lpuds(&mut self) -> LPUDS_W<'_>[src]

Bit 10 - Low-power regulator in deepsleep under-drive mode

pub fn mruds(&mut self) -> MRUDS_W<'_>[src]

Bit 11 - Main regulator in deepsleep under-drive mode

pub fn adcdc1(&mut self) -> ADCDC1_W<'_>[src]

Bit 13 - ADCDC1

pub fn vos(&mut self) -> VOS_W<'_>[src]

Bits 14:15 - Regulator voltage scaling output selection

pub fn oden(&mut self) -> ODEN_W<'_>[src]

Bit 16 - Over-drive enable

pub fn odswen(&mut self) -> ODSWEN_W<'_>[src]

Bit 17 - Over-drive switching enabled

pub fn uden(&mut self) -> UDEN_W<'_>[src]

Bits 18:19 - Under-drive enable in stop mode

impl W<u32, Reg<u32, _CSR1>>[src]

pub fn bre(&mut self) -> BRE_W<'_>[src]

Bit 9 - Backup regulator enable

pub fn vosrdy(&mut self) -> VOSRDY_W<'_>[src]

Bit 14 - Regulator voltage scaling output selection ready bit

pub fn odrdy(&mut self) -> ODRDY_W<'_>[src]

Bit 16 - Over-drive mode ready

pub fn odswrdy(&mut self) -> ODSWRDY_W<'_>[src]

Bit 17 - Over-drive mode switching ready

pub fn udrdy(&mut self) -> UDRDY_W<'_>[src]

Bits 18:19 - Under-drive ready flag

impl W<u32, Reg<u32, _CR2>>[src]

pub fn wupp1(&mut self) -> WUPP1_W<'_>[src]

Bit 8 - Wakeup pin polarity bit for PA0

pub fn wupp2(&mut self) -> WUPP2_W<'_>[src]

Bit 9 - Wakeup pin polarity bit for PA2

pub fn wupp3(&mut self) -> WUPP3_W<'_>[src]

Bit 10 - Wakeup pin polarity bit for PC1

pub fn wupp4(&mut self) -> WUPP4_W<'_>[src]

Bit 11 - Wakeup pin polarity bit for PC13

pub fn wupp5(&mut self) -> WUPP5_W<'_>[src]

Bit 12 - Wakeup pin polarity bit for PI8

pub fn wupp6(&mut self) -> WUPP6_W<'_>[src]

Bit 13 - Wakeup pin polarity bit for PI11

impl W<u32, Reg<u32, _CSR2>>[src]

pub fn ewup1(&mut self) -> EWUP1_W<'_>[src]

Bit 8 - Enable Wakeup pin for PA0

pub fn ewup2(&mut self) -> EWUP2_W<'_>[src]

Bit 9 - Enable Wakeup pin for PA2

pub fn ewup3(&mut self) -> EWUP3_W<'_>[src]

Bit 10 - Enable Wakeup pin for PC1

pub fn ewup4(&mut self) -> EWUP4_W<'_>[src]

Bit 11 - Enable Wakeup pin for PC13

pub fn ewup5(&mut self) -> EWUP5_W<'_>[src]

Bit 12 - Enable Wakeup pin for PI8

pub fn ewup6(&mut self) -> EWUP6_W<'_>[src]

Bit 13 - Enable Wakeup pin for PI11

impl W<u32, Reg<u32, _KR>>[src]

pub fn key(&mut self) -> KEY_W<'_>[src]

Bits 0:15 - Key value (write only, read 0000h)

impl W<u32, Reg<u32, _PR>>[src]

pub fn pr(&mut self) -> PR_W<'_>[src]

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>[src]

pub fn rl(&mut self) -> RL_W<'_>[src]

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>[src]

pub fn win(&mut self) -> WIN_W<'_>[src]

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>[src]

pub fn wdga(&mut self) -> WDGA_W<'_>[src]

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>[src]

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>[src]

pub fn ewi(&mut self) -> EWI_W<'_>[src]

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>[src]

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>[src]

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>[src]

pub fn ewif(&mut self) -> EWIF_W<'_>[src]

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>[src]

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>[src]

pub fn ois4(&mut self) -> OIS4_W<'_>[src]

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>[src]

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>[src]

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>[src]

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>[src]

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>[src]

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>[src]

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>[src]

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>[src]

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>[src]

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>[src]

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn etp(&mut self) -> ETP_W<'_>[src]

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>[src]

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>[src]

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>[src]

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tde(&mut self) -> TDE_W<'_>[src]

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>[src]

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>[src]

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>[src]

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>[src]

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>[src]

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>[src]

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>[src]

Bit 5 - COM interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc4of(&mut self) -> CC4OF_W<'_>[src]

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>[src]

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>[src]

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>[src]

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn bg(&mut self) -> BG_W<'_>[src]

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>[src]

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>[src]

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>[src]

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2ce(&mut self) -> OC2CE_W<'_>[src]

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>[src]

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>[src]

pub fn oc4ce(&mut self) -> OC4CE_W<'_>[src]

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>[src]

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>[src]

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>[src]

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>[src]

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>[src]

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>[src]

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>[src]

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>[src]

pub fn ic4f(&mut self) -> IC4F_W<'_>[src]

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>[src]

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>[src]

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>[src]

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc4p(&mut self) -> CC4P_W<'_>[src]

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>[src]

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>[src]

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>[src]

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>[src]

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>[src]

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>[src]

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>[src]

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>[src]

pub fn dbl(&mut self) -> DBL_W<'_>[src]

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>[src]

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>[src]

pub fn dmab(&mut self) -> DMAB_W<'_>[src]

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _RCR>>[src]

pub fn rep(&mut self) -> REP_W<'_>[src]

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _BDTR>>[src]

pub fn moe(&mut self) -> MOE_W<'_>[src]

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>[src]

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>[src]

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>[src]

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>[src]

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>[src]

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>[src]

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>[src]

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>[src]

pub fn oc5fe(&mut self) -> OC5FE_W<'_>[src]

Bit 2 - Output compare 5 fast enable

pub fn oc5pe(&mut self) -> OC5PE_W<'_>[src]

Bit 3 - Output compare 5 preload enable

pub fn oc5m(&mut self) -> OC5M_W<'_>[src]

Bits 4:6 - Output compare 5 mode

pub fn oc5ce(&mut self) -> OC5CE_W<'_>[src]

Bit 7 - Output compare 5 clear enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>[src]

Bit 10 - Output compare 6 fast enable

pub fn oc6pe(&mut self) -> OC6PE_W<'_>[src]

Bit 11 - Output compare 6 preload enable

pub fn oc6m(&mut self) -> OC6M_W<'_>[src]

Bits 12:14 - Output compare 6 mode

pub fn oc6ce(&mut self) -> OC6CE_W<'_>[src]

Bit 15 - Output compare 6 clear enable

pub fn oc5m3(&mut self) -> OC5M3_W<'_>[src]

Bit 16 - Output Compare 5 mode

pub fn oc6m3(&mut self) -> OC6M3_W<'_>[src]

Bit 24 - Output Compare 6 mode

impl W<u32, Reg<u32, _CCR5>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 5 value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>[src]

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>[src]

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>[src]

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CRR6>>[src]

pub fn ccr6(&mut self) -> CCR6_W<'_>[src]

Bits 0:15 - Capture/Compare 6 value

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>[src]

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>[src]

pub fn ti1s(&mut self) -> TI1S_W<'_>[src]

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>[src]

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn etp(&mut self) -> ETP_W<'_>[src]

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>[src]

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>[src]

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>[src]

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tde(&mut self) -> TDE_W<'_>[src]

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>[src]

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>[src]

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>[src]

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>[src]

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc4of(&mut self) -> CC4OF_W<'_>[src]

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>[src]

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>[src]

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>[src]

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2ce(&mut self) -> OC2CE_W<'_>[src]

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>[src]

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>[src]

pub fn oc4ce(&mut self) -> OC4CE_W<'_>[src]

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>[src]

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>[src]

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>[src]

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>[src]

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>[src]

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>[src]

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>[src]

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>[src]

pub fn ic4f(&mut self) -> IC4F_W<'_>[src]

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>[src]

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>[src]

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>[src]

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc4np(&mut self) -> CC4NP_W<'_>[src]

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>[src]

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>[src]

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>[src]

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>[src]

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>[src]

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>[src]

pub fn dbl(&mut self) -> DBL_W<'_>[src]

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>[src]

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>[src]

pub fn dmab(&mut self) -> DMAB_W<'_>[src]

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>[src]

pub fn ti4_rmp(&mut self) -> TI4_RMP_W<'_>[src]

Bits 2:3 - Input Capture 4 remap

pub fn etr1_rmp(&mut self) -> ETR1_RMP_W<'_>[src]

Bit 1 - External trigger remap

pub fn itr1_rmp(&mut self) -> ITR1_RMP_W<'_>[src]

Bit 0 - Internal trigger 1 remap

impl W<u32, Reg<u32, _OR2>>[src]

pub fn etrsel(&mut self) -> ETRSEL_W<'_>[src]

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>[src]

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>[src]

pub fn ti1s(&mut self) -> TI1S_W<'_>[src]

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>[src]

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn etp(&mut self) -> ETP_W<'_>[src]

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>[src]

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>[src]

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>[src]

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tde(&mut self) -> TDE_W<'_>[src]

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>[src]

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>[src]

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>[src]

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>[src]

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc4of(&mut self) -> CC4OF_W<'_>[src]

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>[src]

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>[src]

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>[src]

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2ce(&mut self) -> OC2CE_W<'_>[src]

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>[src]

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>[src]

pub fn oc4ce(&mut self) -> OC4CE_W<'_>[src]

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>[src]

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>[src]

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>[src]

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>[src]

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>[src]

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>[src]

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>[src]

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>[src]

pub fn ic4f(&mut self) -> IC4F_W<'_>[src]

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>[src]

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>[src]

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>[src]

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc4np(&mut self) -> CC4NP_W<'_>[src]

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>[src]

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>[src]

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>[src]

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>[src]

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>[src]

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt_h(&mut self) -> CNT_H_W<'_>[src]

Bits 16:31 - High counter value

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr_h(&mut self) -> ARR_H_W<'_>[src]

Bits 16:31 - High Auto-reload value

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>[src]

Bits 16:31 - High Capture/Compare 1 value

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>[src]

pub fn dbl(&mut self) -> DBL_W<'_>[src]

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>[src]

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>[src]

pub fn dmab(&mut self) -> DMAB_W<'_>[src]

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>[src]

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>[src]

Bits 0:1 - Input Capture 1 remap

impl W<u32, Reg<u32, _OR2>>[src]

pub fn etrsel(&mut self) -> ETRSEL_W<'_>[src]

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>[src]

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>[src]

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>[src]

pub fn ti1s(&mut self) -> TI1S_W<'_>[src]

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>[src]

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn etp(&mut self) -> ETP_W<'_>[src]

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>[src]

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>[src]

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>[src]

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tde(&mut self) -> TDE_W<'_>[src]

Bit 14 - Trigger DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>[src]

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>[src]

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>[src]

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>[src]

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc4of(&mut self) -> CC4OF_W<'_>[src]

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>[src]

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>[src]

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>[src]

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>[src]

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>[src]

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2ce(&mut self) -> OC2CE_W<'_>[src]

Bit 15 - OC2CE

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - OC2M

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - OC2PE

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - OC2FE

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - CC2S

pub fn oc1ce(&mut self) -> OC1CE_W<'_>[src]

Bit 7 - OC1CE

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - OC1M

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - OC1PE

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - OC1FE

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - CC1S

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>[src]

pub fn oc4ce(&mut self) -> OC4CE_W<'_>[src]

Bit 15 - O24CE

pub fn oc4m(&mut self) -> OC4M_W<'_>[src]

Bits 12:14 - OC4M

pub fn oc4pe(&mut self) -> OC4PE_W<'_>[src]

Bit 11 - OC4PE

pub fn oc4fe(&mut self) -> OC4FE_W<'_>[src]

Bit 10 - OC4FE

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - CC4S

pub fn oc3ce(&mut self) -> OC3CE_W<'_>[src]

Bit 7 - OC3CE

pub fn oc3m(&mut self) -> OC3M_W<'_>[src]

Bits 4:6 - OC3M

pub fn oc3pe(&mut self) -> OC3PE_W<'_>[src]

Bit 3 - OC3PE

pub fn oc3fe(&mut self) -> OC3FE_W<'_>[src]

Bit 2 - OC3FE

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - CC3S

impl W<u32, Reg<u32, _CCMR2_INPUT>>[src]

pub fn ic4f(&mut self) -> IC4F_W<'_>[src]

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>[src]

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>[src]

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>[src]

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>[src]

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>[src]

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc4np(&mut self) -> CC4NP_W<'_>[src]

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>[src]

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>[src]

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>[src]

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>[src]

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>[src]

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt_h(&mut self) -> CNT_H_W<'_>[src]

Bits 16:31 - High counter value

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr_h(&mut self) -> ARR_H_W<'_>[src]

Bits 16:31 - High Auto-reload value

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>[src]

Bits 16:31 - High Capture/Compare 1 value

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>[src]

pub fn dbl(&mut self) -> DBL_W<'_>[src]

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>[src]

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>[src]

pub fn dmab(&mut self) -> DMAB_W<'_>[src]

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>[src]

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 6 - Trigger interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc2of(&mut self) -> CC2OF_W<'_>[src]

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>[src]

Bit 6 - Trigger interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>[src]

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn tg(&mut self) -> TG_W<'_>[src]

Bit 6 - Trigger generation

pub fn cc2g(&mut self) -> CC2G_W<'_>[src]

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc2m(&mut self) -> OC2M_W<'_>[src]

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>[src]

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>[src]

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic2f(&mut self) -> IC2F_W<'_>[src]

Bits 12:14 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>[src]

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>[src]

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:6 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc2np(&mut self) -> CC2NP_W<'_>[src]

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>[src]

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>[src]

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _CR1>>[src]

pub fn ckd(&mut self) -> CKD_W<'_>[src]

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

impl W<u32, Reg<u32, _DIER>>[src]

pub fn cc1ie(&mut self) -> CC1IE_W<'_>[src]

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn cc1of(&mut self) -> CC1OF_W<'_>[src]

Bit 9 - Capture/Compare 1 overcapture flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>[src]

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn cc1g(&mut self) -> CC1G_W<'_>[src]

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>[src]

pub fn oc1m(&mut self) -> OC1M_W<'_>[src]

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>[src]

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>[src]

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>[src]

pub fn ic1f(&mut self) -> IC1F_W<'_>[src]

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>[src]

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>[src]

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>[src]

pub fn cc1np(&mut self) -> CC1NP_W<'_>[src]

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>[src]

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>[src]

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ccr(&mut self) -> CCR_W<'_>[src]

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _SMCR>>[src]

pub fn sms3(&mut self) -> SMS3_W<'_>[src]

Bit 16 - Slave mode selection

pub fn etp(&mut self) -> ETP_W<'_>[src]

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>[src]

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>[src]

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>[src]

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>[src]

Bit 7 - Master/slave mode

pub fn ts(&mut self) -> TS_W<'_>[src]

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>[src]

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _OR>>[src]

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>[src]

Bits 0:1 - TIM11 Input 1 remapping capability

impl W<u32, Reg<u32, _CR1>>[src]

pub fn arpe(&mut self) -> ARPE_W<'_>[src]

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>[src]

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>[src]

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>[src]

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>[src]

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>[src]

pub fn mms(&mut self) -> MMS_W<'_>[src]

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>[src]

pub fn ude(&mut self) -> UDE_W<'_>[src]

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>[src]

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn uif(&mut self) -> UIF_W<'_>[src]

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>[src]

pub fn ug(&mut self) -> UG_W<'_>[src]

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>[src]

pub fn cnt(&mut self) -> CNT_W<'_>[src]

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>[src]

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _MACCR>>[src]

pub fn re(&mut self) -> RE_W<'_>[src]

Bit 2 - Receiver enable

pub fn te(&mut self) -> TE_W<'_>[src]

Bit 3 - Transmitter enable

pub fn dc(&mut self) -> DC_W<'_>[src]

Bit 4 - Deferral check

pub fn bl(&mut self) -> BL_W<'_>[src]

Bits 5:6 - Back-off limit

pub fn apcs(&mut self) -> APCS_W<'_>[src]

Bit 7 - Automatic pad/CRC stripping

pub fn rd(&mut self) -> RD_W<'_>[src]

Bit 9 - Retry disable

pub fn ipco(&mut self) -> IPCO_W<'_>[src]

Bit 10 - IPv4 checksum offload

pub fn dm(&mut self) -> DM_W<'_>[src]

Bit 11 - Duplex mode

pub fn lm(&mut self) -> LM_W<'_>[src]

Bit 12 - Loopback mode

pub fn rod(&mut self) -> ROD_W<'_>[src]

Bit 13 - Receive own disable

pub fn fes(&mut self) -> FES_W<'_>[src]

Bit 14 - Fast Ethernet speed

pub fn csd(&mut self) -> CSD_W<'_>[src]

Bit 16 - Carrier sense disable

pub fn ifg(&mut self) -> IFG_W<'_>[src]

Bits 17:19 - Interframe gap

pub fn jd(&mut self) -> JD_W<'_>[src]

Bit 22 - Jabber disable

pub fn wd(&mut self) -> WD_W<'_>[src]

Bit 23 - Watchdog disable

pub fn cstf(&mut self) -> CSTF_W<'_>[src]

Bit 25 - CRC stripping for type frames

impl W<u32, Reg<u32, _MACFFR>>[src]

pub fn pm(&mut self) -> PM_W<'_>[src]

Bit 0 - Promiscuous mode

pub fn hu(&mut self) -> HU_W<'_>[src]

Bit 1 - Hash unicast

pub fn hm(&mut self) -> HM_W<'_>[src]

Bit 2 - Hash multicast

pub fn daif(&mut self) -> DAIF_W<'_>[src]

Bit 3 - Destination address unique filtering

pub fn pam(&mut self) -> PAM_W<'_>[src]

Bit 4 - Pass all multicast

pub fn bfd(&mut self) -> BFD_W<'_>[src]

Bit 5 - Broadcast frames disable

pub fn pcf(&mut self) -> PCF_W<'_>[src]

Bits 6:7 - Pass control frames

pub fn saif(&mut self) -> SAIF_W<'_>[src]

Bit 7 - Source address inverse filtering

pub fn saf(&mut self) -> SAF_W<'_>[src]

Bit 8 - Source address filter

pub fn hpf(&mut self) -> HPF_W<'_>[src]

Bit 9 - Hash or perfect filter

pub fn ra(&mut self) -> RA_W<'_>[src]

Bit 31 - Receive all

impl W<u32, Reg<u32, _MACHTHR>>[src]

pub fn hth(&mut self) -> HTH_W<'_>[src]

Bits 0:31 - Upper 32 bits of hash table

impl W<u32, Reg<u32, _MACHTLR>>[src]

pub fn htl(&mut self) -> HTL_W<'_>[src]

Bits 0:31 - Lower 32 bits of hash table

impl W<u32, Reg<u32, _MACMIIAR>>[src]

pub fn mb(&mut self) -> MB_W<'_>[src]

Bit 0 - MII busy

pub fn mw(&mut self) -> MW_W<'_>[src]

Bit 1 - MII write

pub fn cr(&mut self) -> CR_W<'_>[src]

Bits 2:4 - Clock range

pub fn mr(&mut self) -> MR_W<'_>[src]

Bits 6:10 - MII register - select the desired MII register in the PHY device

pub fn pa(&mut self) -> PA_W<'_>[src]

Bits 11:15 - PHY address - select which of possible 32 PHYs is being accessed

impl W<u32, Reg<u32, _MACMIIDR>>[src]

pub fn md(&mut self) -> MD_W<'_>[src]

Bits 0:15 - MII data read from/written to the PHY

impl W<u32, Reg<u32, _MACFCR>>[src]

pub fn fcb(&mut self) -> FCB_W<'_>[src]

Bit 0 - Flow control busy/back pressure activate

pub fn tfce(&mut self) -> TFCE_W<'_>[src]

Bit 1 - Transmit flow control enable

pub fn rfce(&mut self) -> RFCE_W<'_>[src]

Bit 2 - Receive flow control enable

pub fn upfd(&mut self) -> UPFD_W<'_>[src]

Bit 3 - Unicast pause frame detect

pub fn plt(&mut self) -> PLT_W<'_>[src]

Bits 4:5 - Pause low threshold

pub fn zqpd(&mut self) -> ZQPD_W<'_>[src]

Bit 7 - Zero-quanta pause disable

pub fn pt(&mut self) -> PT_W<'_>[src]

Bits 16:31 - Pause time

impl W<u32, Reg<u32, _MACVLANTR>>[src]

pub fn vlanti(&mut self) -> VLANTI_W<'_>[src]

Bits 0:15 - VLAN tag identifier (for receive frames)

pub fn vlantc(&mut self) -> VLANTC_W<'_>[src]

Bit 16 - 12-bit VLAN tag comparison

impl W<u32, Reg<u32, _MACPMTCSR>>[src]

pub fn pd(&mut self) -> PD_W<'_>[src]

Bit 0 - Power down

pub fn mpe(&mut self) -> MPE_W<'_>[src]

Bit 1 - Magic packet enable

pub fn wfe(&mut self) -> WFE_W<'_>[src]

Bit 2 - Wakeup frame enable

pub fn mpr(&mut self) -> MPR_W<'_>[src]

Bit 5 - Magic packet received

pub fn wfr(&mut self) -> WFR_W<'_>[src]

Bit 6 - Wakeup frame received

pub fn gu(&mut self) -> GU_W<'_>[src]

Bit 9 - Global unicast

pub fn wffrpr(&mut self) -> WFFRPR_W<'_>[src]

Bit 31 - Wakeup frame filter register pointer reset

impl W<u32, Reg<u32, _MACSR>>[src]

pub fn tsts(&mut self) -> TSTS_W<'_>[src]

Bit 9 - Time stamp trigger status

impl W<u32, Reg<u32, _MACIMR>>[src]

pub fn pmtim(&mut self) -> PMTIM_W<'_>[src]

Bit 3 - PMT interrupt mask

pub fn tstim(&mut self) -> TSTIM_W<'_>[src]

Bit 9 - Time stamp trigger interrupt mask

impl W<u32, Reg<u32, _MACA0HR>>[src]

pub fn maca0h(&mut self) -> MACA0H_W<'_>[src]

Bits 0:15 - MAC address0 high

impl W<u32, Reg<u32, _MACA0LR>>[src]

pub fn maca0l(&mut self) -> MACA0L_W<'_>[src]

Bits 0:31 - 0

impl W<u32, Reg<u32, _MACA1HR>>[src]

pub fn maca1h(&mut self) -> MACA1H_W<'_>[src]

Bits 0:15 - MACA1H

pub fn mbc(&mut self) -> MBC_W<'_>[src]

Bits 24:29 - MBC

pub fn sa(&mut self) -> SA_W<'_>[src]

Bit 30 - SA

pub fn ae(&mut self) -> AE_W<'_>[src]

Bit 31 - AE

impl W<u32, Reg<u32, _MACA1LR>>[src]

pub fn maca1l(&mut self) -> MACA1L_W<'_>[src]

Bits 0:31 - MACA1LR

impl W<u32, Reg<u32, _MACA2HR>>[src]

pub fn maca2h(&mut self) -> MACA2H_W<'_>[src]

Bits 0:15 - MAC2AH

pub fn mbc(&mut self) -> MBC_W<'_>[src]

Bits 24:29 - MBC

pub fn sa(&mut self) -> SA_W<'_>[src]

Bit 30 - SA

pub fn ae(&mut self) -> AE_W<'_>[src]

Bit 31 - AE

impl W<u32, Reg<u32, _MACA2LR>>[src]

pub fn maca2l(&mut self) -> MACA2L_W<'_>[src]

Bits 0:31 - MACA2L

impl W<u32, Reg<u32, _MACA3HR>>[src]

pub fn maca3h(&mut self) -> MACA3H_W<'_>[src]

Bits 0:15 - MACA3H

pub fn mbc(&mut self) -> MBC_W<'_>[src]

Bits 24:29 - MBC

pub fn sa(&mut self) -> SA_W<'_>[src]

Bit 30 - SA

pub fn ae(&mut self) -> AE_W<'_>[src]

Bit 31 - AE

impl W<u32, Reg<u32, _MACA3LR>>[src]

pub fn maca3l(&mut self) -> MACA3L_W<'_>[src]

Bits 0:31 - MBCA3L

impl W<u32, Reg<u32, _DR>>[src]

pub fn dr(&mut self) -> DR_W<'_>[src]

Bits 0:31 - Data Register

impl W<u32, Reg<u32, _IDR>>[src]

pub fn idr(&mut self) -> IDR_W<'_>[src]

Bits 0:7 - Independent Data register

impl W<u32, Reg<u32, _CR>>[src]

pub fn reset(&mut self) -> RESET_W<'_>[src]

Bit 0 - RESET bit

pub fn rev_out(&mut self) -> REV_OUT_W<'_>[src]

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>[src]

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>[src]

Bits 3:4 - Polynomial size

impl W<u32, Reg<u32, _INIT>>[src]

pub fn init(&mut self) -> INIT_W<'_>[src]

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>[src]

pub fn pol(&mut self) -> POL_W<'_>[src]

Bits 0:31 - Programmable polynomial

impl W<u8, Reg<u8, _DR8>>[src]

pub fn dr8(&mut self) -> DR8_W<'_>[src]

Bits 0:7 - Data register bits

impl W<u16, Reg<u16, _DR16>>[src]

pub fn dr16(&mut self) -> DR16_W<'_>[src]

Bits 0:15 - Data register bits

impl W<u32, Reg<u32, _TIR>>[src]

pub fn stid(&mut self) -> STID_W<'_>[src]

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>[src]

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>[src]

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>[src]

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>[src]

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>[src]

pub fn time(&mut self) -> TIME_W<'_>[src]

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>[src]

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>[src]

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>[src]

pub fn data3(&mut self) -> DATA3_W<'_>[src]

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>[src]

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>[src]

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>[src]

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>[src]

pub fn data7(&mut self) -> DATA7_W<'_>[src]

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>[src]

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>[src]

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>[src]

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>[src]

pub fn fb(&mut self) -> FB_W<'_>[src]

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>[src]

pub fn fb(&mut self) -> FB_W<'_>[src]

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>[src]

pub fn dbf(&mut self) -> DBF_W<'_>[src]

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>[src]

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>[src]

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>[src]

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>[src]

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>[src]

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>[src]

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>[src]

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>[src]

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>[src]

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>[src]

pub fn slaki(&mut self) -> SLAKI_W<'_>[src]

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>[src]

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>[src]

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>[src]

pub fn abrq2(&mut self) -> ABRQ2_W<'_>[src]

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>[src]

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>[src]

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>[src]

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>[src]

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>[src]

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>[src]

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>[src]

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>[src]

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>[src]

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>[src]

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>[src]

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>[src]

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>[src]

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>[src]

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>[src]

pub fn rfom(&mut self) -> RFOM_W<'_>[src]

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>[src]

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>[src]

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>[src]

pub fn slkie(&mut self) -> SLKIE_W<'_>[src]

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>[src]

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>[src]

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>[src]

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>[src]

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>[src]

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>[src]

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>[src]

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>[src]

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>[src]

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>[src]

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>[src]

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>[src]

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>[src]

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>[src]

pub fn lec(&mut self) -> LEC_W<'_>[src]

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>[src]

pub fn silm(&mut self) -> SILM_W<'_>[src]

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>[src]

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>[src]

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>[src]

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>[src]

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>[src]

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>[src]

pub fn can2sb(&mut self) -> CAN2SB_W<'_>[src]

Bits 8:13 - CAN2SB

pub fn finit(&mut self) -> FINIT_W<'_>[src]

Bit 0 - FINIT

impl W<u32, Reg<u32, _FM1R>>[src]

pub fn fbm0(&mut self) -> FBM0_W<'_>[src]

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>[src]

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>[src]

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>[src]

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>[src]

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>[src]

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>[src]

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>[src]

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>[src]

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>[src]

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>[src]

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>[src]

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>[src]

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>[src]

Bit 13 - Filter mode

pub fn fbm14(&mut self) -> FBM14_W<'_>[src]

Bit 14 - Filter mode

pub fn fbm15(&mut self) -> FBM15_W<'_>[src]

Bit 15 - Filter mode

pub fn fbm16(&mut self) -> FBM16_W<'_>[src]

Bit 16 - Filter mode

pub fn fbm17(&mut self) -> FBM17_W<'_>[src]

Bit 17 - Filter mode

pub fn fbm18(&mut self) -> FBM18_W<'_>[src]

Bit 18 - Filter mode

pub fn fbm19(&mut self) -> FBM19_W<'_>[src]

Bit 19 - Filter mode

pub fn fbm20(&mut self) -> FBM20_W<'_>[src]

Bit 20 - Filter mode

pub fn fbm21(&mut self) -> FBM21_W<'_>[src]

Bit 21 - Filter mode

pub fn fbm22(&mut self) -> FBM22_W<'_>[src]

Bit 22 - Filter mode

pub fn fbm23(&mut self) -> FBM23_W<'_>[src]

Bit 23 - Filter mode

pub fn fbm24(&mut self) -> FBM24_W<'_>[src]

Bit 24 - Filter mode

pub fn fbm25(&mut self) -> FBM25_W<'_>[src]

Bit 25 - Filter mode

pub fn fbm26(&mut self) -> FBM26_W<'_>[src]

Bit 26 - Filter mode

pub fn fbm27(&mut self) -> FBM27_W<'_>[src]

Bit 27 - Filter mode

impl W<u32, Reg<u32, _FS1R>>[src]

pub fn fsc0(&mut self) -> FSC0_W<'_>[src]

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>[src]

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>[src]

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>[src]

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>[src]

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>[src]

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>[src]

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>[src]

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>[src]

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>[src]

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>[src]

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>[src]

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>[src]

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>[src]

Bit 13 - Filter scale configuration

pub fn fsc14(&mut self) -> FSC14_W<'_>[src]

Bit 14 - Filter scale configuration

pub fn fsc15(&mut self) -> FSC15_W<'_>[src]

Bit 15 - Filter scale configuration

pub fn fsc16(&mut self) -> FSC16_W<'_>[src]

Bit 16 - Filter scale configuration

pub fn fsc17(&mut self) -> FSC17_W<'_>[src]

Bit 17 - Filter scale configuration

pub fn fsc18(&mut self) -> FSC18_W<'_>[src]

Bit 18 - Filter scale configuration

pub fn fsc19(&mut self) -> FSC19_W<'_>[src]

Bit 19 - Filter scale configuration

pub fn fsc20(&mut self) -> FSC20_W<'_>[src]

Bit 20 - Filter scale configuration

pub fn fsc21(&mut self) -> FSC21_W<'_>[src]

Bit 21 - Filter scale configuration

pub fn fsc22(&mut self) -> FSC22_W<'_>[src]

Bit 22 - Filter scale configuration

pub fn fsc23(&mut self) -> FSC23_W<'_>[src]

Bit 23 - Filter scale configuration

pub fn fsc24(&mut self) -> FSC24_W<'_>[src]

Bit 24 - Filter scale configuration

pub fn fsc25(&mut self) -> FSC25_W<'_>[src]

Bit 25 - Filter scale configuration

pub fn fsc26(&mut self) -> FSC26_W<'_>[src]

Bit 26 - Filter scale configuration

pub fn fsc27(&mut self) -> FSC27_W<'_>[src]

Bit 27 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>[src]

pub fn ffa0(&mut self) -> FFA0_W<'_>[src]

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>[src]

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>[src]

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>[src]

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>[src]

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>[src]

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>[src]

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>[src]

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>[src]

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>[src]

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>[src]

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>[src]

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>[src]

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>[src]

Bit 13 - Filter FIFO assignment for filter 13

pub fn ffa14(&mut self) -> FFA14_W<'_>[src]

Bit 14 - Filter FIFO assignment for filter 14

pub fn ffa15(&mut self) -> FFA15_W<'_>[src]

Bit 15 - Filter FIFO assignment for filter 15

pub fn ffa16(&mut self) -> FFA16_W<'_>[src]

Bit 16 - Filter FIFO assignment for filter 16

pub fn ffa17(&mut self) -> FFA17_W<'_>[src]

Bit 17 - Filter FIFO assignment for filter 17

pub fn ffa18(&mut self) -> FFA18_W<'_>[src]

Bit 18 - Filter FIFO assignment for filter 18

pub fn ffa19(&mut self) -> FFA19_W<'_>[src]

Bit 19 - Filter FIFO assignment for filter 19

pub fn ffa20(&mut self) -> FFA20_W<'_>[src]

Bit 20 - Filter FIFO assignment for filter 20

pub fn ffa21(&mut self) -> FFA21_W<'_>[src]

Bit 21 - Filter FIFO assignment for filter 21

pub fn ffa22(&mut self) -> FFA22_W<'_>[src]

Bit 22 - Filter FIFO assignment for filter 22

pub fn ffa23(&mut self) -> FFA23_W<'_>[src]

Bit 23 - Filter FIFO assignment for filter 23

pub fn ffa24(&mut self) -> FFA24_W<'_>[src]

Bit 24 - Filter FIFO assignment for filter 24

pub fn ffa25(&mut self) -> FFA25_W<'_>[src]

Bit 25 - Filter FIFO assignment for filter 25

pub fn ffa26(&mut self) -> FFA26_W<'_>[src]

Bit 26 - Filter FIFO assignment for filter 26

pub fn ffa27(&mut self) -> FFA27_W<'_>[src]

Bit 27 - Filter FIFO assignment for filter 27

impl W<u32, Reg<u32, _FA1R>>[src]

pub fn fact0(&mut self) -> FACT0_W<'_>[src]

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>[src]

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>[src]

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>[src]

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>[src]

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>[src]

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>[src]

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>[src]

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>[src]

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>[src]

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>[src]

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>[src]

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>[src]

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>[src]

Bit 13 - Filter active

pub fn fact14(&mut self) -> FACT14_W<'_>[src]

Bit 14 - Filter active

pub fn fact15(&mut self) -> FACT15_W<'_>[src]

Bit 15 - Filter active

pub fn fact16(&mut self) -> FACT16_W<'_>[src]

Bit 16 - Filter active

pub fn fact17(&mut self) -> FACT17_W<'_>[src]

Bit 17 - Filter active

pub fn fact18(&mut self) -> FACT18_W<'_>[src]

Bit 18 - Filter active

pub fn fact19(&mut self) -> FACT19_W<'_>[src]

Bit 19 - Filter active

pub fn fact20(&mut self) -> FACT20_W<'_>[src]

Bit 20 - Filter active

pub fn fact21(&mut self) -> FACT21_W<'_>[src]

Bit 21 - Filter active

pub fn fact22(&mut self) -> FACT22_W<'_>[src]

Bit 22 - Filter active

pub fn fact23(&mut self) -> FACT23_W<'_>[src]

Bit 23 - Filter active

pub fn fact24(&mut self) -> FACT24_W<'_>[src]

Bit 24 - Filter active

pub fn fact25(&mut self) -> FACT25_W<'_>[src]

Bit 25 - Filter active

pub fn fact26(&mut self) -> FACT26_W<'_>[src]

Bit 26 - Filter active

pub fn fact27(&mut self) -> FACT27_W<'_>[src]

Bit 27 - Filter active

impl W<u32, Reg<u32, _ACR>>[src]

pub fn latency(&mut self) -> LATENCY_W<'_>[src]

Bits 0:3 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>[src]

Bit 8 - Prefetch enable

pub fn arten(&mut self) -> ARTEN_W<'_>[src]

Bit 9 - ART Accelerator Enable

pub fn artrst(&mut self) -> ARTRST_W<'_>[src]

Bit 11 - ART Accelerator reset

impl W<u32, Reg<u32, _KEYR>>[src]

pub fn key(&mut self) -> KEY_W<'_>[src]

Bits 0:31 - FPEC key

impl W<u32, Reg<u32, _OPTKEYR>>[src]

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>[src]

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>[src]

pub fn eop(&mut self) -> EOP_W<'_>[src]

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>[src]

Bit 1 - Operation error

pub fn wrperr(&mut self) -> WRPERR_W<'_>[src]

Bit 4 - Write protection error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>[src]

Bit 5 - Programming alignment error

pub fn pgperr(&mut self) -> PGPERR_W<'_>[src]

Bit 6 - Programming parallelism error

pub fn erserr(&mut self) -> ERSERR_W<'_>[src]

Bit 7 - Programming sequence error

impl W<u32, Reg<u32, _CR>>[src]

pub fn pg(&mut self) -> PG_W<'_>[src]

Bit 0 - Programming

pub fn ser(&mut self) -> SER_W<'_>[src]

Bit 1 - Sector Erase

pub fn mer1(&mut self) -> MER1_W<'_>[src]

Bit 2 - Mass Erase of sectors 0 to 11

pub fn snb(&mut self) -> SNB_W<'_>[src]

Bits 3:7 - Sector number

pub fn psize(&mut self) -> PSIZE_W<'_>[src]

Bits 8:9 - Program size

pub fn mer2(&mut self) -> MER2_W<'_>[src]

Bit 15 - Mass Erase of sectors 12 to 23

pub fn strt(&mut self) -> STRT_W<'_>[src]

Bit 16 - Start

pub fn eopie(&mut self) -> EOPIE_W<'_>[src]

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>[src]

Bit 25 - Error interrupt enable

pub fn lock(&mut self) -> LOCK_W<'_>[src]

Bit 31 - Lock

impl W<u32, Reg<u32, _OPTCR>>[src]

pub fn optlock(&mut self) -> OPTLOCK_W<'_>[src]

Bit 0 - Option lock

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>[src]

Bit 1 - Option start

pub fn bor_lev(&mut self) -> BOR_LEV_W<'_>[src]

Bits 2:3 - BOR reset Level

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>[src]

Bit 4 - User option bytes

pub fn iwdg_sw(&mut self) -> IWDG_SW_W<'_>[src]

Bit 5 - User option bytes

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>[src]

Bit 6 - User option bytes

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>[src]

Bit 7 - User option bytes

pub fn rdp(&mut self) -> RDP_W<'_>[src]

Bits 8:15 - Read protect

pub fn n_wrp(&mut self) -> NWRP_W<'_>[src]

Bits 16:27 - Not write protect

pub fn n_dboot(&mut self) -> NDBOOT_W<'_>[src]

Bit 28 - Dual Boot mode (valid only when nDBANK=0)

pub fn n_dbank(&mut self) -> NDBANK_W<'_>[src]

Bit 29 - Not dual bank mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>[src]

Bit 30 - Independent watchdog counter freeze in standby mode

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>[src]

Bit 31 - Independent watchdog counter freeze in Stop mode

impl W<u32, Reg<u32, _OPTCR1>>[src]

pub fn boot_add0(&mut self) -> BOOT_ADD0_W<'_>[src]

Bits 0:15 - Boot base address when Boot pin =0

pub fn boot_add1(&mut self) -> BOOT_ADD1_W<'_>[src]

Bits 16:31 - Boot base address when Boot pin =1

impl W<u32, Reg<u32, _IMR>>[src]

pub fn mr0(&mut self) -> MR0_W<'_>[src]

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>[src]

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>[src]

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>[src]

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>[src]

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>[src]

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>[src]

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>[src]

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>[src]

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>[src]

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>[src]

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>[src]

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>[src]

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>[src]

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>[src]

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>[src]

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>[src]

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>[src]

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>[src]

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>[src]

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>[src]

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>[src]

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>[src]

Bit 22 - Interrupt Mask on line 22

impl W<u32, Reg<u32, _EMR>>[src]

pub fn mr0(&mut self) -> MR0_W<'_>[src]

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>[src]

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>[src]

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>[src]

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>[src]

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>[src]

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>[src]

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>[src]

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>[src]

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>[src]

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>[src]

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>[src]

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>[src]

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>[src]

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>[src]

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>[src]

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>[src]

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>[src]

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>[src]

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>[src]

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>[src]

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>[src]

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>[src]

Bit 22 - Event Mask on line 22

impl W<u32, Reg<u32, _RTSR>>[src]

pub fn tr0(&mut self) -> TR0_W<'_>[src]

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>[src]

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>[src]

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>[src]

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>[src]

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>[src]

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>[src]

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>[src]

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>[src]

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>[src]

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>[src]

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>[src]

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>[src]

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>[src]

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>[src]

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>[src]

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>[src]

Bit 16 - Rising trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>[src]

Bit 17 - Rising trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>[src]

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>[src]

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>[src]

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>[src]

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>[src]

Bit 22 - Rising trigger event configuration of line 22

impl W<u32, Reg<u32, _FTSR>>[src]

pub fn tr0(&mut self) -> TR0_W<'_>[src]

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>[src]

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>[src]

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>[src]

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>[src]

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>[src]

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>[src]

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>[src]

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>[src]

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>[src]

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>[src]

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>[src]

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>[src]

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>[src]

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>[src]

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>[src]

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>[src]

Bit 16 - Falling trigger event configuration of line 16

pub fn tr17(&mut self) -> TR17_W<'_>[src]

Bit 17 - Falling trigger event configuration of line 17

pub fn tr18(&mut self) -> TR18_W<'_>[src]

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>[src]

Bit 19 - Falling trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>[src]

Bit 20 - Falling trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>[src]

Bit 21 - Falling trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>[src]

Bit 22 - Falling trigger event configuration of line 22

impl W<u32, Reg<u32, _SWIER>>[src]

pub fn swier0(&mut self) -> SWIER0_W<'_>[src]

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>[src]

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>[src]

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>[src]

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>[src]

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>[src]

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>[src]

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>[src]

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>[src]

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>[src]

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>[src]

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>[src]

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>[src]

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>[src]

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>[src]

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>[src]

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>[src]

Bit 16 - Software Interrupt on line 16

pub fn swier17(&mut self) -> SWIER17_W<'_>[src]

Bit 17 - Software Interrupt on line 17

pub fn swier18(&mut self) -> SWIER18_W<'_>[src]

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>[src]

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>[src]

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>[src]

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>[src]

Bit 22 - Software Interrupt on line 22

impl W<u32, Reg<u32, _PR>>[src]

pub fn pr0(&mut self) -> PR0_W<'_>[src]

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>[src]

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>[src]

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>[src]

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>[src]

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>[src]

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>[src]

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>[src]

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>[src]

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>[src]

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>[src]

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>[src]

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>[src]

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>[src]

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>[src]

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>[src]

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>[src]

Bit 16 - Pending bit 16

pub fn pr17(&mut self) -> PR17_W<'_>[src]

Bit 17 - Pending bit 17

pub fn pr18(&mut self) -> PR18_W<'_>[src]

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>[src]

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>[src]

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>[src]

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>[src]

Bit 22 - Pending bit 22

impl W<u32, Reg<u32, _CR>>[src]

pub fn cluten(&mut self) -> CLUTEN_W<'_>[src]

Bit 4 - Color Look-Up Table Enable

pub fn colken(&mut self) -> COLKEN_W<'_>[src]

Bit 1 - Color Keying Enable

pub fn len(&mut self) -> LEN_W<'_>[src]

Bit 0 - Layer Enable

impl W<u32, Reg<u32, _WHPCR>>[src]

pub fn whsppos(&mut self) -> WHSPPOS_W<'_>[src]

Bits 16:27 - Window Horizontal Stop Position

pub fn whstpos(&mut self) -> WHSTPOS_W<'_>[src]

Bits 0:11 - Window Horizontal Start Position

impl W<u32, Reg<u32, _WVPCR>>[src]

pub fn wvsppos(&mut self) -> WVSPPOS_W<'_>[src]

Bits 16:26 - Window Vertical Stop Position

pub fn wvstpos(&mut self) -> WVSTPOS_W<'_>[src]

Bits 0:10 - Window Vertical Start Position

impl W<u32, Reg<u32, _CKCR>>[src]

pub fn ckred(&mut self) -> CKRED_W<'_>[src]

Bits 16:23 - Color Key Red value

pub fn ckgreen(&mut self) -> CKGREEN_W<'_>[src]

Bits 8:15 - Color Key Green value

pub fn ckblue(&mut self) -> CKBLUE_W<'_>[src]

Bits 0:7 - Color Key Blue value

impl W<u32, Reg<u32, _PFCR>>[src]

pub fn pf(&mut self) -> PF_W<'_>[src]

Bits 0:2 - Pixel Format

impl W<u32, Reg<u32, _CACR>>[src]

pub fn consta(&mut self) -> CONSTA_W<'_>[src]

Bits 0:7 - Constant Alpha

impl W<u32, Reg<u32, _DCCR>>[src]

pub fn dcalpha(&mut self) -> DCALPHA_W<'_>[src]

Bits 24:31 - Default Color Alpha

pub fn dcred(&mut self) -> DCRED_W<'_>[src]

Bits 16:23 - Default Color Red

pub fn dcgreen(&mut self) -> DCGREEN_W<'_>[src]

Bits 8:15 - Default Color Green

pub fn dcblue(&mut self) -> DCBLUE_W<'_>[src]

Bits 0:7 - Default Color Blue

impl W<u32, Reg<u32, _BFCR>>[src]

pub fn bf1(&mut self) -> BF1_W<'_>[src]

Bits 8:10 - Blending Factor 1

pub fn bf2(&mut self) -> BF2_W<'_>[src]

Bits 0:2 - Blending Factor 2

impl W<u32, Reg<u32, _CFBAR>>[src]

pub fn cfbadd(&mut self) -> CFBADD_W<'_>[src]

Bits 0:31 - Color Frame Buffer Start Address

impl W<u32, Reg<u32, _CFBLR>>[src]

pub fn cfbp(&mut self) -> CFBP_W<'_>[src]

Bits 16:28 - Color Frame Buffer Pitch in bytes

pub fn cfbll(&mut self) -> CFBLL_W<'_>[src]

Bits 0:12 - Color Frame Buffer Line Length

impl W<u32, Reg<u32, _CFBLNR>>[src]

pub fn cfblnbr(&mut self) -> CFBLNBR_W<'_>[src]

Bits 0:10 - Frame Buffer Line Number

impl W<u32, Reg<u32, _CLUTWR>>[src]

pub fn clutadd(&mut self) -> CLUTADD_W<'_>[src]

Bits 24:31 - CLUT Address

pub fn red(&mut self) -> RED_W<'_>[src]

Bits 16:23 - Red value

pub fn green(&mut self) -> GREEN_W<'_>[src]

Bits 8:15 - Green value

pub fn blue(&mut self) -> BLUE_W<'_>[src]

Bits 0:7 - Blue value

impl W<u32, Reg<u32, _SSCR>>[src]

pub fn hsw(&mut self) -> HSW_W<'_>[src]

Bits 16:27 - Horizontal Synchronization Width (in units of pixel clock period)

pub fn vsh(&mut self) -> VSH_W<'_>[src]

Bits 0:10 - Vertical Synchronization Height (in units of horizontal scan line)

impl W<u32, Reg<u32, _BPCR>>[src]

pub fn ahbp(&mut self) -> AHBP_W<'_>[src]

Bits 16:27 - Accumulated Horizontal back porch (in units of pixel clock period)

pub fn avbp(&mut self) -> AVBP_W<'_>[src]

Bits 0:10 - Accumulated Vertical back porch (in units of horizontal scan line)

impl W<u32, Reg<u32, _AWCR>>[src]

pub fn aaw(&mut self) -> AAW_W<'_>[src]

Bits 16:27 - Accumulated Active Width (in units of pixel clock period)

pub fn aah(&mut self) -> AAH_W<'_>[src]

Bits 0:10 - Accumulated Active Height (in units of horizontal scan line)

impl W<u32, Reg<u32, _TWCR>>[src]

pub fn totalw(&mut self) -> TOTALW_W<'_>[src]

Bits 16:27 - Total Width (in units of pixel clock period)

pub fn totalh(&mut self) -> TOTALH_W<'_>[src]

Bits 0:10 - Total Height (in units of horizontal scan line)

impl W<u32, Reg<u32, _GCR>>[src]

pub fn hspol(&mut self) -> HSPOL_W<'_>[src]

Bit 31 - Horizontal Synchronization Polarity

pub fn vspol(&mut self) -> VSPOL_W<'_>[src]

Bit 30 - Vertical Synchronization Polarity

pub fn depol(&mut self) -> DEPOL_W<'_>[src]

Bit 29 - Data Enable Polarity

pub fn pcpol(&mut self) -> PCPOL_W<'_>[src]

Bit 28 - Pixel Clock Polarity

pub fn den(&mut self) -> DEN_W<'_>[src]

Bit 16 - Dither Enable

pub fn ltdcen(&mut self) -> LTDCEN_W<'_>[src]

Bit 0 - LCD-TFT controller enable bit

impl W<u32, Reg<u32, _SRCR>>[src]

pub fn vbr(&mut self) -> VBR_W<'_>[src]

Bit 1 - Vertical Blanking Reload

pub fn imr(&mut self) -> IMR_W<'_>[src]

Bit 0 - Immediate Reload

impl W<u32, Reg<u32, _BCCR>>[src]

pub fn bcblue(&mut self) -> BCBLUE_W<'_>[src]

Bits 0:7 - Background color blue value

pub fn bcgreen(&mut self) -> BCGREEN_W<'_>[src]

Bits 8:15 - Background color green value

pub fn bcred(&mut self) -> BCRED_W<'_>[src]

Bits 16:23 - Background color red value

impl W<u32, Reg<u32, _IER>>[src]

pub fn rrie(&mut self) -> RRIE_W<'_>[src]

Bit 3 - Register Reload interrupt enable

pub fn terrie(&mut self) -> TERRIE_W<'_>[src]

Bit 2 - Transfer Error Interrupt Enable

pub fn fuie(&mut self) -> FUIE_W<'_>[src]

Bit 1 - FIFO Underrun Interrupt Enable

pub fn lie(&mut self) -> LIE_W<'_>[src]

Bit 0 - Line Interrupt Enable

impl W<u32, Reg<u32, _ICR>>[src]

pub fn crrif(&mut self) -> CRRIF_W<'_>[src]

Bit 3 - Clears Register Reload Interrupt Flag

pub fn cterrif(&mut self) -> CTERRIF_W<'_>[src]

Bit 2 - Clears the Transfer Error Interrupt Flag

pub fn cfuif(&mut self) -> CFUIF_W<'_>[src]

Bit 1 - Clears the FIFO Underrun Interrupt flag

pub fn clif(&mut self) -> CLIF_W<'_>[src]

Bit 0 - Clears the Line Interrupt Flag

impl W<u32, Reg<u32, _LIPCR>>[src]

pub fn lipos(&mut self) -> LIPOS_W<'_>[src]

Bits 0:10 - Line Interrupt Position

impl W<u32, Reg<u32, _CR1>>[src]

pub fn mckdiv(&mut self) -> MCKDIV_W<'_>[src]

Bits 20:23 - Master clock divider

pub fn nodiv(&mut self) -> NODIV_W<'_>[src]

Bit 19 - No divider

pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]

Bit 17 - DMA enable

pub fn saien(&mut self) -> SAIEN_W<'_>[src]

Bit 16 - Audio block A enable

pub fn outdriv(&mut self) -> OUTDRIV_W<'_>[src]

Bit 13 - Output drive

pub fn mono(&mut self) -> MONO_W<'_>[src]

Bit 12 - Mono mode

pub fn syncen(&mut self) -> SYNCEN_W<'_>[src]

Bits 10:11 - Synchronization enable

pub fn ckstr(&mut self) -> CKSTR_W<'_>[src]

Bit 9 - Clock strobing edge

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>[src]

Bit 8 - Least significant bit first

pub fn ds(&mut self) -> DS_W<'_>[src]

Bits 5:7 - Data size

pub fn prtcfg(&mut self) -> PRTCFG_W<'_>[src]

Bits 2:3 - Protocol configuration

pub fn mode(&mut self) -> MODE_W<'_>[src]

Bits 0:1 - Audio block mode

impl W<u32, Reg<u32, _CR2>>[src]

pub fn comp(&mut self) -> COMP_W<'_>[src]

Bits 14:15 - Companding mode

pub fn cpl(&mut self) -> CPL_W<'_>[src]

Bit 13 - Complement bit

pub fn mutecn(&mut self) -> MUTECN_W<'_>[src]

Bits 7:12 - Mute counter

pub fn muteval(&mut self) -> MUTEVAL_W<'_>[src]

Bit 6 - Mute value

pub fn mute(&mut self) -> MUTE_W<'_>[src]

Bit 5 - Mute

pub fn tris(&mut self) -> TRIS_W<'_>[src]

Bit 4 - Tristate management on data line

pub fn fflush(&mut self) -> FFLUSH_W<'_>[src]

Bit 3 - FIFO flush

pub fn fth(&mut self) -> FTH_W<'_>[src]

Bits 0:2 - FIFO threshold

impl W<u32, Reg<u32, _FRCR>>[src]

pub fn fsoff(&mut self) -> FSOFF_W<'_>[src]

Bit 18 - Frame synchronization offset

pub fn fspol(&mut self) -> FSPOL_W<'_>[src]

Bit 17 - Frame synchronization polarity

pub fn fsdef(&mut self) -> FSDEF_W<'_>[src]

Bit 16 - Frame synchronization definition

pub fn fsall(&mut self) -> FSALL_W<'_>[src]

Bits 8:14 - Frame synchronization active level length

pub fn frl(&mut self) -> FRL_W<'_>[src]

Bits 0:7 - Frame length

impl W<u32, Reg<u32, _SLOTR>>[src]

pub fn sloten(&mut self) -> SLOTEN_W<'_>[src]

Bits 16:31 - Slot enable

pub fn nbslot(&mut self) -> NBSLOT_W<'_>[src]

Bits 8:11 - Number of slots in an audio frame

pub fn slotsz(&mut self) -> SLOTSZ_W<'_>[src]

Bits 6:7 - Slot size

pub fn fboff(&mut self) -> FBOFF_W<'_>[src]

Bits 0:4 - First bit offset

impl W<u32, Reg<u32, _IM>>[src]

pub fn lfsdetie(&mut self) -> LFSDETIE_W<'_>[src]

Bit 6 - Late frame synchronization detection interrupt enable

pub fn afsdetie(&mut self) -> AFSDETIE_W<'_>[src]

Bit 5 - Anticipated frame synchronization detection interrupt enable

pub fn cnrdyie(&mut self) -> CNRDYIE_W<'_>[src]

Bit 4 - Codec not ready interrupt enable

pub fn freqie(&mut self) -> FREQIE_W<'_>[src]

Bit 3 - FIFO request interrupt enable

pub fn wckcfgie(&mut self) -> WCKCFGIE_W<'_>[src]

Bit 2 - Wrong clock configuration interrupt enable

pub fn mutedetie(&mut self) -> MUTEDETIE_W<'_>[src]

Bit 1 - Mute detection interrupt enable

pub fn ovrudrie(&mut self) -> OVRUDRIE_W<'_>[src]

Bit 0 - Overrun/underrun interrupt enable

impl W<u32, Reg<u32, _SR>>[src]

pub fn flvl(&mut self) -> FLVL_W<'_>[src]

Bits 16:18 - FIFO level threshold

pub fn lfsdet(&mut self) -> LFSDET_W<'_>[src]

Bit 6 - Late frame synchronization detection

pub fn afsdet(&mut self) -> AFSDET_W<'_>[src]

Bit 5 - Anticipated frame synchronization detection

pub fn cnrdy(&mut self) -> CNRDY_W<'_>[src]

Bit 4 - Codec not ready

pub fn freq(&mut self) -> FREQ_W<'_>[src]

Bit 3 - FIFO request

pub fn wckcfg(&mut self) -> WCKCFG_W<'_>[src]

Bit 2 - Wrong clock configuration flag. This bit is read only.

pub fn mutedet(&mut self) -> MUTEDET_W<'_>[src]

Bit 1 - Mute detection

pub fn ovrudr(&mut self) -> OVRUDR_W<'_>[src]

Bit 0 - Overrun / underrun

impl W<u32, Reg<u32, _CLRFR>>[src]

pub fn clfsdet(&mut self) -> CLFSDET_W<'_>[src]

Bit 6 - Clear late frame synchronization detection flag

pub fn cafsdet(&mut self) -> CAFSDET_W<'_>[src]

Bit 5 - Clear anticipated frame synchronization detection flag.

pub fn ccnrdy(&mut self) -> CCNRDY_W<'_>[src]

Bit 4 - Clear codec not ready flag

pub fn cwckcfg(&mut self) -> CWCKCFG_W<'_>[src]

Bit 2 - Clear wrong clock configuration flag

pub fn cmutedet(&mut self) -> CMUTEDET_W<'_>[src]

Bit 1 - Mute detection flag

pub fn covrudr(&mut self) -> COVRUDR_W<'_>[src]

Bit 0 - Clear overrun / underrun

impl W<u32, Reg<u32, _DR>>[src]

pub fn data(&mut self) -> DATA_W<'_>[src]

Bits 0:31 - Data

impl W<u32, Reg<u32, _GCR>>[src]

pub fn syncin(&mut self) -> SYNCIN_W<'_>[src]

Bits 0:1 - Synchronization inputs

pub fn syncout(&mut self) -> SYNCOUT_W<'_>[src]

Bits 4:5 - Synchronization outputs

impl W<u32, Reg<u32, _CR>>[src]

pub fn mode(&mut self) -> MODE_W<'_>[src]

Bits 16:17 - DMA2D mode

pub fn ceie(&mut self) -> CEIE_W<'_>[src]

Bit 13 - Configuration Error Interrupt Enable

pub fn ctcie(&mut self) -> CTCIE_W<'_>[src]

Bit 12 - CLUT transfer complete interrupt enable

pub fn caeie(&mut self) -> CAEIE_W<'_>[src]

Bit 11 - CLUT access error interrupt enable

pub fn twie(&mut self) -> TWIE_W<'_>[src]

Bit 10 - Transfer watermark interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>[src]

Bit 9 - Transfer complete interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>[src]

Bit 8 - Transfer error interrupt enable

pub fn abort(&mut self) -> ABORT_W<'_>[src]

Bit 2 - Abort

pub fn susp(&mut self) -> SUSP_W<'_>[src]

Bit 1 - Suspend

pub fn start(&mut self) -> START_W<'_>[src]

Bit 0 - Start

impl W<u32, Reg<u32, _IFCR>>[src]

pub fn cceif(&mut self) -> CCEIF_W<'_>[src]

Bit 5 - Clear configuration error interrupt flag

pub fn cctcif(&mut self) -> CCTCIF_W<'_>[src]

Bit 4 - Clear CLUT transfer complete interrupt flag

pub fn caecif(&mut self) -> CAECIF_W<'_>[src]

Bit 3 - Clear CLUT access error interrupt flag

pub fn ctwif(&mut self) -> CTWIF_W<'_>[src]

Bit 2 - Clear transfer watermark interrupt flag

pub fn ctcif(&mut self) -> CTCIF_W<'_>[src]

Bit 1 - Clear transfer complete interrupt flag

pub fn cteif(&mut self) -> CTEIF_W<'_>[src]

Bit 0 - Clear Transfer error interrupt flag

impl W<u32, Reg<u32, _FGMAR>>[src]

pub fn ma(&mut self) -> MA_W<'_>[src]

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _FGOR>>[src]

pub fn lo(&mut self) -> LO_W<'_>[src]

Bits 0:13 - Line offset

impl W<u32, Reg<u32, _BGMAR>>[src]

pub fn ma(&mut self) -> MA_W<'_>[src]

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _BGOR>>[src]

pub fn lo(&mut self) -> LO_W<'_>[src]

Bits 0:13 - Line offset

impl W<u32, Reg<u32, _FGPFCCR>>[src]

pub fn alpha(&mut self) -> ALPHA_W<'_>[src]

Bits 24:31 - Alpha value

pub fn am(&mut self) -> AM_W<'_>[src]

Bits 16:17 - Alpha mode

pub fn cs(&mut self) -> CS_W<'_>[src]

Bits 8:15 - CLUT size

pub fn start(&mut self) -> START_W<'_>[src]

Bit 5 - Start

pub fn ccm(&mut self) -> CCM_W<'_>[src]

Bit 4 - CLUT color mode

pub fn cm(&mut self) -> CM_W<'_>[src]

Bits 0:3 - Color mode

impl W<u32, Reg<u32, _FGCOLR>>[src]

pub fn red(&mut self) -> RED_W<'_>[src]

Bits 16:23 - Red Value

pub fn green(&mut self) -> GREEN_W<'_>[src]

Bits 8:15 - Green Value

pub fn blue(&mut self) -> BLUE_W<'_>[src]

Bits 0:7 - Blue Value

impl W<u32, Reg<u32, _BGPFCCR>>[src]

pub fn alpha(&mut self) -> ALPHA_W<'_>[src]

Bits 24:31 - Alpha value

pub fn am(&mut self) -> AM_W<'_>[src]

Bits 16:17 - Alpha mode

pub fn cs(&mut self) -> CS_W<'_>[src]

Bits 8:15 - CLUT size

pub fn start(&mut self) -> START_W<'_>[src]

Bit 5 - Start

pub fn ccm(&mut self) -> CCM_W<'_>[src]

Bit 4 - CLUT Color mode

pub fn cm(&mut self) -> CM_W<'_>[src]

Bits 0:3 - Color mode

impl W<u32, Reg<u32, _BGCOLR>>[src]

pub fn red(&mut self) -> RED_W<'_>[src]

Bits 16:23 - Red Value

pub fn green(&mut self) -> GREEN_W<'_>[src]

Bits 8:15 - Green Value

pub fn blue(&mut self) -> BLUE_W<'_>[src]

Bits 0:7 - Blue Value

impl W<u32, Reg<u32, _FGCMAR>>[src]

pub fn ma(&mut self) -> MA_W<'_>[src]

Bits 0:31 - Memory Address

impl W<u32, Reg<u32, _BGCMAR>>[src]

pub fn ma(&mut self) -> MA_W<'_>[src]

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _OPFCCR>>[src]

pub fn cm(&mut self) -> CM_W<'_>[src]

Bits 0:2 - Color mode

impl W<u32, Reg<u32, _OCOLR>>[src]

pub fn aplha(&mut self) -> APLHA_W<'_>[src]

Bits 24:31 - Alpha Channel Value

pub fn red(&mut self) -> RED_W<'_>[src]

Bits 16:23 - Red Value

pub fn green(&mut self) -> GREEN_W<'_>[src]

Bits 8:15 - Green Value

pub fn blue(&mut self) -> BLUE_W<'_>[src]

Bits 0:7 - Blue Value

impl W<u32, Reg<u32, _OMAR>>[src]

pub fn ma(&mut self) -> MA_W<'_>[src]

Bits 0:31 - Memory Address

impl W<u32, Reg<u32, _OOR>>[src]

pub fn lo(&mut self) -> LO_W<'_>[src]

Bits 0:13 - Line Offset

impl W<u32, Reg<u32, _NLR>>[src]

pub fn pl(&mut self) -> PL_W<'_>[src]

Bits 16:29 - Pixel per lines

pub fn nl(&mut self) -> NL_W<'_>[src]

Bits 0:15 - Number of lines

impl W<u32, Reg<u32, _LWR>>[src]

pub fn lw(&mut self) -> LW_W<'_>[src]

Bits 0:15 - Line watermark

impl W<u32, Reg<u32, _AMTCR>>[src]

pub fn dt(&mut self) -> DT_W<'_>[src]

Bits 8:15 - Dead Time

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - Enable

impl W<u32, Reg<u32, _FGCLUT>>[src]

pub fn aplha(&mut self) -> APLHA_W<'_>[src]

Bits 24:31 - APLHA

pub fn red(&mut self) -> RED_W<'_>[src]

Bits 16:23 - RED

pub fn green(&mut self) -> GREEN_W<'_>[src]

Bits 8:15 - GREEN

pub fn blue(&mut self) -> BLUE_W<'_>[src]

Bits 0:7 - BLUE

impl W<u32, Reg<u32, _BGCLUT>>[src]

pub fn aplha(&mut self) -> APLHA_W<'_>[src]

Bits 24:31 - APLHA

pub fn red(&mut self) -> RED_W<'_>[src]

Bits 16:23 - RED

pub fn green(&mut self) -> GREEN_W<'_>[src]

Bits 8:15 - GREEN

pub fn blue(&mut self) -> BLUE_W<'_>[src]

Bits 0:7 - BLUE

impl W<u32, Reg<u32, _CR>>[src]

pub fn prescaler(&mut self) -> PRESCALER_W<'_>[src]

Bits 24:31 - Clock prescaler

pub fn pmm(&mut self) -> PMM_W<'_>[src]

Bit 23 - Polling match mode

pub fn apms(&mut self) -> APMS_W<'_>[src]

Bit 22 - Automatic poll mode stop

pub fn toie(&mut self) -> TOIE_W<'_>[src]

Bit 20 - TimeOut interrupt enable

pub fn smie(&mut self) -> SMIE_W<'_>[src]

Bit 19 - Status match interrupt enable

pub fn ftie(&mut self) -> FTIE_W<'_>[src]

Bit 18 - FIFO threshold interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>[src]

Bit 17 - Transfer complete interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>[src]

Bit 16 - Transfer error interrupt enable

pub fn fthres(&mut self) -> FTHRES_W<'_>[src]

Bits 8:12 - IFO threshold level

pub fn fsel(&mut self) -> FSEL_W<'_>[src]

Bit 7 - FLASH memory selection

pub fn dfm(&mut self) -> DFM_W<'_>[src]

Bit 6 - Dual-flash mode

pub fn sshift(&mut self) -> SSHIFT_W<'_>[src]

Bit 4 - Sample shift

pub fn tcen(&mut self) -> TCEN_W<'_>[src]

Bit 3 - Timeout counter enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]

Bit 2 - DMA enable

pub fn abort(&mut self) -> ABORT_W<'_>[src]

Bit 1 - Abort request

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - Enable

impl W<u32, Reg<u32, _DCR>>[src]

pub fn fsize(&mut self) -> FSIZE_W<'_>[src]

Bits 16:20 - FLASH memory size

pub fn csht(&mut self) -> CSHT_W<'_>[src]

Bits 8:10 - Chip select high time

pub fn ckmode(&mut self) -> CKMODE_W<'_>[src]

Bit 0 - Mode 0 / mode 3

impl W<u32, Reg<u32, _FCR>>[src]

pub fn ctof(&mut self) -> CTOF_W<'_>[src]

Bit 4 - Clear timeout flag

pub fn csmf(&mut self) -> CSMF_W<'_>[src]

Bit 3 - Clear status match flag

pub fn ctcf(&mut self) -> CTCF_W<'_>[src]

Bit 1 - Clear transfer complete flag

pub fn ctef(&mut self) -> CTEF_W<'_>[src]

Bit 0 - Clear transfer error flag

impl W<u32, Reg<u32, _DLR>>[src]

pub fn dl(&mut self) -> DL_W<'_>[src]

Bits 0:31 - Data length

impl W<u32, Reg<u32, _CCR>>[src]

pub fn ddrm(&mut self) -> DDRM_W<'_>[src]

Bit 31 - Double data rate mode

pub fn dhhc(&mut self) -> DHHC_W<'_>[src]

Bit 30 - DDR hold half cycle

pub fn sioo(&mut self) -> SIOO_W<'_>[src]

Bit 28 - Send instruction only once mode

pub fn fmode(&mut self) -> FMODE_W<'_>[src]

Bits 26:27 - Functional mode

pub fn dmode(&mut self) -> DMODE_W<'_>[src]

Bits 24:25 - Data mode

pub fn dcyc(&mut self) -> DCYC_W<'_>[src]

Bits 18:22 - Number of dummy cycles

pub fn absize(&mut self) -> ABSIZE_W<'_>[src]

Bits 16:17 - Alternate bytes size

pub fn abmode(&mut self) -> ABMODE_W<'_>[src]

Bits 14:15 - Alternate bytes mode

pub fn adsize(&mut self) -> ADSIZE_W<'_>[src]

Bits 12:13 - Address size

pub fn admode(&mut self) -> ADMODE_W<'_>[src]

Bits 10:11 - Address mode

pub fn imode(&mut self) -> IMODE_W<'_>[src]

Bits 8:9 - Instruction mode

pub fn instruction(&mut self) -> INSTRUCTION_W<'_>[src]

Bits 0:7 - Instruction

impl W<u32, Reg<u32, _AR>>[src]

pub fn address(&mut self) -> ADDRESS_W<'_>[src]

Bits 0:31 - Address

impl W<u32, Reg<u32, _ABR>>[src]

pub fn alternate(&mut self) -> ALTERNATE_W<'_>[src]

Bits 0:31 - ALTERNATE

impl W<u32, Reg<u32, _DR>>[src]

pub fn data(&mut self) -> DATA_W<'_>[src]

Bits 0:31 - Data

impl W<u32, Reg<u32, _PSMKR>>[src]

pub fn mask(&mut self) -> MASK_W<'_>[src]

Bits 0:31 - Status mask

impl W<u32, Reg<u32, _PSMAR>>[src]

pub fn match_(&mut self) -> MATCH_W<'_>[src]

Bits 0:31 - Status match

impl W<u32, Reg<u32, _PIR>>[src]

pub fn interval(&mut self) -> INTERVAL_W<'_>[src]

Bits 0:15 - Polling interval

impl W<u32, Reg<u32, _LPTR>>[src]

pub fn timeout(&mut self) -> TIMEOUT_W<'_>[src]

Bits 0:15 - Timeout period

impl W<u32, Reg<u32, _CR>>[src]

pub fn txeom(&mut self) -> TXEOM_W<'_>[src]

Bit 2 - Tx End Of Message

pub fn txsom(&mut self) -> TXSOM_W<'_>[src]

Bit 1 - Tx start of message

pub fn cecen(&mut self) -> CECEN_W<'_>[src]

Bit 0 - CEC Enable

impl W<u32, Reg<u32, _CFGR>>[src]

pub fn sft(&mut self) -> SFT_W<'_>[src]

Bits 0:2 - Signal Free Time

pub fn rxtol(&mut self) -> RXTOL_W<'_>[src]

Bit 3 - Rx-Tolerance

pub fn brestp(&mut self) -> BRESTP_W<'_>[src]

Bit 4 - Rx-stop on bit rising error

pub fn bregen(&mut self) -> BREGEN_W<'_>[src]

Bit 5 - Generate error-bit on bit rising error

pub fn lbpegen(&mut self) -> LBPEGEN_W<'_>[src]

Bit 6 - Generate Error-Bit on Long Bit Period Error

pub fn brdnogen(&mut self) -> BRDNOGEN_W<'_>[src]

Bit 7 - Avoid Error-Bit Generation in Broadcast

pub fn sftop(&mut self) -> SFTOP_W<'_>[src]

Bit 8 - SFT Option Bit

pub fn oar(&mut self) -> OAR_W<'_>[src]

Bits 16:30 - Own addresses configuration

pub fn lstn(&mut self) -> LSTN_W<'_>[src]

Bit 31 - Listen mode

impl W<u32, Reg<u32, _TXDR>>[src]

pub fn txd(&mut self) -> TXD_W<'_>[src]

Bits 0:7 - Tx Data register

impl W<u32, Reg<u32, _ISR>>[src]

pub fn txacke(&mut self) -> TXACKE_W<'_>[src]

Bit 12 - Tx-Missing acknowledge error

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 11 - Tx-Error

pub fn txudr(&mut self) -> TXUDR_W<'_>[src]

Bit 10 - Tx-Buffer Underrun

pub fn txend(&mut self) -> TXEND_W<'_>[src]

Bit 9 - End of Transmission

pub fn txbr(&mut self) -> TXBR_W<'_>[src]

Bit 8 - Tx-Byte Request

pub fn arblst(&mut self) -> ARBLST_W<'_>[src]

Bit 7 - Arbitration Lost

pub fn rxacke(&mut self) -> RXACKE_W<'_>[src]

Bit 6 - Rx-Missing Acknowledge

pub fn lbpe(&mut self) -> LBPE_W<'_>[src]

Bit 5 - Rx-Long Bit Period Error

pub fn sbpe(&mut self) -> SBPE_W<'_>[src]

Bit 4 - Rx-Short Bit period error

pub fn bre(&mut self) -> BRE_W<'_>[src]

Bit 3 - Rx-Bit rising error

pub fn rxovr(&mut self) -> RXOVR_W<'_>[src]

Bit 2 - Rx-Overrun

pub fn rxend(&mut self) -> RXEND_W<'_>[src]

Bit 1 - End Of Reception

pub fn rxbr(&mut self) -> RXBR_W<'_>[src]

Bit 0 - Rx-Byte Received

impl W<u32, Reg<u32, _IER>>[src]

pub fn txackie(&mut self) -> TXACKIE_W<'_>[src]

Bit 12 - Tx-Missing Acknowledge Error Interrupt Enable

pub fn txerrie(&mut self) -> TXERRIE_W<'_>[src]

Bit 11 - Tx-Error Interrupt Enable

pub fn txudrie(&mut self) -> TXUDRIE_W<'_>[src]

Bit 10 - Tx-Underrun interrupt enable

pub fn txendie(&mut self) -> TXENDIE_W<'_>[src]

Bit 9 - Tx-End of message interrupt enable

pub fn txbrie(&mut self) -> TXBRIE_W<'_>[src]

Bit 8 - Tx-Byte Request Interrupt Enable

pub fn arblstie(&mut self) -> ARBLSTIE_W<'_>[src]

Bit 7 - Arbitration Lost Interrupt Enable

pub fn rxackie(&mut self) -> RXACKIE_W<'_>[src]

Bit 6 - Rx-Missing Acknowledge Error Interrupt Enable

pub fn lbpeie(&mut self) -> LBPEIE_W<'_>[src]

Bit 5 - Long Bit Period Error Interrupt Enable

pub fn sbpeie(&mut self) -> SBPEIE_W<'_>[src]

Bit 4 - Short Bit Period Error Interrupt Enable

pub fn breie(&mut self) -> BREIE_W<'_>[src]

Bit 3 - Bit Rising Error Interrupt Enable

pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>[src]

Bit 2 - Rx-Buffer Overrun Interrupt Enable

pub fn rxendie(&mut self) -> RXENDIE_W<'_>[src]

Bit 1 - End Of Reception Interrupt Enable

pub fn rxbrie(&mut self) -> RXBRIE_W<'_>[src]

Bit 0 - Rx-Byte Received Interrupt Enable

impl W<u32, Reg<u32, _CR>>[src]

pub fn spdifen(&mut self) -> SPDIFEN_W<'_>[src]

Bits 0:1 - Peripheral Block Enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>[src]

Bit 2 - Receiver DMA ENable for data flow

pub fn rxsteo(&mut self) -> RXSTEO_W<'_>[src]

Bit 3 - STerEO Mode

pub fn drfmt(&mut self) -> DRFMT_W<'_>[src]

Bits 4:5 - RX Data format

pub fn pmsk(&mut self) -> PMSK_W<'_>[src]

Bit 6 - Mask Parity error bit

pub fn vmsk(&mut self) -> VMSK_W<'_>[src]

Bit 7 - Mask of Validity bit

pub fn cumsk(&mut self) -> CUMSK_W<'_>[src]

Bit 8 - Mask of channel status and user bits

pub fn ptmsk(&mut self) -> PTMSK_W<'_>[src]

Bit 9 - Mask of Preamble Type bits

pub fn cbdmaen(&mut self) -> CBDMAEN_W<'_>[src]

Bit 10 - Control Buffer DMA ENable for control flow

pub fn chsel(&mut self) -> CHSEL_W<'_>[src]

Bit 11 - Channel Selection

pub fn nbtr(&mut self) -> NBTR_W<'_>[src]

Bits 12:13 - Maximum allowed re-tries during synchronization phase

pub fn wfa(&mut self) -> WFA_W<'_>[src]

Bit 14 - Wait For Activity

pub fn insel(&mut self) -> INSEL_W<'_>[src]

Bits 16:18 - input selection

impl W<u32, Reg<u32, _IMR>>[src]

pub fn rxneie(&mut self) -> RXNEIE_W<'_>[src]

Bit 0 - RXNE interrupt enable

pub fn csrneie(&mut self) -> CSRNEIE_W<'_>[src]

Bit 1 - Control Buffer Ready Interrupt Enable

pub fn perrie(&mut self) -> PERRIE_W<'_>[src]

Bit 2 - Parity error interrupt enable

pub fn ovrie(&mut self) -> OVRIE_W<'_>[src]

Bit 3 - Overrun error Interrupt Enable

pub fn sblkie(&mut self) -> SBLKIE_W<'_>[src]

Bit 4 - Synchronization Block Detected Interrupt Enable

pub fn syncdie(&mut self) -> SYNCDIE_W<'_>[src]

Bit 5 - Synchronization Done

pub fn ifeie(&mut self) -> IFEIE_W<'_>[src]

Bit 6 - Serial Interface Error Interrupt Enable

impl W<u32, Reg<u32, _IFCR>>[src]

pub fn perrcf(&mut self) -> PERRCF_W<'_>[src]

Bit 2 - Clears the Parity error flag

pub fn ovrcf(&mut self) -> OVRCF_W<'_>[src]

Bit 3 - Clears the Overrun error flag

pub fn sbdcf(&mut self) -> SBDCF_W<'_>[src]

Bit 4 - Clears the Synchronization Block Detected flag

pub fn syncdcf(&mut self) -> SYNCDCF_W<'_>[src]

Bit 5 - Clears the Synchronization Done flag

impl W<u32, Reg<u32, _POWER>>[src]

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>[src]

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>[src]

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>[src]

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>[src]

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>[src]

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>[src]

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>[src]

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>[src]

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>[src]

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>[src]

pub fn cmdarg(&mut self) -> CMDARG_W<'_>[src]

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>[src]

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>[src]

Bit 14 - CE-ATA command

pub fn n_ien(&mut self) -> NIEN_W<'_>[src]

Bit 13 - not Interrupt Enable

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>[src]

Bit 12 - Enable CMD completion

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>[src]

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>[src]

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>[src]

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)

pub fn waitint(&mut self) -> WAITINT_W<'_>[src]

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>[src]

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>[src]

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>[src]

pub fn datatime(&mut self) -> DATATIME_W<'_>[src]

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>[src]

pub fn datalength(&mut self) -> DATALENGTH_W<'_>[src]

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>[src]

pub fn sdioen(&mut self) -> SDIOEN_W<'_>[src]

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>[src]

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>[src]

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>[src]

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>[src]

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>[src]

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer

pub fn dtdir(&mut self) -> DTDIR_W<'_>[src]

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>[src]

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>[src]

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>[src]

Bit 23 - CEATAEND flag clear bit

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>[src]

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>[src]

Bit 10 - DBCKEND flag clear bit

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>[src]

Bit 9 - STBITERR flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>[src]

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>[src]

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>[src]

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>[src]

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>[src]

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>[src]

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>[src]

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>[src]

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>[src]

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>[src]

pub fn ceataendie(&mut self) -> CEATAENDIE_W<'_>[src]

Bit 23 - CE-ATA command completion signal received interrupt enable

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>[src]

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>[src]

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>[src]

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>[src]

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>[src]

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>[src]

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>[src]

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>[src]

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>[src]

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>[src]

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>[src]

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>[src]

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>[src]

Bit 10 - Data block end interrupt enable

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>[src]

Bit 9 - Start bit error interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>[src]

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>[src]

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>[src]

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>[src]

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>[src]

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>[src]

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>[src]

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>[src]

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>[src]

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>[src]

pub fn fifodata(&mut self) -> FIFODATA_W<'_>[src]

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _ICR>>[src]

pub fn downcf(&mut self) -> DOWNCF_W<'_>[src]

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>[src]

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>[src]

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>[src]

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>[src]

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>[src]

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>[src]

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>[src]

pub fn downie(&mut self) -> DOWNIE_W<'_>[src]

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>[src]

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>[src]

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>[src]

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>[src]

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>[src]

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>[src]

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>[src]

pub fn enc(&mut self) -> ENC_W<'_>[src]

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>[src]

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>[src]

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>[src]

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>[src]

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>[src]

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>[src]

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>[src]

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>[src]

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>[src]

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>[src]

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>[src]

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>[src]

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>[src]

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>[src]

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>[src]

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>[src]

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>[src]

pub fn cmp(&mut self) -> CMP_W<'_>[src]

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>[src]

pub fn arr(&mut self) -> ARR_W<'_>[src]

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _CR1>>[src]

pub fn pe(&mut self) -> PE_W<'_>[src]

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>[src]

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>[src]

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>[src]

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>[src]

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>[src]

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>[src]

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>[src]

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>[src]

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>[src]

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>[src]

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>[src]

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>[src]

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>[src]

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>[src]

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>[src]

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>[src]

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>[src]

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>[src]

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>[src]

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>[src]

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>[src]

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>[src]

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>[src]

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>[src]

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>[src]

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>[src]

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>[src]

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>[src]

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>[src]

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>[src]

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>[src]

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>[src]

pub fn oa1(&mut self) -> OA1_W<'_>[src]

Bits 0:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>[src]

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>[src]

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>[src]

pub fn oa2(&mut self) -> OA2_W<'_>[src]

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>[src]

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>[src]

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>[src]

pub fn scll(&mut self) -> SCLL_W<'_>[src]

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>[src]

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>[src]

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>[src]

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>[src]

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>[src]

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>[src]

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>[src]

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>[src]

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>[src]

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>[src]

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>[src]

pub fn txis(&mut self) -> TXIS_W<'_>[src]

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>[src]

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>[src]

pub fn alertcf(&mut self) -> ALERTCF_W<'_>[src]

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>[src]

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>[src]

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>[src]

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>[src]

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>[src]

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>[src]

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>[src]

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>[src]

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>[src]

pub fn txdata(&mut self) -> TXDATA_W<'_>[src]

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _TR>>[src]

pub fn pm(&mut self) -> PM_W<'_>[src]

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>[src]

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>[src]

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>[src]

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>[src]

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>[src]

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>[src]

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>[src]

pub fn yt(&mut self) -> YT_W<'_>[src]

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>[src]

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>[src]

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>[src]

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>[src]

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>[src]

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>[src]

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>[src]

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>[src]

Bits 0:2 - Wakeup clock selection

pub fn tsedge(&mut self) -> TSEDGE_W<'_>[src]

Bit 3 - Time-stamp event active edge

pub fn refckon(&mut self) -> REFCKON_W<'_>[src]

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>[src]

Bit 5 - Bypass the shadow registers

pub fn fmt(&mut self) -> FMT_W<'_>[src]

Bit 6 - Hour format

pub fn alrae(&mut self) -> ALRAE_W<'_>[src]

Bit 8 - Alarm A enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>[src]

Bit 9 - Alarm B enable

pub fn wute(&mut self) -> WUTE_W<'_>[src]

Bit 10 - Wakeup timer enable

pub fn tse(&mut self) -> TSE_W<'_>[src]

Bit 11 - Time stamp enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>[src]

Bit 12 - Alarm A interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>[src]

Bit 13 - Alarm B interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>[src]

Bit 14 - Wakeup timer interrupt enable

pub fn tsie(&mut self) -> TSIE_W<'_>[src]

Bit 15 - Time-stamp interrupt enable

pub fn add1h(&mut self) -> ADD1H_W<'_>[src]

Bit 16 - Add 1 hour (summer time change)

pub fn sub1h(&mut self) -> SUB1H_W<'_>[src]

Bit 17 - Subtract 1 hour (winter time change)

pub fn bkp(&mut self) -> BKP_W<'_>[src]

Bit 18 - Backup

pub fn cosel(&mut self) -> COSEL_W<'_>[src]

Bit 19 - Calibration output selection

pub fn pol(&mut self) -> POL_W<'_>[src]

Bit 20 - Output polarity

pub fn osel(&mut self) -> OSEL_W<'_>[src]

Bits 21:22 - Output selection

pub fn coe(&mut self) -> COE_W<'_>[src]

Bit 23 - Calibration output enable

pub fn itse(&mut self) -> ITSE_W<'_>[src]

Bit 24 - timestamp on internal event enable

impl W<u32, Reg<u32, _ISR>>[src]

pub fn shpf(&mut self) -> SHPF_W<'_>[src]

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>[src]

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>[src]

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>[src]

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>[src]

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>[src]

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>[src]

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>[src]

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>[src]

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>[src]

Bit 14 - RTC_TAMP2 detection flag

pub fn tamp3f(&mut self) -> TAMP3F_W<'_>[src]

Bit 15 - RTC_TAMP3 detection flag

impl W<u32, Reg<u32, _PRER>>[src]

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>[src]

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>[src]

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>[src]

pub fn wut(&mut self) -> WUT_W<'_>[src]

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _ALRMAR>>[src]

pub fn msk4(&mut self) -> MSK4_W<'_>[src]

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>[src]

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>[src]

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>[src]

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>[src]

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>[src]

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>[src]

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>[src]

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>[src]

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>[src]

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>[src]

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>[src]

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>[src]

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>[src]

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>[src]

pub fn msk4(&mut self) -> MSK4_W<'_>[src]

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>[src]

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>[src]

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>[src]

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>[src]

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>[src]

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>[src]

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>[src]

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>[src]

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>[src]

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>[src]

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>[src]

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>[src]

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>[src]

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>[src]

pub fn key(&mut self) -> KEY_W<'_>[src]

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>[src]

pub fn add1s(&mut self) -> ADD1S_W<'_>[src]

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>[src]

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>[src]

pub fn calp(&mut self) -> CALP_W<'_>[src]

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>[src]

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>[src]

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>[src]

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAMPCR>>[src]

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>[src]

Bit 0 - Tamper 1 detection enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>[src]

Bit 1 - Active level for tamper 1

pub fn tampie(&mut self) -> TAMPIE_W<'_>[src]

Bit 2 - Tamper interrupt enable

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>[src]

Bit 3 - Tamper 2 detection enable

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>[src]

Bit 4 - Active level for tamper 2

pub fn tamp3e(&mut self) -> TAMP3E_W<'_>[src]

Bit 5 - Tamper 3 detection enable

pub fn tamp3trg(&mut self) -> TAMP3TRG_W<'_>[src]

Bit 6 - Active level for tamper 3

pub fn tampts(&mut self) -> TAMPTS_W<'_>[src]

Bit 7 - Activate timestamp on tamper detection event

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>[src]

Bits 8:10 - Tamper sampling frequency

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>[src]

Bits 11:12 - Tamper filter count

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>[src]

Bits 13:14 - Tamper precharge duration

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>[src]

Bit 15 - TAMPER pull-up disable

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>[src]

Bit 16 - Tamper 1 interrupt enable

pub fn tamp1noerase(&mut self) -> TAMP1NOERASE_W<'_>[src]

Bit 17 - Tamper 1 no erase

pub fn tamp1mf(&mut self) -> TAMP1MF_W<'_>[src]

Bit 18 - Tamper 1 mask flag

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>[src]

Bit 19 - Tamper 2 interrupt enable

pub fn tamp2noerase(&mut self) -> TAMP2NOERASE_W<'_>[src]

Bit 20 - Tamper 2 no erase

pub fn tamp2mf(&mut self) -> TAMP2MF_W<'_>[src]

Bit 21 - Tamper 2 mask flag

pub fn tamp3ie(&mut self) -> TAMP3IE_W<'_>[src]

Bit 22 - Tamper 3 interrupt enable

pub fn tamp3noerase(&mut self) -> TAMP3NOERASE_W<'_>[src]

Bit 23 - Tamper 3 no erase

pub fn tamp3mf(&mut self) -> TAMP3MF_W<'_>[src]

Bit 24 - Tamper 3 mask flag

impl W<u32, Reg<u32, _ALRMASSR>>[src]

pub fn maskss(&mut self) -> MASKSS_W<'_>[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>[src]

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>[src]

pub fn maskss(&mut self) -> MASKSS_W<'_>[src]

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>[src]

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _OR>>[src]

pub fn rtc_alarm_type(&mut self) -> RTC_ALARM_TYPE_W<'_>[src]

Bit 0 - RTC_ALARM on PC13 output type

pub fn rtc_out_rmp(&mut self) -> RTC_OUT_RMP_W<'_>[src]

Bit 1 - RTC_OUT remap

impl W<u32, Reg<u32, _BKPR>>[src]

pub fn bkp(&mut self) -> BKP_W<'_>[src]

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR1>>[src]

pub fn m1(&mut self) -> M1_W<'_>[src]

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>[src]

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>[src]

Bit 26 - Receiver timeout interrupt enable

pub fn over8(&mut self) -> OVER8_W<'_>[src]

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>[src]

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>[src]

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>[src]

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>[src]

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>[src]

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>[src]

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>[src]

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>[src]

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>[src]

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>[src]

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>[src]

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>[src]

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>[src]

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>[src]

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>[src]

Bit 0 - USART enable

pub fn deat(&mut self) -> DEAT_W<'_>[src]

Bits 21:25 - Driver Enable assertion time

pub fn dedt(&mut self) -> DEDT_W<'_>[src]

Bits 16:20 - Driver Enable de-assertion time

impl W<u32, Reg<u32, _CR2>>[src]

pub fn rtoen(&mut self) -> RTOEN_W<'_>[src]

Bit 23 - Receiver timeout enable

pub fn abren(&mut self) -> ABREN_W<'_>[src]

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>[src]

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>[src]

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>[src]

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>[src]

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>[src]

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>[src]

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>[src]

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>[src]

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>[src]

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>[src]

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>[src]

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>[src]

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>[src]

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>[src]

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn abrmod(&mut self) -> ABRMOD_W<'_>[src]

Bits 21:22 - Auto baud rate mode

pub fn add(&mut self) -> ADD_W<'_>[src]

Bits 24:31 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>[src]

pub fn wufie(&mut self) -> WUFIE_W<'_>[src]

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>[src]

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>[src]

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>[src]

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>[src]

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>[src]

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>[src]

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>[src]

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>[src]

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>[src]

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>[src]

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>[src]

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>[src]

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>[src]

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>[src]

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>[src]

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>[src]

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>[src]

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>[src]

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>[src]

pub fn brr(&mut self) -> BRR_W<'_>[src]

Bits 0:15 - DIV_Mantissa

impl W<u32, Reg<u32, _GTPR>>[src]

pub fn gt(&mut self) -> GT_W<'_>[src]

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>[src]

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>[src]

pub fn blen(&mut self) -> BLEN_W<'_>[src]

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>[src]

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>[src]

pub fn txfrq(&mut self) -> TXFRQ_W<'_>[src]

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>[src]

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>[src]

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>[src]

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>[src]

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>[src]

pub fn wucf(&mut self) -> WUCF_W<'_>[src]

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>[src]

Bit 17 - Character match clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>[src]

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>[src]

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>[src]

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>[src]

Bit 8 - LIN break detection clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>[src]

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>[src]

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>[src]

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>[src]

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>[src]

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>[src]

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>[src]

pub fn tdr(&mut self) -> TDR_W<'_>[src]

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _OTG_FS_GOTGCTL>>[src]

pub fn srq(&mut self) -> SRQ_W<'_>[src]

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>[src]

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>[src]

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>[src]

Bit 11 - Device HNP enabled

pub fn vbvaloen(&mut self) -> VBVALOEN_W<'_>[src]

Bit 2 - VBUS valid override enable

pub fn vbvaloval(&mut self) -> VBVALOVAL_W<'_>[src]

Bit 3 - VBUS valid override value

pub fn avaloen(&mut self) -> AVALOEN_W<'_>[src]

Bit 4 - A-peripheral session valid override enable

pub fn avaloval(&mut self) -> AVALOVAL_W<'_>[src]

Bit 5 - A-peripheral session valid override value

pub fn bvaloen(&mut self) -> BVALOEN_W<'_>[src]

Bit 6 - B-peripheral session valid override enable

pub fn bvaloval(&mut self) -> BVALOVAL_W<'_>[src]

Bit 7 - B-peripheral session valid override value

pub fn ehen(&mut self) -> EHEN_W<'_>[src]

Bit 12 - Embedded host enable

pub fn otgver(&mut self) -> OTGVER_W<'_>[src]

Bit 20 - OTG version

impl W<u32, Reg<u32, _OTG_FS_GOTGINT>>[src]

pub fn sedet(&mut self) -> SEDET_W<'_>[src]

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>[src]

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>[src]

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>[src]

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>[src]

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>[src]

Bit 19 - Debounce done

pub fn idchng(&mut self) -> IDCHNG_W<'_>[src]

Bit 20 - ID input pin changed

impl W<u32, Reg<u32, _OTG_FS_GAHBCFG>>[src]

pub fn gint(&mut self) -> GINT_W<'_>[src]

Bit 0 - Global interrupt mask

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>[src]

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>[src]

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _OTG_FS_GUSBCFG>>[src]

pub fn tocal(&mut self) -> TOCAL_W<'_>[src]

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>[src]

Bit 6 - Full Speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>[src]

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>[src]

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>[src]

Bits 10:13 - USB turnaround time

pub fn fhmod(&mut self) -> FHMOD_W<'_>[src]

Bit 29 - Force host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>[src]

Bit 30 - Force device mode

impl W<u32, Reg<u32, _OTG_FS_GRSTCTL>>[src]

pub fn csrst(&mut self) -> CSRST_W<'_>[src]

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>[src]

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>[src]

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>[src]

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>[src]

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _OTG_FS_GINTSTS>>[src]

pub fn mmis(&mut self) -> MMIS_W<'_>[src]

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>[src]

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>[src]

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>[src]

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>[src]

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>[src]

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>[src]

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>[src]

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>[src]

Bit 20 - Incomplete isochronous IN transfer

pub fn ipxfr_incompisoout(&mut self) -> IPXFR_INCOMPISOOUT_W<'_>[src]

Bit 21 - Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>[src]

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>[src]

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>[src]

Bit 30 - Session request/new session detected interrupt

pub fn wkupint(&mut self) -> WKUPINT_W<'_>[src]

Bit 31 - Resume/remote wakeup detected interrupt

pub fn rstdet(&mut self) -> RSTDET_W<'_>[src]

Bit 23 - Reset detected interrupt

impl W<u32, Reg<u32, _OTG_FS_GINTMSK>>[src]

pub fn mmism(&mut self) -> MMISM_W<'_>[src]

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>[src]

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>[src]

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>[src]

Bit 4 - Receive FIFO non-empty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>[src]

Bit 5 - Non-periodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>[src]

Bit 6 - Global non-periodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>[src]

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>[src]

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>[src]

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>[src]

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>[src]

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>[src]

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>[src]

Bit 15 - End of periodic frame interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>[src]

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>[src]

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>[src]

Bit 20 - Incomplete isochronous IN transfer mask

pub fn ipxfrm_iisooxfrm(&mut self) -> IPXFRM_IISOOXFRM_W<'_>[src]

Bit 21 - Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)

pub fn hcim(&mut self) -> HCIM_W<'_>[src]

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>[src]

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>[src]

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>[src]

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>[src]

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>[src]

Bit 31 - Resume/remote wakeup detected interrupt mask

pub fn rstdetm(&mut self) -> RSTDETM_W<'_>[src]

Bit 23 - Reset detected interrupt mask

pub fn lpmin(&mut self) -> LPMIN_W<'_>[src]

Bit 27 - LPM interrupt mask

impl W<u32, Reg<u32, _OTG_FS_GRXFSIZ>>[src]

pub fn rxfd(&mut self) -> RXFD_W<'_>[src]

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF0_DEVICE>>[src]

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>[src]

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>[src]

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_HNPTXFSIZ_HOST>>[src]

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>[src]

Bits 0:15 - Non-periodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>[src]

Bits 16:31 - Non-periodic TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_GCCFG>>[src]

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>[src]

Bit 16 - Power down

pub fn bcden(&mut self) -> BCDEN_W<'_>[src]

Bit 17 - Battery charging detector (BCD) enable

pub fn dcden(&mut self) -> DCDEN_W<'_>[src]

Bit 18 - Data contact detection (DCD) mode enable

pub fn pden(&mut self) -> PDEN_W<'_>[src]

Bit 19 - Primary detection (PD) mode enable

pub fn sden(&mut self) -> SDEN_W<'_>[src]

Bit 20 - Secondary detection (SD) mode enable

pub fn vbden(&mut self) -> VBDEN_W<'_>[src]

Bit 21 - USB VBUS detection enable

pub fn dcdet(&mut self) -> DCDET_W<'_>[src]

Bit 0 - Data contact detection (DCD) status

pub fn pdet(&mut self) -> PDET_W<'_>[src]

Bit 1 - Primary detection (PD) status

pub fn sdet(&mut self) -> SDET_W<'_>[src]

Bit 2 - Secondary detection (SD) status

pub fn ps2det(&mut self) -> PS2DET_W<'_>[src]

Bit 3 - DM pull-up detection status

impl W<u32, Reg<u32, _OTG_FS_CID>>[src]

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>[src]

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _OTG_FS_HPTXFSIZ>>[src]

pub fn ptxsa(&mut self) -> PTXSA_W<'_>[src]

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfsiz(&mut self) -> PTXFSIZ_W<'_>[src]

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF1>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFO2 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF2>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFO3 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF3>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFO4 transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_FS_GI2CCTL>>[src]

pub fn rwdata(&mut self) -> RWDATA_W<'_>[src]

Bits 0:7 - I2C Read/Write Data

pub fn regaddr(&mut self) -> REGADDR_W<'_>[src]

Bits 8:15 - I2C Register Address

pub fn addr(&mut self) -> ADDR_W<'_>[src]

Bits 16:22 - I2C Address

pub fn i2cen(&mut self) -> I2CEN_W<'_>[src]

Bit 23 - I2C Enable

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 24 - I2C ACK

pub fn i2cdevadr(&mut self) -> I2CDEVADR_W<'_>[src]

Bits 26:27 - I2C Device Address

pub fn i2cdatse0(&mut self) -> I2CDATSE0_W<'_>[src]

Bit 28 - I2C DatSe0 USB mode

pub fn rw(&mut self) -> RW_W<'_>[src]

Bit 30 - Read/Write Indicator

pub fn bsydne(&mut self) -> BSYDNE_W<'_>[src]

Bit 31 - I2C Busy/Done

impl W<u32, Reg<u32, _OTG_FS_GPWRDN>>[src]

pub fn adpmen(&mut self) -> ADPMEN_W<'_>[src]

Bit 0 - ADP module enable

pub fn adpif(&mut self) -> ADPIF_W<'_>[src]

Bit 23 - ADP interrupt flag

impl W<u32, Reg<u32, _OTG_FS_GADPCTL>>[src]

pub fn prbdschg(&mut self) -> PRBDSCHG_W<'_>[src]

Bits 0:1 - Probe discharge

pub fn prbdelta(&mut self) -> PRBDELTA_W<'_>[src]

Bits 2:3 - Probe delta

pub fn prbper(&mut self) -> PRBPER_W<'_>[src]

Bits 4:5 - Probe period

pub fn enaprb(&mut self) -> ENAPRB_W<'_>[src]

Bit 17 - Enable probe

pub fn enasns(&mut self) -> ENASNS_W<'_>[src]

Bit 18 - Enable sense

pub fn adpen(&mut self) -> ADPEN_W<'_>[src]

Bit 20 - ADP enable

pub fn adpprbif(&mut self) -> ADPPRBIF_W<'_>[src]

Bit 21 - ADP probe interrupt flag

pub fn adpsnsif(&mut self) -> ADPSNSIF_W<'_>[src]

Bit 22 - ADP sense interrupt flag

pub fn adptoif(&mut self) -> ADPTOIF_W<'_>[src]

Bit 23 - ADP timeout interrupt flag

pub fn adpprbim(&mut self) -> ADPPRBIM_W<'_>[src]

Bit 24 - ADP probe interrupt mask

pub fn adpsnsim(&mut self) -> ADPSNSIM_W<'_>[src]

Bit 25 - ADP sense interrupt mask

pub fn adptoim(&mut self) -> ADPTOIM_W<'_>[src]

Bit 26 - ADP timeout interrupt mask

pub fn ar(&mut self) -> AR_W<'_>[src]

Bits 27:28 - Access request

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF4>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint Tx FIFO depth

impl W<u32, Reg<u32, _OTG_FS_DIEPTXF5>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint Tx FIFO depth

impl W<u32, Reg<u32, _OTG_FS_GLPMCFG>>[src]

pub fn lpmen(&mut self) -> LPMEN_W<'_>[src]

Bit 0 - LPM support enable

pub fn lpmack(&mut self) -> LPMACK_W<'_>[src]

Bit 1 - LPM token acknowledge enable

pub fn besl(&mut self) -> BESL_W<'_>[src]

Bits 2:5 - Best effort service latency

pub fn remwake(&mut self) -> REMWAKE_W<'_>[src]

Bit 6 - bRemoteWake value

pub fn l1ssen(&mut self) -> L1SSEN_W<'_>[src]

Bit 7 - L1 Shallow Sleep enable

pub fn beslthrs(&mut self) -> BESLTHRS_W<'_>[src]

Bits 8:11 - BESL threshold

pub fn l1dsen(&mut self) -> L1DSEN_W<'_>[src]

Bit 12 - L1 deep sleep enable

pub fn lpmchidx(&mut self) -> LPMCHIDX_W<'_>[src]

Bits 17:20 - LPM Channel Index

pub fn lpmrcnt(&mut self) -> LPMRCNT_W<'_>[src]

Bits 21:23 - LPM retry count

pub fn sndlpm(&mut self) -> SNDLPM_W<'_>[src]

Bit 24 - Send LPM transaction

pub fn enbesl(&mut self) -> ENBESL_W<'_>[src]

Bit 28 - Enable best effort service latency

impl W<u32, Reg<u32, _OTG_HS_GOTGCTL>>[src]

pub fn srq(&mut self) -> SRQ_W<'_>[src]

Bit 1 - Session request

pub fn hnprq(&mut self) -> HNPRQ_W<'_>[src]

Bit 9 - HNP request

pub fn hshnpen(&mut self) -> HSHNPEN_W<'_>[src]

Bit 10 - Host set HNP enable

pub fn dhnpen(&mut self) -> DHNPEN_W<'_>[src]

Bit 11 - Device HNP enabled

pub fn ehen(&mut self) -> EHEN_W<'_>[src]

Bit 12 - Embedded host enable

impl W<u32, Reg<u32, _OTG_HS_GOTGINT>>[src]

pub fn sedet(&mut self) -> SEDET_W<'_>[src]

Bit 2 - Session end detected

pub fn srsschg(&mut self) -> SRSSCHG_W<'_>[src]

Bit 8 - Session request success status change

pub fn hnsschg(&mut self) -> HNSSCHG_W<'_>[src]

Bit 9 - Host negotiation success status change

pub fn hngdet(&mut self) -> HNGDET_W<'_>[src]

Bit 17 - Host negotiation detected

pub fn adtochg(&mut self) -> ADTOCHG_W<'_>[src]

Bit 18 - A-device timeout change

pub fn dbcdne(&mut self) -> DBCDNE_W<'_>[src]

Bit 19 - Debounce done

pub fn idchng(&mut self) -> IDCHNG_W<'_>[src]

Bit 20 - ID input pin changed

impl W<u32, Reg<u32, _OTG_HS_GAHBCFG>>[src]

pub fn gint(&mut self) -> GINT_W<'_>[src]

Bit 0 - Global interrupt mask

pub fn hbstlen(&mut self) -> HBSTLEN_W<'_>[src]

Bits 1:4 - Burst length/type

pub fn dmaen(&mut self) -> DMAEN_W<'_>[src]

Bit 5 - DMA enable

pub fn txfelvl(&mut self) -> TXFELVL_W<'_>[src]

Bit 7 - TxFIFO empty level

pub fn ptxfelvl(&mut self) -> PTXFELVL_W<'_>[src]

Bit 8 - Periodic TxFIFO empty level

impl W<u32, Reg<u32, _OTG_HS_GUSBCFG>>[src]

pub fn tocal(&mut self) -> TOCAL_W<'_>[src]

Bits 0:2 - FS timeout calibration

pub fn physel(&mut self) -> PHYSEL_W<'_>[src]

Bit 6 - USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select

pub fn srpcap(&mut self) -> SRPCAP_W<'_>[src]

Bit 8 - SRP-capable

pub fn hnpcap(&mut self) -> HNPCAP_W<'_>[src]

Bit 9 - HNP-capable

pub fn trdt(&mut self) -> TRDT_W<'_>[src]

Bits 10:13 - USB turnaround time

pub fn phylpcs(&mut self) -> PHYLPCS_W<'_>[src]

Bit 15 - PHY Low-power clock select

pub fn ulpifsls(&mut self) -> ULPIFSLS_W<'_>[src]

Bit 17 - ULPI FS/LS select

pub fn ulpiar(&mut self) -> ULPIAR_W<'_>[src]

Bit 18 - ULPI Auto-resume

pub fn ulpicsm(&mut self) -> ULPICSM_W<'_>[src]

Bit 19 - ULPI Clock SuspendM

pub fn ulpievbusd(&mut self) -> ULPIEVBUSD_W<'_>[src]

Bit 20 - ULPI External VBUS Drive

pub fn ulpievbusi(&mut self) -> ULPIEVBUSI_W<'_>[src]

Bit 21 - ULPI external VBUS indicator

pub fn tsdps(&mut self) -> TSDPS_W<'_>[src]

Bit 22 - TermSel DLine pulsing selection

pub fn pcci(&mut self) -> PCCI_W<'_>[src]

Bit 23 - Indicator complement

pub fn ptci(&mut self) -> PTCI_W<'_>[src]

Bit 24 - Indicator pass through

pub fn ulpiipd(&mut self) -> ULPIIPD_W<'_>[src]

Bit 25 - ULPI interface protect disable

pub fn fhmod(&mut self) -> FHMOD_W<'_>[src]

Bit 29 - Forced host mode

pub fn fdmod(&mut self) -> FDMOD_W<'_>[src]

Bit 30 - Forced peripheral mode

impl W<u32, Reg<u32, _OTG_HS_GRSTCTL>>[src]

pub fn csrst(&mut self) -> CSRST_W<'_>[src]

Bit 0 - Core soft reset

pub fn hsrst(&mut self) -> HSRST_W<'_>[src]

Bit 1 - HCLK soft reset

pub fn fcrst(&mut self) -> FCRST_W<'_>[src]

Bit 2 - Host frame counter reset

pub fn rxfflsh(&mut self) -> RXFFLSH_W<'_>[src]

Bit 4 - RxFIFO flush

pub fn txfflsh(&mut self) -> TXFFLSH_W<'_>[src]

Bit 5 - TxFIFO flush

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 6:10 - TxFIFO number

impl W<u32, Reg<u32, _OTG_HS_GINTSTS>>[src]

pub fn mmis(&mut self) -> MMIS_W<'_>[src]

Bit 1 - Mode mismatch interrupt

pub fn sof(&mut self) -> SOF_W<'_>[src]

Bit 3 - Start of frame

pub fn esusp(&mut self) -> ESUSP_W<'_>[src]

Bit 10 - Early suspend

pub fn usbsusp(&mut self) -> USBSUSP_W<'_>[src]

Bit 11 - USB suspend

pub fn usbrst(&mut self) -> USBRST_W<'_>[src]

Bit 12 - USB reset

pub fn enumdne(&mut self) -> ENUMDNE_W<'_>[src]

Bit 13 - Enumeration done

pub fn isoodrp(&mut self) -> ISOODRP_W<'_>[src]

Bit 14 - Isochronous OUT packet dropped interrupt

pub fn eopf(&mut self) -> EOPF_W<'_>[src]

Bit 15 - End of periodic frame interrupt

pub fn iisoixfr(&mut self) -> IISOIXFR_W<'_>[src]

Bit 20 - Incomplete isochronous IN transfer

pub fn pxfr_incompisoout(&mut self) -> PXFR_INCOMPISOOUT_W<'_>[src]

Bit 21 - Incomplete periodic transfer

pub fn datafsusp(&mut self) -> DATAFSUSP_W<'_>[src]

Bit 22 - Data fetch suspended

pub fn cidschg(&mut self) -> CIDSCHG_W<'_>[src]

Bit 28 - Connector ID status change

pub fn discint(&mut self) -> DISCINT_W<'_>[src]

Bit 29 - Disconnect detected interrupt

pub fn srqint(&mut self) -> SRQINT_W<'_>[src]

Bit 30 - Session request/new session detected interrupt

pub fn wkuint(&mut self) -> WKUINT_W<'_>[src]

Bit 31 - Resume/remote wakeup detected interrupt

impl W<u32, Reg<u32, _OTG_HS_GINTMSK>>[src]

pub fn mmism(&mut self) -> MMISM_W<'_>[src]

Bit 1 - Mode mismatch interrupt mask

pub fn otgint(&mut self) -> OTGINT_W<'_>[src]

Bit 2 - OTG interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>[src]

Bit 3 - Start of frame mask

pub fn rxflvlm(&mut self) -> RXFLVLM_W<'_>[src]

Bit 4 - Receive FIFO nonempty mask

pub fn nptxfem(&mut self) -> NPTXFEM_W<'_>[src]

Bit 5 - Nonperiodic TxFIFO empty mask

pub fn ginakeffm(&mut self) -> GINAKEFFM_W<'_>[src]

Bit 6 - Global nonperiodic IN NAK effective mask

pub fn gonakeffm(&mut self) -> GONAKEFFM_W<'_>[src]

Bit 7 - Global OUT NAK effective mask

pub fn esuspm(&mut self) -> ESUSPM_W<'_>[src]

Bit 10 - Early suspend mask

pub fn usbsuspm(&mut self) -> USBSUSPM_W<'_>[src]

Bit 11 - USB suspend mask

pub fn usbrst(&mut self) -> USBRST_W<'_>[src]

Bit 12 - USB reset mask

pub fn enumdnem(&mut self) -> ENUMDNEM_W<'_>[src]

Bit 13 - Enumeration done mask

pub fn isoodrpm(&mut self) -> ISOODRPM_W<'_>[src]

Bit 14 - Isochronous OUT packet dropped interrupt mask

pub fn eopfm(&mut self) -> EOPFM_W<'_>[src]

Bit 15 - End of periodic frame interrupt mask

pub fn iepint(&mut self) -> IEPINT_W<'_>[src]

Bit 18 - IN endpoints interrupt mask

pub fn oepint(&mut self) -> OEPINT_W<'_>[src]

Bit 19 - OUT endpoints interrupt mask

pub fn iisoixfrm(&mut self) -> IISOIXFRM_W<'_>[src]

Bit 20 - Incomplete isochronous IN transfer mask

pub fn pxfrm_iisooxfrm(&mut self) -> PXFRM_IISOOXFRM_W<'_>[src]

Bit 21 - Incomplete periodic transfer mask

pub fn fsuspm(&mut self) -> FSUSPM_W<'_>[src]

Bit 22 - Data fetch suspended mask

pub fn hcim(&mut self) -> HCIM_W<'_>[src]

Bit 25 - Host channels interrupt mask

pub fn ptxfem(&mut self) -> PTXFEM_W<'_>[src]

Bit 26 - Periodic TxFIFO empty mask

pub fn cidschgm(&mut self) -> CIDSCHGM_W<'_>[src]

Bit 28 - Connector ID status change mask

pub fn discint(&mut self) -> DISCINT_W<'_>[src]

Bit 29 - Disconnect detected interrupt mask

pub fn srqim(&mut self) -> SRQIM_W<'_>[src]

Bit 30 - Session request/new session detected interrupt mask

pub fn wuim(&mut self) -> WUIM_W<'_>[src]

Bit 31 - Resume/remote wakeup detected interrupt mask

pub fn rstde(&mut self) -> RSTDE_W<'_>[src]

Bit 23 - Reset detected interrupt mask

pub fn lpmintm(&mut self) -> LPMINTM_W<'_>[src]

Bit 27 - LPM interrupt mask

impl W<u32, Reg<u32, _OTG_HS_GRXFSIZ>>[src]

pub fn rxfd(&mut self) -> RXFD_W<'_>[src]

Bits 0:15 - RxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_HNPTXFSIZ_HOST>>[src]

pub fn nptxfsa(&mut self) -> NPTXFSA_W<'_>[src]

Bits 0:15 - Nonperiodic transmit RAM start address

pub fn nptxfd(&mut self) -> NPTXFD_W<'_>[src]

Bits 16:31 - Nonperiodic TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF0_DEVICE>>[src]

pub fn tx0fsa(&mut self) -> TX0FSA_W<'_>[src]

Bits 0:15 - Endpoint 0 transmit RAM start address

pub fn tx0fd(&mut self) -> TX0FD_W<'_>[src]

Bits 16:31 - Endpoint 0 TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_GCCFG>>[src]

pub fn pwrdwn(&mut self) -> PWRDWN_W<'_>[src]

Bit 16 - Power down

pub fn bcden(&mut self) -> BCDEN_W<'_>[src]

Bit 17 - Battery charging detector (BCD) enable

pub fn dcden(&mut self) -> DCDEN_W<'_>[src]

Bit 18 - Data contact detection (DCD) mode enable

pub fn pden(&mut self) -> PDEN_W<'_>[src]

Bit 19 - Primary detection (PD) mode enable

pub fn sden(&mut self) -> SDEN_W<'_>[src]

Bit 20 - Secondary detection (SD) mode enable

pub fn vbden(&mut self) -> VBDEN_W<'_>[src]

Bit 21 - USB VBUS detection enable

pub fn dcdet(&mut self) -> DCDET_W<'_>[src]

Bit 0 - Data contact detection (DCD) status

pub fn pdet(&mut self) -> PDET_W<'_>[src]

Bit 1 - Primary detection (PD) status

pub fn sdet(&mut self) -> SDET_W<'_>[src]

Bit 2 - Secondary detection (SD) status

pub fn ps2det(&mut self) -> PS2DET_W<'_>[src]

Bit 3 - DM pull-up detection status

impl W<u32, Reg<u32, _OTG_HS_CID>>[src]

pub fn product_id(&mut self) -> PRODUCT_ID_W<'_>[src]

Bits 0:31 - Product ID field

impl W<u32, Reg<u32, _OTG_HS_HPTXFSIZ>>[src]

pub fn ptxsa(&mut self) -> PTXSA_W<'_>[src]

Bits 0:15 - Host periodic TxFIFO start address

pub fn ptxfd(&mut self) -> PTXFD_W<'_>[src]

Bits 16:31 - Host periodic TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF1>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF2>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF3>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF4>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF5>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF6>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_DIEPTXF7>>[src]

pub fn ineptxsa(&mut self) -> INEPTXSA_W<'_>[src]

Bits 0:15 - IN endpoint FIFOx transmit RAM start address

pub fn ineptxfd(&mut self) -> INEPTXFD_W<'_>[src]

Bits 16:31 - IN endpoint TxFIFO depth

impl W<u32, Reg<u32, _OTG_HS_GLPMCFG>>[src]

pub fn lpmen(&mut self) -> LPMEN_W<'_>[src]

Bit 0 - LPM support enable

pub fn lpmack(&mut self) -> LPMACK_W<'_>[src]

Bit 1 - LPM token acknowledge enable

pub fn l1ssen(&mut self) -> L1SSEN_W<'_>[src]

Bit 7 - L1 Shallow Sleep enable

pub fn beslthrs(&mut self) -> BESLTHRS_W<'_>[src]

Bits 8:11 - BESL threshold

pub fn l1dsen(&mut self) -> L1DSEN_W<'_>[src]

Bit 12 - L1 deep sleep enable

pub fn lpmchidx(&mut self) -> LPMCHIDX_W<'_>[src]

Bits 17:20 - LPM Channel Index

pub fn lpmrcnt(&mut self) -> LPMRCNT_W<'_>[src]

Bits 21:23 - LPM retry count

pub fn sndlpm(&mut self) -> SNDLPM_W<'_>[src]

Bit 24 - Send LPM transaction

pub fn enbesl(&mut self) -> ENBESL_W<'_>[src]

Bit 28 - Enable best effort service latency

impl W<u32, Reg<u32, _CR>>[src]

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - Peripheral enable

pub fn wrie(&mut self) -> WRIE_W<'_>[src]

Bit 1 - Register write interrupt enable

pub fn rdie(&mut self) -> RDIE_W<'_>[src]

Bit 2 - Register Read Interrupt Enable

pub fn eie(&mut self) -> EIE_W<'_>[src]

Bit 3 - Error interrupt enable

pub fn dpc(&mut self) -> DPC_W<'_>[src]

Bit 7 - Disable Preamble Check

pub fn port_address(&mut self) -> PORT_ADDRESS_W<'_>[src]

Bits 8:12 - Slaves's address

impl W<u32, Reg<u32, _CWRFR>>[src]

pub fn cwrf(&mut self) -> CWRF_W<'_>[src]

Bits 0:31 - Clear the write flag

impl W<u32, Reg<u32, _CRDFR>>[src]

pub fn crdf(&mut self) -> CRDF_W<'_>[src]

Bits 0:31 - Clear the read flag

impl W<u32, Reg<u32, _CLRFR>>[src]

pub fn cperf(&mut self) -> CPERF_W<'_>[src]

Bit 0 - Clear the preamble error flag

pub fn cserf(&mut self) -> CSERF_W<'_>[src]

Bit 1 - Clear the start error flag

pub fn cterf(&mut self) -> CTERF_W<'_>[src]

Bit 2 - Clear the turnaround error flag

impl W<u32, Reg<u32, _DOUTR>>[src]

pub fn dout(&mut self) -> DOUT_W<'_>[src]

Bits 0:15 - Output data sent to MDIO Master during read frames

impl W<u32, Reg<u32, _DFSDM_CHCFG0R1>>[src]

pub fn sitp(&mut self) -> SITP_W<'_>[src]

Bits 0:1 - Serial interface type for channel 0

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>[src]

Bits 2:3 - SPI clock select for channel 0

pub fn scden(&mut self) -> SCDEN_W<'_>[src]

Bit 5 - Short-circuit detector enable on channel 0

pub fn ckaben(&mut self) -> CKABEN_W<'_>[src]

Bit 6 - Clock absence detector enable on channel 0

pub fn chen(&mut self) -> CHEN_W<'_>[src]

Bit 7 - Channel 0 enable

pub fn chinsel(&mut self) -> CHINSEL_W<'_>[src]

Bit 8 - Channel inputs selection

pub fn datmpx(&mut self) -> DATMPX_W<'_>[src]

Bits 12:13 - Input data multiplexer for channel 0

pub fn datpack(&mut self) -> DATPACK_W<'_>[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>[src]

Bits 16:23 - Output serial clock divider

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>[src]

Bit 30 - Output serial clock source selection

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>[src]

Bit 31 - Global enable for DFSDM interface

impl W<u32, Reg<u32, _DFSDM_CHCFG1R1>>[src]

pub fn sitp(&mut self) -> SITP_W<'_>[src]

Bits 0:1 - Serial interface type for channel 1

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>[src]

Bits 2:3 - SPI clock select for channel 1

pub fn scden(&mut self) -> SCDEN_W<'_>[src]

Bit 5 - Short-circuit detector enable on channel 1

pub fn ckaben(&mut self) -> CKABEN_W<'_>[src]

Bit 6 - Clock absence detector enable on channel 1

pub fn chen(&mut self) -> CHEN_W<'_>[src]

Bit 7 - Channel 1 enable

pub fn chinsel(&mut self) -> CHINSEL_W<'_>[src]

Bit 8 - Channel inputs selection

pub fn datmpx(&mut self) -> DATMPX_W<'_>[src]

Bits 12:13 - Input data multiplexer for channel 1

pub fn datpack(&mut self) -> DATPACK_W<'_>[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>[src]

Bits 16:23 - Output serial clock divider

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>[src]

Bit 30 - Output serial clock source selection

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>[src]

Bit 31 - Global enable for DFSDM interface

impl W<u32, Reg<u32, _DFSDM_CHCFG2R1>>[src]

pub fn sitp(&mut self) -> SITP_W<'_>[src]

Bits 0:1 - Serial interface type for channel 2

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>[src]

Bits 2:3 - SPI clock select for channel 2

pub fn scden(&mut self) -> SCDEN_W<'_>[src]

Bit 5 - Short-circuit detector enable on channel 2

pub fn ckaben(&mut self) -> CKABEN_W<'_>[src]

Bit 6 - Clock absence detector enable on channel 2

pub fn chen(&mut self) -> CHEN_W<'_>[src]

Bit 7 - Channel 2 enable

pub fn chinsel(&mut self) -> CHINSEL_W<'_>[src]

Bit 8 - Channel inputs selection

pub fn datmpx(&mut self) -> DATMPX_W<'_>[src]

Bits 12:13 - Input data multiplexer for channel 2

pub fn datpack(&mut self) -> DATPACK_W<'_>[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>[src]

Bits 16:23 - Output serial clock divider

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>[src]

Bit 30 - Output serial clock source selection

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>[src]

Bit 31 - Global enable for DFSDM interface

impl W<u32, Reg<u32, _DFSDM_CHCFG3R1>>[src]

pub fn sitp(&mut self) -> SITP_W<'_>[src]

Bits 0:1 - Serial interface type for channel 3

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>[src]

Bits 2:3 - SPI clock select for channel 3

pub fn scden(&mut self) -> SCDEN_W<'_>[src]

Bit 5 - Short-circuit detector enable on channel 3

pub fn ckaben(&mut self) -> CKABEN_W<'_>[src]

Bit 6 - Clock absence detector enable on channel 3

pub fn chen(&mut self) -> CHEN_W<'_>[src]

Bit 7 - Channel 3 enable

pub fn chinsel(&mut self) -> CHINSEL_W<'_>[src]

Bit 8 - Channel inputs selection

pub fn datmpx(&mut self) -> DATMPX_W<'_>[src]

Bits 12:13 - Input data multiplexer for channel 3

pub fn datpack(&mut self) -> DATPACK_W<'_>[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>[src]

Bits 16:23 - Output serial clock divider

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>[src]

Bit 30 - Output serial clock source selection

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>[src]

Bit 31 - Global enable for DFSDM interface

impl W<u32, Reg<u32, _DFSDM_CHCFG4R1>>[src]

pub fn sitp(&mut self) -> SITP_W<'_>[src]

Bits 0:1 - Serial interface type for channel 4

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>[src]

Bits 2:3 - SPI clock select for channel 4

pub fn scden(&mut self) -> SCDEN_W<'_>[src]

Bit 5 - Short-circuit detector enable on channel 4

pub fn ckaben(&mut self) -> CKABEN_W<'_>[src]

Bit 6 - Clock absence detector enable on channel 4

pub fn chen(&mut self) -> CHEN_W<'_>[src]

Bit 7 - Channel 4 enable

pub fn chinsel(&mut self) -> CHINSEL_W<'_>[src]

Bit 8 - Channel inputs selection

pub fn datmpx(&mut self) -> DATMPX_W<'_>[src]

Bits 12:13 - Input data multiplexer for channel 4

pub fn datpack(&mut self) -> DATPACK_W<'_>[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>[src]

Bits 16:23 - Output serial clock divider

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>[src]

Bit 30 - Output serial clock source selection

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>[src]

Bit 31 - Global enable for DFSDM interface

impl W<u32, Reg<u32, _DFSDM_CHCFG5R1>>[src]

pub fn sitp(&mut self) -> SITP_W<'_>[src]

Bits 0:1 - Serial interface type for channel 5

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>[src]

Bits 2:3 - SPI clock select for channel 5

pub fn scden(&mut self) -> SCDEN_W<'_>[src]

Bit 5 - Short-circuit detector enable on channel 5

pub fn ckaben(&mut self) -> CKABEN_W<'_>[src]

Bit 6 - Clock absence detector enable on channel 5

pub fn chen(&mut self) -> CHEN_W<'_>[src]

Bit 7 - Channel 5 enable

pub fn chinsel(&mut self) -> CHINSEL_W<'_>[src]

Bit 8 - Channel inputs selection

pub fn datmpx(&mut self) -> DATMPX_W<'_>[src]

Bits 12:13 - Input data multiplexer for channel 5

pub fn datpack(&mut self) -> DATPACK_W<'_>[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>[src]

Bits 16:23 - Output serial clock divider

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>[src]

Bit 30 - Output serial clock source selection

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>[src]

Bit 31 - Global enable for DFSDM interface

impl W<u32, Reg<u32, _DFSDM_CHCFG6R1>>[src]

pub fn sitp(&mut self) -> SITP_W<'_>[src]

Bits 0:1 - Serial interface type for channel 6

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>[src]

Bits 2:3 - SPI clock select for channel 6

pub fn scden(&mut self) -> SCDEN_W<'_>[src]

Bit 5 - Short-circuit detector enable on channel 6

pub fn ckaben(&mut self) -> CKABEN_W<'_>[src]

Bit 6 - Clock absence detector enable on channel 6

pub fn chen(&mut self) -> CHEN_W<'_>[src]

Bit 7 - Channel 6 enable

pub fn chinsel(&mut self) -> CHINSEL_W<'_>[src]

Bit 8 - Channel inputs selection

pub fn datmpx(&mut self) -> DATMPX_W<'_>[src]

Bits 12:13 - Input data multiplexer for channel 6

pub fn datpack(&mut self) -> DATPACK_W<'_>[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>[src]

Bits 16:23 - Output serial clock divider

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>[src]

Bit 30 - Output serial clock source selection

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>[src]

Bit 31 - Global enable for DFSDM interface

impl W<u32, Reg<u32, _DFSDM_CHCFG7R1>>[src]

pub fn sitp(&mut self) -> SITP_W<'_>[src]

Bits 0:1 - Serial interface type for channel 7

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>[src]

Bits 2:3 - SPI clock select for channel 7

pub fn scden(&mut self) -> SCDEN_W<'_>[src]

Bit 5 - Short-circuit detector enable on channel 7

pub fn ckaben(&mut self) -> CKABEN_W<'_>[src]

Bit 6 - Clock absence detector enable on channel 7

pub fn chen(&mut self) -> CHEN_W<'_>[src]

Bit 7 - Channel 7 enable

pub fn chinsel(&mut self) -> CHINSEL_W<'_>[src]

Bit 8 - Channel inputs selection

pub fn datmpx(&mut self) -> DATMPX_W<'_>[src]

Bits 12:13 - Input data multiplexer for channel 7

pub fn datpack(&mut self) -> DATPACK_W<'_>[src]

Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>[src]

Bits 16:23 - Output serial clock divider

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>[src]

Bit 30 - Output serial clock source selection

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>[src]

Bit 31 - Global enable for DFSDM interface

impl W<u32, Reg<u32, _DFSDM_CHCFG0R2>>[src]

pub fn dtrbs(&mut self) -> DTRBS_W<'_>[src]

Bits 3:7 - Data right bit-shift for channel 0

pub fn offset(&mut self) -> OFFSET_W<'_>[src]

Bits 8:31 - 24-bit calibration offset for channel 0

impl W<u32, Reg<u32, _DFSDM_CHCFG1R2>>[src]

pub fn dtrbs(&mut self) -> DTRBS_W<'_>[src]

Bits 3:7 - Data right bit-shift for channel 1

pub fn offset(&mut self) -> OFFSET_W<'_>[src]

Bits 8:31 - 24-bit calibration offset for channel 1

impl W<u32, Reg<u32, _DFSDM_CHCFG2R2>>[src]

pub fn dtrbs(&mut self) -> DTRBS_W<'_>[src]

Bits 3:7 - Data right bit-shift for channel 2

pub fn offset(&mut self) -> OFFSET_W<'_>[src]

Bits 8:31 - 24-bit calibration offset for channel 2

impl W<u32, Reg<u32, _DFSDM_CHCFG3R2>>[src]

pub fn dtrbs(&mut self) -> DTRBS_W<'_>[src]

Bits 3:7 - Data right bit-shift for channel 3

pub fn offset(&mut self) -> OFFSET_W<'_>[src]

Bits 8:31 - 24-bit calibration offset for channel 3

impl W<u32, Reg<u32, _DFSDM_CHCFG4R2>>[src]

pub fn dtrbs(&mut self) -> DTRBS_W<'_>[src]

Bits 3:7 - Data right bit-shift for channel 4

pub fn offset(&mut self) -> OFFSET_W<'_>[src]

Bits 8:31 - 24-bit calibration offset for channel 4

impl W<u32, Reg<u32, _DFSDM_CHCFG5R2>>[src]

pub fn dtrbs(&mut self) -> DTRBS_W<'_>[src]

Bits 3:7 - Data right bit-shift for channel 5

pub fn offset(&mut self) -> OFFSET_W<'_>[src]

Bits 8:31 - 24-bit calibration offset for channel 5

impl W<u32, Reg<u32, _DFSDM_CHCFG6R2>>[src]

pub fn dtrbs(&mut self) -> DTRBS_W<'_>[src]

Bits 3:7 - Data right bit-shift for channel 6

pub fn offset(&mut self) -> OFFSET_W<'_>[src]

Bits 8:31 - 24-bit calibration offset for channel 6

impl W<u32, Reg<u32, _DFSDM_CHCFG7R2>>[src]

pub fn dtrbs(&mut self) -> DTRBS_W<'_>[src]

Bits 3:7 - Data right bit-shift for channel 7

pub fn offset(&mut self) -> OFFSET_W<'_>[src]

Bits 8:31 - 24-bit calibration offset for channel 7

impl W<u32, Reg<u32, _DFSDM_AWSCD0R>>[src]

pub fn scdt(&mut self) -> SCDT_W<'_>[src]

Bits 0:7 - short-circuit detector threshold for channel 0

pub fn bkscd(&mut self) -> BKSCD_W<'_>[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 0

pub fn awfosr(&mut self) -> AWFOSR_W<'_>[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 0

pub fn awford(&mut self) -> AWFORD_W<'_>[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 0

impl W<u32, Reg<u32, _DFSDM_AWSCD1R>>[src]

pub fn scdt(&mut self) -> SCDT_W<'_>[src]

Bits 0:7 - short-circuit detector threshold for channel 1

pub fn bkscd(&mut self) -> BKSCD_W<'_>[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 1

pub fn awfosr(&mut self) -> AWFOSR_W<'_>[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 1

pub fn awford(&mut self) -> AWFORD_W<'_>[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 1

impl W<u32, Reg<u32, _DFSDM_AWSCD2R>>[src]

pub fn scdt(&mut self) -> SCDT_W<'_>[src]

Bits 0:7 - short-circuit detector threshold for channel 2

pub fn bkscd(&mut self) -> BKSCD_W<'_>[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 2

pub fn awfosr(&mut self) -> AWFOSR_W<'_>[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 2

pub fn awford(&mut self) -> AWFORD_W<'_>[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 2

impl W<u32, Reg<u32, _DFSDM_AWSCD3R>>[src]

pub fn scdt(&mut self) -> SCDT_W<'_>[src]

Bits 0:7 - short-circuit detector threshold for channel 3

pub fn bkscd(&mut self) -> BKSCD_W<'_>[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 3

pub fn awfosr(&mut self) -> AWFOSR_W<'_>[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 3

pub fn awford(&mut self) -> AWFORD_W<'_>[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 3

impl W<u32, Reg<u32, _DFSDM_AWSCD4R>>[src]

pub fn scdt(&mut self) -> SCDT_W<'_>[src]

Bits 0:7 - short-circuit detector threshold for channel 4

pub fn bkscd(&mut self) -> BKSCD_W<'_>[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 4

pub fn awfosr(&mut self) -> AWFOSR_W<'_>[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 4

pub fn awford(&mut self) -> AWFORD_W<'_>[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 4

impl W<u32, Reg<u32, _DFSDM_AWSCD5R>>[src]

pub fn scdt(&mut self) -> SCDT_W<'_>[src]

Bits 0:7 - short-circuit detector threshold for channel 5

pub fn bkscd(&mut self) -> BKSCD_W<'_>[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 5

pub fn awfosr(&mut self) -> AWFOSR_W<'_>[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 5

pub fn awford(&mut self) -> AWFORD_W<'_>[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 5

impl W<u32, Reg<u32, _DFSDM_AWSCD6R>>[src]

pub fn scdt(&mut self) -> SCDT_W<'_>[src]

Bits 0:7 - short-circuit detector threshold for channel 6

pub fn bkscd(&mut self) -> BKSCD_W<'_>[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 6

pub fn awfosr(&mut self) -> AWFOSR_W<'_>[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 6

pub fn awford(&mut self) -> AWFORD_W<'_>[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 6

impl W<u32, Reg<u32, _DFSDM_AWSCD7R>>[src]

pub fn scdt(&mut self) -> SCDT_W<'_>[src]

Bits 0:7 - short-circuit detector threshold for channel 7

pub fn bkscd(&mut self) -> BKSCD_W<'_>[src]

Bits 12:15 - Break signal assignment for short-circuit detector on channel 7

pub fn awfosr(&mut self) -> AWFOSR_W<'_>[src]

Bits 16:20 - Analog watchdog filter oversampling ratio (decimation rate) on channel 7

pub fn awford(&mut self) -> AWFORD_W<'_>[src]

Bits 22:23 - Analog watchdog Sinc filter order on channel 7

impl W<u32, Reg<u32, _DFSDM_CHDATIN0R>>[src]

pub fn indat0(&mut self) -> INDAT0_W<'_>[src]

Bits 0:15 - Input data for channel 0

pub fn indat1(&mut self) -> INDAT1_W<'_>[src]

Bits 16:31 - Input data for channel 1

impl W<u32, Reg<u32, _DFSDM_CHDATIN1R>>[src]

pub fn indat0(&mut self) -> INDAT0_W<'_>[src]

Bits 0:15 - Input data for channel 1

pub fn indat1(&mut self) -> INDAT1_W<'_>[src]

Bits 16:31 - Input data for channel 2

impl W<u32, Reg<u32, _DFSDM_CHDATIN2R>>[src]

pub fn indat0(&mut self) -> INDAT0_W<'_>[src]

Bits 0:15 - Input data for channel 2

pub fn indat1(&mut self) -> INDAT1_W<'_>[src]

Bits 16:31 - Input data for channel 3

impl W<u32, Reg<u32, _DFSDM_CHDATIN3R>>[src]

pub fn indat0(&mut self) -> INDAT0_W<'_>[src]

Bits 0:15 - Input data for channel 3

pub fn indat1(&mut self) -> INDAT1_W<'_>[src]

Bits 16:31 - Input data for channel 4

impl W<u32, Reg<u32, _DFSDM_CHDATIN4R>>[src]

pub fn indat0(&mut self) -> INDAT0_W<'_>[src]

Bits 0:15 - Input data for channel 4

pub fn indat1(&mut self) -> INDAT1_W<'_>[src]

Bits 16:31 - Input data for channel 5

impl W<u32, Reg<u32, _DFSDM_CHDATIN5R>>[src]

pub fn indat0(&mut self) -> INDAT0_W<'_>[src]

Bits 0:15 - Input data for channel 5

pub fn indat1(&mut self) -> INDAT1_W<'_>[src]

Bits 16:31 - Input data for channel 6

impl W<u32, Reg<u32, _DFSDM_CHDATIN6R>>[src]

pub fn indat0(&mut self) -> INDAT0_W<'_>[src]

Bits 0:15 - Input data for channel 6

pub fn indat1(&mut self) -> INDAT1_W<'_>[src]

Bits 16:31 - Input data for channel 7

impl W<u32, Reg<u32, _DFSDM_CHDATIN7R>>[src]

pub fn indat0(&mut self) -> INDAT0_W<'_>[src]

Bits 0:15 - Input data for channel 7

pub fn indat1(&mut self) -> INDAT1_W<'_>[src]

Bits 16:31 - Input data for channel 8

impl W<u32, Reg<u32, _DFSDM0_CR1>>[src]

pub fn dfen(&mut self) -> DFEN_W<'_>[src]

Bit 0 - DFSDM enable

pub fn jswstart(&mut self) -> JSWSTART_W<'_>[src]

Bit 1 - Start a conversion of the injected group of channels

pub fn jsync(&mut self) -> JSYNC_W<'_>[src]

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jscan(&mut self) -> JSCAN_W<'_>[src]

Bit 4 - Scanning conversion mode for injected conversions

pub fn jdmaen(&mut self) -> JDMAEN_W<'_>[src]

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>[src]

Bits 8:12 - Trigger signal selection for launching injected conversions

pub fn jexten(&mut self) -> JEXTEN_W<'_>[src]

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn rswstart(&mut self) -> RSWSTART_W<'_>[src]

Bit 17 - Software start of a conversion on the regular channel

pub fn rcont(&mut self) -> RCONT_W<'_>[src]

Bit 18 - Continuous mode selection for regular conversions

pub fn rsync(&mut self) -> RSYNC_W<'_>[src]

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rdmaen(&mut self) -> RDMAEN_W<'_>[src]

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rch(&mut self) -> RCH_W<'_>[src]

Bits 24:26 - Regular channel selection

pub fn fast(&mut self) -> FAST_W<'_>[src]

Bit 29 - Fast conversion mode selection for regular conversions

pub fn awfsel(&mut self) -> AWFSEL_W<'_>[src]

Bit 30 - Analog watchdog fast mode select

impl W<u32, Reg<u32, _DFSDM1_CR1>>[src]

pub fn dfen(&mut self) -> DFEN_W<'_>[src]

Bit 0 - DFSDM enable

pub fn jswstart(&mut self) -> JSWSTART_W<'_>[src]

Bit 1 - Start a conversion of the injected group of channels

pub fn jsync(&mut self) -> JSYNC_W<'_>[src]

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jscan(&mut self) -> JSCAN_W<'_>[src]

Bit 4 - Scanning conversion mode for injected conversions

pub fn jdmaen(&mut self) -> JDMAEN_W<'_>[src]

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>[src]

Bits 8:12 - Trigger signal selection for launching injected conversions

pub fn jexten(&mut self) -> JEXTEN_W<'_>[src]

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn rswstart(&mut self) -> RSWSTART_W<'_>[src]

Bit 17 - Software start of a conversion on the regular channel

pub fn rcont(&mut self) -> RCONT_W<'_>[src]

Bit 18 - Continuous mode selection for regular conversions

pub fn rsync(&mut self) -> RSYNC_W<'_>[src]

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rdmaen(&mut self) -> RDMAEN_W<'_>[src]

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rch(&mut self) -> RCH_W<'_>[src]

Bits 24:26 - Regular channel selection

pub fn fast(&mut self) -> FAST_W<'_>[src]

Bit 29 - Fast conversion mode selection for regular conversions

pub fn awfsel(&mut self) -> AWFSEL_W<'_>[src]

Bit 30 - Analog watchdog fast mode select

impl W<u32, Reg<u32, _DFSDM2_CR1>>[src]

pub fn dfen(&mut self) -> DFEN_W<'_>[src]

Bit 0 - DFSDM enable

pub fn jswstart(&mut self) -> JSWSTART_W<'_>[src]

Bit 1 - Start a conversion of the injected group of channels

pub fn jsync(&mut self) -> JSYNC_W<'_>[src]

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jscan(&mut self) -> JSCAN_W<'_>[src]

Bit 4 - Scanning conversion mode for injected conversions

pub fn jdmaen(&mut self) -> JDMAEN_W<'_>[src]

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>[src]

Bits 8:12 - Trigger signal selection for launching injected conversions

pub fn jexten(&mut self) -> JEXTEN_W<'_>[src]

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn rswstart(&mut self) -> RSWSTART_W<'_>[src]

Bit 17 - Software start of a conversion on the regular channel

pub fn rcont(&mut self) -> RCONT_W<'_>[src]

Bit 18 - Continuous mode selection for regular conversions

pub fn rsync(&mut self) -> RSYNC_W<'_>[src]

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rdmaen(&mut self) -> RDMAEN_W<'_>[src]

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rch(&mut self) -> RCH_W<'_>[src]

Bits 24:26 - Regular channel selection

pub fn fast(&mut self) -> FAST_W<'_>[src]

Bit 29 - Fast conversion mode selection for regular conversions

pub fn awfsel(&mut self) -> AWFSEL_W<'_>[src]

Bit 30 - Analog watchdog fast mode select

impl W<u32, Reg<u32, _DFSDM3_CR1>>[src]

pub fn dfen(&mut self) -> DFEN_W<'_>[src]

Bit 0 - DFSDM enable

pub fn jswstart(&mut self) -> JSWSTART_W<'_>[src]

Bit 1 - Start a conversion of the injected group of channels

pub fn jsync(&mut self) -> JSYNC_W<'_>[src]

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jscan(&mut self) -> JSCAN_W<'_>[src]

Bit 4 - Scanning conversion mode for injected conversions

pub fn jdmaen(&mut self) -> JDMAEN_W<'_>[src]

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>[src]

Bits 8:12 - Trigger signal selection for launching injected conversions

pub fn jexten(&mut self) -> JEXTEN_W<'_>[src]

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn rswstart(&mut self) -> RSWSTART_W<'_>[src]

Bit 17 - Software start of a conversion on the regular channel

pub fn rcont(&mut self) -> RCONT_W<'_>[src]

Bit 18 - Continuous mode selection for regular conversions

pub fn rsync(&mut self) -> RSYNC_W<'_>[src]

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rdmaen(&mut self) -> RDMAEN_W<'_>[src]

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rch(&mut self) -> RCH_W<'_>[src]

Bits 24:26 - Regular channel selection

pub fn fast(&mut self) -> FAST_W<'_>[src]

Bit 29 - Fast conversion mode selection for regular conversions

pub fn awfsel(&mut self) -> AWFSEL_W<'_>[src]

Bit 30 - Analog watchdog fast mode select

impl W<u32, Reg<u32, _DFSDM0_CR2>>[src]

pub fn jeocie(&mut self) -> JEOCIE_W<'_>[src]

Bit 0 - Injected end of conversion interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>[src]

Bit 1 - Regular end of conversion interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>[src]

Bit 2 - Injected data overrun interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>[src]

Bit 3 - Regular data overrun interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>[src]

Bit 4 - Analog watchdog interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>[src]

Bit 5 - Short-circuit detector interrupt enable

pub fn ckabie(&mut self) -> CKABIE_W<'_>[src]

Bit 6 - Clock absence interrupt enable

pub fn exch(&mut self) -> EXCH_W<'_>[src]

Bits 8:15 - Extremes detector channel selection

pub fn awdch(&mut self) -> AWDCH_W<'_>[src]

Bits 16:23 - Analog watchdog channel selection

impl W<u32, Reg<u32, _DFSDM1_CR2>>[src]

pub fn jeocie(&mut self) -> JEOCIE_W<'_>[src]

Bit 0 - Injected end of conversion interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>[src]

Bit 1 - Regular end of conversion interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>[src]

Bit 2 - Injected data overrun interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>[src]

Bit 3 - Regular data overrun interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>[src]

Bit 4 - Analog watchdog interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>[src]

Bit 5 - Short-circuit detector interrupt enable

pub fn ckabie(&mut self) -> CKABIE_W<'_>[src]

Bit 6 - Clock absence interrupt enable

pub fn exch(&mut self) -> EXCH_W<'_>[src]

Bits 8:15 - Extremes detector channel selection

pub fn awdch(&mut self) -> AWDCH_W<'_>[src]

Bits 16:23 - Analog watchdog channel selection

impl W<u32, Reg<u32, _DFSDM2_CR2>>[src]

pub fn jeocie(&mut self) -> JEOCIE_W<'_>[src]

Bit 0 - Injected end of conversion interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>[src]

Bit 1 - Regular end of conversion interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>[src]

Bit 2 - Injected data overrun interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>[src]

Bit 3 - Regular data overrun interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>[src]

Bit 4 - Analog watchdog interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>[src]

Bit 5 - Short-circuit detector interrupt enable

pub fn ckabie(&mut self) -> CKABIE_W<'_>[src]

Bit 6 - Clock absence interrupt enable

pub fn exch(&mut self) -> EXCH_W<'_>[src]

Bits 8:15 - Extremes detector channel selection

pub fn awdch(&mut self) -> AWDCH_W<'_>[src]

Bits 16:23 - Analog watchdog channel selection

impl W<u32, Reg<u32, _DFSDM3_CR2>>[src]

pub fn jeocie(&mut self) -> JEOCIE_W<'_>[src]

Bit 0 - Injected end of conversion interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>[src]

Bit 1 - Regular end of conversion interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>[src]

Bit 2 - Injected data overrun interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>[src]

Bit 3 - Regular data overrun interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>[src]

Bit 4 - Analog watchdog interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>[src]

Bit 5 - Short-circuit detector interrupt enable

pub fn ckabie(&mut self) -> CKABIE_W<'_>[src]

Bit 6 - Clock absence interrupt enable

pub fn exch(&mut self) -> EXCH_W<'_>[src]

Bits 8:15 - Extremes detector channel selection

pub fn awdch(&mut self) -> AWDCH_W<'_>[src]

Bits 16:23 - Analog watchdog channel selection

impl W<u32, Reg<u32, _DFSDM0_ICR>>[src]

pub fn clrjovrf(&mut self) -> CLRJOVRF_W<'_>[src]

Bit 2 - Clear the injected conversion overrun flag

pub fn clrrovrf(&mut self) -> CLRROVRF_W<'_>[src]

Bit 3 - Clear the regular conversion overrun flag

pub fn clrckabf(&mut self) -> CLRCKABF_W<'_>[src]

Bits 16:23 - Clear the clock absence flag

pub fn clrscdf(&mut self) -> CLRSCDF_W<'_>[src]

Bits 24:31 - Clear the short-circuit detector flag

impl W<u32, Reg<u32, _DFSDM1_ICR>>[src]

pub fn clrjovrf(&mut self) -> CLRJOVRF_W<'_>[src]

Bit 2 - Clear the injected conversion overrun flag

pub fn clrrovrf(&mut self) -> CLRROVRF_W<'_>[src]

Bit 3 - Clear the regular conversion overrun flag

pub fn clrckabf(&mut self) -> CLRCKABF_W<'_>[src]

Bits 16:23 - Clear the clock absence flag

pub fn clrscdf(&mut self) -> CLRSCDF_W<'_>[src]

Bits 24:31 - Clear the short-circuit detector flag

impl W<u32, Reg<u32, _DFSDM2_ICR>>[src]

pub fn clrjovrf(&mut self) -> CLRJOVRF_W<'_>[src]

Bit 2 - Clear the injected conversion overrun flag

pub fn clrrovrf(&mut self) -> CLRROVRF_W<'_>[src]

Bit 3 - Clear the regular conversion overrun flag

pub fn clrckabf(&mut self) -> CLRCKABF_W<'_>[src]

Bits 16:23 - Clear the clock absence flag

pub fn clrscdf(&mut self) -> CLRSCDF_W<'_>[src]

Bits 24:31 - Clear the short-circuit detector flag

impl W<u32, Reg<u32, _DFSDM3_ICR>>[src]

pub fn clrjovrf(&mut self) -> CLRJOVRF_W<'_>[src]

Bit 2 - Clear the injected conversion overrun flag

pub fn clrrovrf(&mut self) -> CLRROVRF_W<'_>[src]

Bit 3 - Clear the regular conversion overrun flag

pub fn clrckabf(&mut self) -> CLRCKABF_W<'_>[src]

Bits 16:23 - Clear the clock absence flag

pub fn clrscdf(&mut self) -> CLRSCDF_W<'_>[src]

Bits 24:31 - Clear the short-circuit detector flag

impl W<u32, Reg<u32, _DFSDM0_JCHGR>>[src]

pub fn jchg(&mut self) -> JCHG_W<'_>[src]

Bits 0:7 - Injected channel group selection

impl W<u32, Reg<u32, _DFSDM1_JCHGR>>[src]

pub fn jchg(&mut self) -> JCHG_W<'_>[src]

Bits 0:7 - Injected channel group selection

impl W<u32, Reg<u32, _DFSDM2_JCHGR>>[src]

pub fn jchg(&mut self) -> JCHG_W<'_>[src]

Bits 0:7 - Injected channel group selection

impl W<u32, Reg<u32, _DFSDM3_JCHGR>>[src]

pub fn jchg(&mut self) -> JCHG_W<'_>[src]

Bits 0:7 - Injected channel group selection

impl W<u32, Reg<u32, _DFSDM0_FCR>>[src]

pub fn iosr(&mut self) -> IOSR_W<'_>[src]

Bits 0:7 - Integrator oversampling ratio (averaging length)

pub fn fosr(&mut self) -> FOSR_W<'_>[src]

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

pub fn ford(&mut self) -> FORD_W<'_>[src]

Bits 29:31 - Sinc filter order

impl W<u32, Reg<u32, _DFSDM1_FCR>>[src]

pub fn iosr(&mut self) -> IOSR_W<'_>[src]

Bits 0:7 - Integrator oversampling ratio (averaging length)

pub fn fosr(&mut self) -> FOSR_W<'_>[src]

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

pub fn ford(&mut self) -> FORD_W<'_>[src]

Bits 29:31 - Sinc filter order

impl W<u32, Reg<u32, _DFSDM2_FCR>>[src]

pub fn iosr(&mut self) -> IOSR_W<'_>[src]

Bits 0:7 - Integrator oversampling ratio (averaging length)

pub fn fosr(&mut self) -> FOSR_W<'_>[src]

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

pub fn ford(&mut self) -> FORD_W<'_>[src]

Bits 29:31 - Sinc filter order

impl W<u32, Reg<u32, _DFSDM3_FCR>>[src]

pub fn iosr(&mut self) -> IOSR_W<'_>[src]

Bits 0:7 - Integrator oversampling ratio (averaging length)

pub fn fosr(&mut self) -> FOSR_W<'_>[src]

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

pub fn ford(&mut self) -> FORD_W<'_>[src]

Bits 29:31 - Sinc filter order

impl W<u32, Reg<u32, _DFSDM0_AWHTR>>[src]

pub fn bkawh(&mut self) -> BKAWH_W<'_>[src]

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

pub fn awht(&mut self) -> AWHT_W<'_>[src]

Bits 8:31 - Analog watchdog high threshold

impl W<u32, Reg<u32, _DFSDM1_AWHTR>>[src]

pub fn bkawh(&mut self) -> BKAWH_W<'_>[src]

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

pub fn awht(&mut self) -> AWHT_W<'_>[src]

Bits 8:31 - Analog watchdog high threshold

impl W<u32, Reg<u32, _DFSDM2_AWHTR>>[src]

pub fn bkawh(&mut self) -> BKAWH_W<'_>[src]

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

pub fn awht(&mut self) -> AWHT_W<'_>[src]

Bits 8:31 - Analog watchdog high threshold

impl W<u32, Reg<u32, _DFSDM3_AWHTR>>[src]

pub fn bkawh(&mut self) -> BKAWH_W<'_>[src]

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

pub fn awht(&mut self) -> AWHT_W<'_>[src]

Bits 8:31 - Analog watchdog high threshold

impl W<u32, Reg<u32, _DFSDM0_AWLTR>>[src]

pub fn bkawl(&mut self) -> BKAWL_W<'_>[src]

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

pub fn awlt(&mut self) -> AWLT_W<'_>[src]

Bits 8:31 - Analog watchdog low threshold

impl W<u32, Reg<u32, _DFSDM1_AWLTR>>[src]

pub fn bkawl(&mut self) -> BKAWL_W<'_>[src]

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

pub fn awlt(&mut self) -> AWLT_W<'_>[src]

Bits 8:31 - Analog watchdog low threshold

impl W<u32, Reg<u32, _DFSDM2_AWLTR>>[src]

pub fn bkawl(&mut self) -> BKAWL_W<'_>[src]

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

pub fn awlt(&mut self) -> AWLT_W<'_>[src]

Bits 8:31 - Analog watchdog low threshold

impl W<u32, Reg<u32, _DFSDM3_AWLTR>>[src]

pub fn bkawl(&mut self) -> BKAWL_W<'_>[src]

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

pub fn awlt(&mut self) -> AWLT_W<'_>[src]

Bits 8:31 - Analog watchdog low threshold

impl W<u32, Reg<u32, _DFSDM0_AWCFR>>[src]

pub fn clrawltf(&mut self) -> CLRAWLTF_W<'_>[src]

Bits 0:7 - Clear the analog watchdog low threshold flag

pub fn clrawhtf(&mut self) -> CLRAWHTF_W<'_>[src]

Bits 8:15 - Clear the analog watchdog high threshold flag

impl W<u32, Reg<u32, _DFSDM1_AWCFR>>[src]

pub fn clrawltf(&mut self) -> CLRAWLTF_W<'_>[src]

Bits 0:7 - Clear the analog watchdog low threshold flag

pub fn clrawhtf(&mut self) -> CLRAWHTF_W<'_>[src]

Bits 8:15 - Clear the analog watchdog high threshold flag

impl W<u32, Reg<u32, _DFSDM2_AWCFR>>[src]

pub fn clrawltf(&mut self) -> CLRAWLTF_W<'_>[src]

Bits 0:7 - Clear the analog watchdog low threshold flag

pub fn clrawhtf(&mut self) -> CLRAWHTF_W<'_>[src]

Bits 8:15 - Clear the analog watchdog high threshold flag

impl W<u32, Reg<u32, _DFSDM3_AWCFR>>[src]

pub fn clrawltf(&mut self) -> CLRAWLTF_W<'_>[src]

Bits 0:7 - Clear the analog watchdog low threshold flag

pub fn clrawhtf(&mut self) -> CLRAWHTF_W<'_>[src]

Bits 8:15 - Clear the analog watchdog high threshold flag

impl W<u32, Reg<u32, _JPEG_CONFR0>>[src]

pub fn start(&mut self) -> START_W<'_>[src]

Bit 0 - Start

impl W<u32, Reg<u32, _JPEG_CONFR1>>[src]

pub fn nf(&mut self) -> NF_W<'_>[src]

Bits 0:1 - Number of color components

pub fn de(&mut self) -> DE_W<'_>[src]

Bit 3 - Decoding Enable

pub fn colorspace(&mut self) -> COLORSPACE_W<'_>[src]

Bits 4:5 - Color Space

pub fn ns(&mut self) -> NS_W<'_>[src]

Bits 6:7 - Number of components for Scan

pub fn hdr(&mut self) -> HDR_W<'_>[src]

Bit 8 - Header Processing

pub fn ysize(&mut self) -> YSIZE_W<'_>[src]

Bits 16:31 - Y Size

impl W<u32, Reg<u32, _JPEG_CONFR2>>[src]

pub fn nmcu(&mut self) -> NMCU_W<'_>[src]

Bits 0:25 - Number of MCU

impl W<u32, Reg<u32, _JPEG_CONFR3>>[src]

pub fn xsize(&mut self) -> XSIZE_W<'_>[src]

Bits 16:31 - X size

impl W<u32, Reg<u32, _JPEG_CONFR4>>[src]

pub fn hd(&mut self) -> HD_W<'_>[src]

Bit 0 - Huffman DC

pub fn ha(&mut self) -> HA_W<'_>[src]

Bit 1 - Huffman AC

pub fn qt(&mut self) -> QT_W<'_>[src]

Bits 2:3 - Quantization Table

pub fn nb(&mut self) -> NB_W<'_>[src]

Bits 4:7 - Number of Block

pub fn vsf(&mut self) -> VSF_W<'_>[src]

Bits 8:11 - Vertical Sampling Factor

pub fn hsf(&mut self) -> HSF_W<'_>[src]

Bits 12:15 - Horizontal Sampling Factor

impl W<u32, Reg<u32, _JPEG_CONFR5>>[src]

pub fn hd(&mut self) -> HD_W<'_>[src]

Bit 0 - Huffman DC

pub fn ha(&mut self) -> HA_W<'_>[src]

Bit 1 - Huffman AC

pub fn qt(&mut self) -> QT_W<'_>[src]

Bits 2:3 - Quantization Table

pub fn nb(&mut self) -> NB_W<'_>[src]

Bits 4:7 - Number of Block

pub fn vsf(&mut self) -> VSF_W<'_>[src]

Bits 8:11 - Vertical Sampling Factor

pub fn hsf(&mut self) -> HSF_W<'_>[src]

Bits 12:15 - Horizontal Sampling Factor

impl W<u32, Reg<u32, _JPEG_CONFR6>>[src]

pub fn hd(&mut self) -> HD_W<'_>[src]

Bit 0 - Huffman DC

pub fn ha(&mut self) -> HA_W<'_>[src]

Bit 1 - Huffman AC

pub fn qt(&mut self) -> QT_W<'_>[src]

Bits 2:3 - Quantization Table

pub fn nb(&mut self) -> NB_W<'_>[src]

Bits 4:7 - Number of Block

pub fn vsf(&mut self) -> VSF_W<'_>[src]

Bits 8:11 - Vertical Sampling Factor

pub fn hsf(&mut self) -> HSF_W<'_>[src]

Bits 12:15 - Horizontal Sampling Factor

impl W<u32, Reg<u32, _JPEG_CONFR7>>[src]

pub fn hd(&mut self) -> HD_W<'_>[src]

Bit 0 - Huffman DC

pub fn ha(&mut self) -> HA_W<'_>[src]

Bit 1 - Huffman AC

pub fn qt(&mut self) -> QT_W<'_>[src]

Bits 2:3 - Quantization Table

pub fn nb(&mut self) -> NB_W<'_>[src]

Bits 4:7 - Number of Block

pub fn vsf(&mut self) -> VSF_W<'_>[src]

Bits 8:11 - Vertical Sampling Factor

pub fn hsf(&mut self) -> HSF_W<'_>[src]

Bits 12:15 - Horizontal Sampling Factor

impl W<u32, Reg<u32, _JPEG_CR>>[src]

pub fn jcen(&mut self) -> JCEN_W<'_>[src]

Bit 0 - JPEG Core Enable

pub fn iftie(&mut self) -> IFTIE_W<'_>[src]

Bit 1 - Input FIFO Threshold Interrupt Enable

pub fn ifnfie(&mut self) -> IFNFIE_W<'_>[src]

Bit 2 - Input FIFO Not Full Interrupt Enable

pub fn oftie(&mut self) -> OFTIE_W<'_>[src]

Bit 3 - Output FIFO Threshold Interrupt Enable

pub fn ofneie(&mut self) -> OFNEIE_W<'_>[src]

Bit 4 - Output FIFO Not Empty Interrupt Enable

pub fn eocie(&mut self) -> EOCIE_W<'_>[src]

Bit 5 - End of Conversion Interrupt Enable

pub fn hpdie(&mut self) -> HPDIE_W<'_>[src]

Bit 6 - Header Parsing Done Interrupt Enable

pub fn idmaen(&mut self) -> IDMAEN_W<'_>[src]

Bit 11 - Input DMA Enable

pub fn odmaen(&mut self) -> ODMAEN_W<'_>[src]

Bit 12 - Output DMA Enable

impl W<u32, Reg<u32, _JPEG_CFR>>[src]

pub fn ceocf(&mut self) -> CEOCF_W<'_>[src]

Bit 5 - Clear End of Conversion Flag

pub fn chpdf(&mut self) -> CHPDF_W<'_>[src]

Bit 6 - Clear Header Parsing Done Flag

impl W<u32, Reg<u32, _JPEG_DIR>>[src]

pub fn datain(&mut self) -> DATAIN_W<'_>[src]

Bits 0:31 - Data Input FIFO

impl W<u32, Reg<u32, _QMEM0_0>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_1>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_2>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_3>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_4>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_5>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_6>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_7>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_8>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_9>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_10>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_11>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_12>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_13>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_14>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM0_15>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_0>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_1>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_2>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_3>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_4>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_5>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_6>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_7>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_8>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_9>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_10>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_11>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_12>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_13>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_14>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM1_15>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_0>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_1>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_2>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_3>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_4>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_5>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_6>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_7>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_8>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_9>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_10>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_11>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_12>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_13>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_14>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM2_15>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_0>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_1>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_2>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_3>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_4>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_5>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_6>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_7>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_8>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_9>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_10>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_11>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_12>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_13>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_14>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _QMEM3_15>>[src]

pub fn qmem_ram(&mut self) -> QMEM_RAM_W<'_>[src]

Bits 0:31 - QMem RAM

impl W<u32, Reg<u32, _HUFFMIN_0>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_1>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_2>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_3>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_4>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_5>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_6>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_7>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_8>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_9>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_10>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_11>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_12>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_13>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_14>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFMIN_15>>[src]

pub fn huff_min_ram(&mut self) -> HUFFMIN_RAM_W<'_>[src]

Bits 0:31 - HuffMin RAM

impl W<u32, Reg<u32, _HUFFBASE0>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE1>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE2>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE3>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE4>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE5>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE6>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE7>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE8>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE9>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE10>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE11>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE12>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE13>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE14>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE15>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE16>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE17>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE18>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE19>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE20>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE21>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE22>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE23>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE24>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE25>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE26>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE27>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE28>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE29>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE30>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFBASE31>>[src]

pub fn huff_base_ram_0(&mut self) -> HUFFBASE_RAM_0_W<'_>[src]

Bits 0:8 - HuffBase RAM

pub fn huff_base_ram_1(&mut self) -> HUFFBASE_RAM_1_W<'_>[src]

Bits 16:24 - HuffBase RAM

impl W<u32, Reg<u32, _HUFFSYMB0>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB1>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB2>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB3>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB4>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB5>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB6>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB7>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB8>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB9>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB10>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB11>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB12>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB13>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB14>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB15>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB16>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB17>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB18>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB19>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB20>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB21>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB22>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB23>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB24>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB25>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB26>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB27>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB28>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB29>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB30>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB31>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB32>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB33>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB34>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB35>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB36>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB37>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB38>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB39>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB40>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB41>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB42>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB43>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB44>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB45>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB46>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB47>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB48>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB49>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB50>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB51>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB52>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB53>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB54>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB55>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB56>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB57>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB58>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB59>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB60>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB61>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB62>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB63>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB64>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB65>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB66>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB67>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB68>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB69>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB70>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB71>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB72>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB73>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB74>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB75>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB76>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB77>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB78>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB79>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB80>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB81>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB82>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _HUFFSYMB83>>[src]

pub fn huff_symb_ram(&mut self) -> HUFFSYMB_RAM_W<'_>[src]

Bits 0:31 - DHTSymb RAM

impl W<u32, Reg<u32, _DHTMEM0>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM2>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM3>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM4>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM5>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM6>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM7>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM8>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM9>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM10>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM11>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM12>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM13>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM14>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM15>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM16>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM17>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM18>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM19>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM20>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM21>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM22>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM23>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM24>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM25>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM26>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM27>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM28>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM29>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM30>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM31>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM32>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM33>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM34>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM35>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM36>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM37>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM38>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM39>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM40>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM41>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM42>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM43>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM44>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM45>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM46>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM47>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM48>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM49>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM50>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM51>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM52>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM53>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM54>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM55>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM56>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM57>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM58>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM59>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM60>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM61>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM62>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM63>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM64>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM65>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM66>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM67>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM68>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM69>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM70>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM71>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM72>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM73>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM74>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM75>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM76>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM77>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM78>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM79>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM80>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM81>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM82>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM83>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM84>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM85>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM86>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM87>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM88>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM89>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM90>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM91>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM92>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM93>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM94>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM95>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM96>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM97>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM98>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM99>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM100>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM101>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM102>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _DHTMEM103>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_0>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_1>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_2>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_3>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_4>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_5>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_6>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_7>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_8>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_9>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_10>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_11>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_12>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_13>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_14>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_15>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_16>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_17>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_18>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_19>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_20>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_21>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_22>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_23>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_24>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_25>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_26>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_27>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_28>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_29>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_30>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_31>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_32>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_33>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_34>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_35>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_36>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_37>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_38>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_39>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_40>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_41>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_42>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_43>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_44>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_45>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_46>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_47>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_48>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_49>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_50>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_51>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_52>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_53>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_54>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_55>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_56>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_57>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_58>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_59>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_60>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_61>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_62>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_63>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_64>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_65>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_66>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_67>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_68>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_69>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_70>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_71>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_72>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_73>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_74>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_75>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_76>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_77>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_78>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_79>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_80>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_81>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_82>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_83>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_84>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_85>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_86>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC0_87>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_0>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_1>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_2>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_3>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_4>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_5>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_6>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_7>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_8>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_9>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_10>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_11>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_12>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_13>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_14>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_15>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_16>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_17>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_18>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_19>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_20>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_21>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_22>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_23>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_24>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_25>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_26>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_27>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_28>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_29>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_30>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_31>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_32>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_33>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_34>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_35>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_36>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_37>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_38>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_39>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_40>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_41>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_42>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_43>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_44>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_45>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_46>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_47>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_48>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_49>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_50>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_51>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_52>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_53>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_54>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_55>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_56>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_57>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_58>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_59>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_60>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_61>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_62>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_63>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_64>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_65>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_66>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_67>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_68>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_69>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_70>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_71>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_72>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_73>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_74>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_75>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_76>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_77>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_78>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_79>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_80>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_81>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_82>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_83>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_84>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_85>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_86>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_AC1_87>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC0_0>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC0_1>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC0_2>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC0_3>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC0_4>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC0_5>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC0_6>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC0_7>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC1_0>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC1_1>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC1_2>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC1_3>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC1_4>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC1_5>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC1_6>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _HUFFENC_DC1_7>>[src]

pub fn dhtmem_ram(&mut self) -> DHTMEM_RAM_W<'_>[src]

Bits 0:31 - DHTMem RAM

impl W<u32, Reg<u32, _MMCCR>>[src]

pub fn cr(&mut self) -> CR_W<'_>[src]

Bit 0 - Counter reset

pub fn csr(&mut self) -> CSR_W<'_>[src]

Bit 1 - Counter stop rollover

pub fn ror(&mut self) -> ROR_W<'_>[src]

Bit 2 - Reset on read

pub fn mcf(&mut self) -> MCF_W<'_>[src]

Bit 3 - MMC counter freeze

pub fn mcp(&mut self) -> MCP_W<'_>[src]

Bit 4 - MMC counter preset

pub fn mcfhp(&mut self) -> MCFHP_W<'_>[src]

Bit 5 - MMC counter Full-Half preset

impl W<u32, Reg<u32, _MMCRIR>>[src]

pub fn rfces(&mut self) -> RFCES_W<'_>[src]

Bit 5 - Received frames CRC error status

pub fn rfaes(&mut self) -> RFAES_W<'_>[src]

Bit 6 - Received frames alignment error status

pub fn rgufs(&mut self) -> RGUFS_W<'_>[src]

Bit 17 - Received good Unicast frames status

impl W<u32, Reg<u32, _MMCRIMR>>[src]

pub fn rfcem(&mut self) -> RFCEM_W<'_>[src]

Bit 5 - Received frame CRC error mask

pub fn rfaem(&mut self) -> RFAEM_W<'_>[src]

Bit 6 - Received frames alignment error mask

pub fn rgufm(&mut self) -> RGUFM_W<'_>[src]

Bit 17 - Received good Unicast frames mask

impl W<u32, Reg<u32, _MMCTIMR>>[src]

pub fn tgfscm(&mut self) -> TGFSCM_W<'_>[src]

Bit 14 - Transmitted good frames single collision mask

pub fn tgfmscm(&mut self) -> TGFMSCM_W<'_>[src]

Bit 15 - Transmitted good frames more than single collision mask

pub fn tgfm(&mut self) -> TGFM_W<'_>[src]

Bit 16 - Transmitted good frames mask

impl W<u32, Reg<u32, _PTPTSCR>>[src]

pub fn tse(&mut self) -> TSE_W<'_>[src]

Bit 0 - TSE

pub fn tsfcu(&mut self) -> TSFCU_W<'_>[src]

Bit 1 - TSFCU

pub fn tsptppsv2e(&mut self) -> TSPTPPSV2E_W<'_>[src]

Bit 10 - TSPTPPSV2E

pub fn tssptpoefe(&mut self) -> TSSPTPOEFE_W<'_>[src]

Bit 11 - TSSPTPOEFE

pub fn tssipv6fe(&mut self) -> TSSIPV6FE_W<'_>[src]

Bit 12 - TSSIPV6FE

pub fn tssipv4fe(&mut self) -> TSSIPV4FE_W<'_>[src]

Bit 13 - TSSIPV4FE

pub fn tsseme(&mut self) -> TSSEME_W<'_>[src]

Bit 14 - TSSEME

pub fn tssmrme(&mut self) -> TSSMRME_W<'_>[src]

Bit 15 - TSSMRME

pub fn tscnt(&mut self) -> TSCNT_W<'_>[src]

Bits 16:17 - TSCNT

pub fn tspffmae(&mut self) -> TSPFFMAE_W<'_>[src]

Bit 18 - TSPFFMAE

pub fn tssti(&mut self) -> TSSTI_W<'_>[src]

Bit 2 - TSSTI

pub fn tsstu(&mut self) -> TSSTU_W<'_>[src]

Bit 3 - TSSTU

pub fn tsite(&mut self) -> TSITE_W<'_>[src]

Bit 4 - TSITE

pub fn ttsaru(&mut self) -> TTSARU_W<'_>[src]

Bit 5 - TTSARU

pub fn tssarfe(&mut self) -> TSSARFE_W<'_>[src]

Bit 8 - TSSARFE

pub fn tsssr(&mut self) -> TSSSR_W<'_>[src]

Bit 9 - TSSSR

impl W<u32, Reg<u32, _PTPSSIR>>[src]

pub fn stssi(&mut self) -> STSSI_W<'_>[src]

Bits 0:7 - STSSI

impl W<u32, Reg<u32, _PTPTSHUR>>[src]

pub fn tsus(&mut self) -> TSUS_W<'_>[src]

Bits 0:31 - TSUS

impl W<u32, Reg<u32, _PTPTSLUR>>[src]

pub fn tsuss(&mut self) -> TSUSS_W<'_>[src]

Bits 0:30 - TSUSS

pub fn tsupns(&mut self) -> TSUPNS_W<'_>[src]

Bit 31 - TSUPNS

impl W<u32, Reg<u32, _PTPTSAR>>[src]

pub fn tsa(&mut self) -> TSA_W<'_>[src]

Bits 0:31 - TSA

impl W<u32, Reg<u32, _PTPTTHR>>[src]

pub fn ttsh(&mut self) -> TTSH_W<'_>[src]

Bits 0:31 - 0

impl W<u32, Reg<u32, _PTPTTLR>>[src]

pub fn ttsl(&mut self) -> TTSL_W<'_>[src]

Bits 0:31 - TTSL

impl W<u32, Reg<u32, _DMABMR>>[src]

pub fn sr(&mut self) -> SR_W<'_>[src]

Bit 0 - Software reset

pub fn da(&mut self) -> DA_W<'_>[src]

Bit 1 - DMA arbitration

pub fn dsl(&mut self) -> DSL_W<'_>[src]

Bits 2:6 - Descriptor skip length

pub fn edfe(&mut self) -> EDFE_W<'_>[src]

Bit 7 - Enhanced descriptor format enable

pub fn pbl(&mut self) -> PBL_W<'_>[src]

Bits 8:13 - Programmable burst length

pub fn pm(&mut self) -> PM_W<'_>[src]

Bits 14:15 - Rx-Tx priority ratio

pub fn fb(&mut self) -> FB_W<'_>[src]

Bit 16 - Fixed burst

pub fn rdp(&mut self) -> RDP_W<'_>[src]

Bits 17:22 - Rx DMA PBL

pub fn usp(&mut self) -> USP_W<'_>[src]

Bit 23 - Use separate PBL

pub fn fpm(&mut self) -> FPM_W<'_>[src]

Bit 24 - 4xPBL mode

pub fn aab(&mut self) -> AAB_W<'_>[src]

Bit 25 - Address-aligned beats

pub fn mb(&mut self) -> MB_W<'_>[src]

Bit 26 - Mixed burst

impl W<u32, Reg<u32, _DMATPDR>>[src]

pub fn tpd(&mut self) -> TPD_W<'_>[src]

Bits 0:31 - Transmit poll demand

impl W<u32, Reg<u32, _DMARPDR>>[src]

pub fn rpd(&mut self) -> RPD_W<'_>[src]

Bits 0:31 - Receive poll demand

impl W<u32, Reg<u32, _DMARDLAR>>[src]

pub fn srl(&mut self) -> SRL_W<'_>[src]

Bits 0:31 - Start of receive list

impl W<u32, Reg<u32, _DMATDLAR>>[src]

pub fn stl(&mut self) -> STL_W<'_>[src]

Bits 0:31 - Start of transmit list

impl W<u32, Reg<u32, _DMASR>>[src]

pub fn ts(&mut self) -> TS_W<'_>[src]

Bit 0 - Transmit status

pub fn tpss(&mut self) -> TPSS_W<'_>[src]

Bit 1 - Transmit process stopped status

pub fn tbus(&mut self) -> TBUS_W<'_>[src]

Bit 2 - Transmit buffer unavailable status

pub fn tjts(&mut self) -> TJTS_W<'_>[src]

Bit 3 - Transmit jabber timeout status

pub fn ros(&mut self) -> ROS_W<'_>[src]

Bit 4 - Receive overflow status

pub fn tus(&mut self) -> TUS_W<'_>[src]

Bit 5 - Transmit underflow status

pub fn rs(&mut self) -> RS_W<'_>[src]

Bit 6 - Receive status

pub fn rbus(&mut self) -> RBUS_W<'_>[src]

Bit 7 - Receive buffer unavailable status

pub fn rpss(&mut self) -> RPSS_W<'_>[src]

Bit 8 - Receive process stopped status

pub fn pwts(&mut self) -> PWTS_W<'_>[src]

Bit 9 - PWTS

pub fn ets(&mut self) -> ETS_W<'_>[src]

Bit 10 - Early transmit status

pub fn fbes(&mut self) -> FBES_W<'_>[src]

Bit 13 - Fatal bus error status

pub fn ers(&mut self) -> ERS_W<'_>[src]

Bit 14 - Early receive status

pub fn ais(&mut self) -> AIS_W<'_>[src]

Bit 15 - Abnormal interrupt summary

pub fn nis(&mut self) -> NIS_W<'_>[src]

Bit 16 - Normal interrupt summary

impl W<u32, Reg<u32, _DMAOMR>>[src]

pub fn sr(&mut self) -> SR_W<'_>[src]

Bit 1 - Start/stop receive

pub fn osf(&mut self) -> OSF_W<'_>[src]

Bit 2 - Operate on second frame

pub fn rtc(&mut self) -> RTC_W<'_>[src]

Bits 3:4 - Receive threshold control

pub fn fugf(&mut self) -> FUGF_W<'_>[src]

Bit 6 - Forward undersized good frames

pub fn fef(&mut self) -> FEF_W<'_>[src]

Bit 7 - Forward error frames

pub fn st(&mut self) -> ST_W<'_>[src]

Bit 13 - Start/stop transmission

pub fn ttc(&mut self) -> TTC_W<'_>[src]

Bits 14:16 - Transmit threshold control

pub fn ftf(&mut self) -> FTF_W<'_>[src]

Bit 20 - Flush transmit FIFO

pub fn tsf(&mut self) -> TSF_W<'_>[src]

Bit 21 - Transmit store and forward

pub fn dfrf(&mut self) -> DFRF_W<'_>[src]

Bit 24 - Disable flushing of received frames

pub fn rsf(&mut self) -> RSF_W<'_>[src]

Bit 25 - Receive store and forward

pub fn dtcefd(&mut self) -> DTCEFD_W<'_>[src]

Bit 26 - Dropping of TCP/IP checksum error frames disable

impl W<u32, Reg<u32, _DMAIER>>[src]

pub fn tie(&mut self) -> TIE_W<'_>[src]

Bit 0 - Transmit interrupt enable

pub fn tpsie(&mut self) -> TPSIE_W<'_>[src]

Bit 1 - Transmit process stopped interrupt enable

pub fn tbuie(&mut self) -> TBUIE_W<'_>[src]

Bit 2 - Transmit buffer unavailable interrupt enable

pub fn tjtie(&mut self) -> TJTIE_W<'_>[src]

Bit 3 - Transmit jabber timeout interrupt enable

pub fn roie(&mut self) -> ROIE_W<'_>[src]

Bit 4 - Receive overflow interrupt enable

pub fn tuie(&mut self) -> TUIE_W<'_>[src]

Bit 5 - Transmit underflow interrupt enable

pub fn rie(&mut self) -> RIE_W<'_>[src]

Bit 6 - Receive interrupt enable

pub fn rbuie(&mut self) -> RBUIE_W<'_>[src]

Bit 7 - Receive buffer unavailable interrupt enable

pub fn rpsie(&mut self) -> RPSIE_W<'_>[src]

Bit 8 - Receive process stopped interrupt enable

pub fn rwtie(&mut self) -> RWTIE_W<'_>[src]

Bit 9 - Receive watchdog timeout interrupt enable

pub fn etie(&mut self) -> ETIE_W<'_>[src]

Bit 10 - Early transmit interrupt enable

pub fn fbeie(&mut self) -> FBEIE_W<'_>[src]

Bit 13 - Fatal bus error interrupt enable

pub fn erie(&mut self) -> ERIE_W<'_>[src]

Bit 14 - Early receive interrupt enable

pub fn aise(&mut self) -> AISE_W<'_>[src]

Bit 15 - Abnormal interrupt summary enable

pub fn nise(&mut self) -> NISE_W<'_>[src]

Bit 16 - Normal interrupt summary enable

impl W<u32, Reg<u32, _DMAMFBOCR>>[src]

pub fn mfc(&mut self) -> MFC_W<'_>[src]

Bits 0:15 - Missed frames by the controller

pub fn omfc(&mut self) -> OMFC_W<'_>[src]

Bit 16 - Overflow bit for missed frame counter

pub fn mfa(&mut self) -> MFA_W<'_>[src]

Bits 17:27 - Missed frames by the application

pub fn ofoc(&mut self) -> OFOC_W<'_>[src]

Bit 28 - Overflow bit for FIFO overflow counter

impl W<u32, Reg<u32, _DMARSWTR>>[src]

pub fn rswtc(&mut self) -> RSWTC_W<'_>[src]

Bits 0:7 - Receive status watchdog timer count

impl W<u32, Reg<u32, _OTG_FS_HCFG>>[src]

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>[src]

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _OTG_FS_HFIR>>[src]

pub fn frivl(&mut self) -> FRIVL_W<'_>[src]

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _OTG_FS_HPTXSTS>>[src]

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>[src]

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _OTG_FS_HAINTMSK>>[src]

pub fn haintm(&mut self) -> HAINTM_W<'_>[src]

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _OTG_FS_HPRT>>[src]

pub fn pcdet(&mut self) -> PCDET_W<'_>[src]

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>[src]

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>[src]

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>[src]

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>[src]

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>[src]

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>[src]

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>[src]

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>[src]

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _OTG_FS_HCCHAR0>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR1>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR2>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR3>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR4>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR5>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR6>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCCHAR7>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT0>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT1>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT2>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT3>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT4>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT5>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT6>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINT7>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK0>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK1>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK2>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK3>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK4>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK5>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK6>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK7>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ0>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ1>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ2>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ3>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ4>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ5>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ6>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ7>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCCHAR8>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT8>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK8>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ8>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCCHAR9>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT9>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK9>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ9>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCCHAR10>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT10>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK10>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ10>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_HCCHAR11>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 20:21 - Multicount

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_FS_HCINT11>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_FS_HCINTMSK11>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_FS_HCTSIZ11>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_FS_DCFG>>[src]

pub fn dspd(&mut self) -> DSPD_W<'_>[src]

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>[src]

Bit 2 - Non-zero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>[src]

Bits 11:12 - Periodic frame interval

impl W<u32, Reg<u32, _OTG_FS_DCTL>>[src]

pub fn rwusig(&mut self) -> RWUSIG_W<'_>[src]

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>[src]

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>[src]

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>[src]

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>[src]

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>[src]

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>[src]

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>[src]

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _OTG_FS_DIEPMSK>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>[src]

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>[src]

Bit 3 - Timeout condition mask (Non-isochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>[src]

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>[src]

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>[src]

Bit 6 - IN endpoint NAK effective mask

impl W<u32, Reg<u32, _OTG_FS_DOEPMSK>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>[src]

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>[src]

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled mask

impl W<u32, Reg<u32, _OTG_FS_DAINTMSK>>[src]

pub fn iepm(&mut self) -> IEPM_W<'_>[src]

Bits 0:15 - IN EP interrupt mask bits

pub fn oepint(&mut self) -> OEPINT_W<'_>[src]

Bits 16:31 - OUT endpoint interrupt bits

impl W<u32, Reg<u32, _OTG_FS_DVBUSDIS>>[src]

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>[src]

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _OTG_FS_DVBUSPULSE>>[src]

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>[src]

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _OTG_FS_DIEPEMPMSK>>[src]

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>[src]

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL0>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:1 - Maximum packet size

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL1>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm_sd1pid(&mut self) -> SODDFRM_SD1PID_W<'_>[src]

Bit 29 - SODDFRM/SD1PID

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL2>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL3>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL0>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL1>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL2>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL3>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPINT0>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPINT1>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPINT2>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPINT3>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPINT0>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPINT1>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPINT2>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPINT3>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ0>>[src]

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:20 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ0>>[src]

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>[src]

Bits 29:30 - SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bit 19 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:6 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ1>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ2>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ3>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ1>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ2>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ3>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL4>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPINT4>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ4>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DTXFSTS4>>[src]

pub fn ineptfsav(&mut self) -> INEPTFSAV_W<'_>[src]

Bits 0:15 - IN endpoint TxFIFO space available

impl W<u32, Reg<u32, _OTG_FS_DIEPCTL5>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TXFNUM

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DIEPINT5>>[src]

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - INEPNE

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - ITTXFE

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - TOC

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DIEPTSIZ55>>[src]

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DTXFSTS55>>[src]

pub fn ineptfsav(&mut self) -> INEPTFSAV_W<'_>[src]

Bits 0:15 - IN endpoint TxFIFO space available

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL4>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPINT4>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ4>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_DOEPCTL5>>[src]

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - EPENA

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - EPDIS

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - SODDFRM

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - SD0PID/SEVNFRM

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - SNAK

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - CNAK

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - Stall

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - SNPM

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - EPTYP

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USBAEP

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - MPSIZ

impl W<u32, Reg<u32, _OTG_FS_DOEPINT5>>[src]

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - B2BSTUP

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OTEPDIS

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - STUP

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - EPDISD

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - XFRC

impl W<u32, Reg<u32, _OTG_FS_DOEPTSIZ5>>[src]

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

impl W<u32, Reg<u32, _OTG_FS_PCGCCTL>>[src]

pub fn stppclk(&mut self) -> STPPCLK_W<'_>[src]

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>[src]

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>[src]

Bit 4 - PHY Suspended

impl W<u32, Reg<u32, _OTG_HS_HCFG>>[src]

pub fn fslspcs(&mut self) -> FSLSPCS_W<'_>[src]

Bits 0:1 - FS/LS PHY clock select

impl W<u32, Reg<u32, _OTG_HS_HFIR>>[src]

pub fn frivl(&mut self) -> FRIVL_W<'_>[src]

Bits 0:15 - Frame interval

impl W<u32, Reg<u32, _OTG_HS_HPTXSTS>>[src]

pub fn ptxfsavl(&mut self) -> PTXFSAVL_W<'_>[src]

Bits 0:15 - Periodic transmit data FIFO space available

impl W<u32, Reg<u32, _OTG_HS_HAINTMSK>>[src]

pub fn haintm(&mut self) -> HAINTM_W<'_>[src]

Bits 0:15 - Channel interrupt mask

impl W<u32, Reg<u32, _OTG_HS_HPRT>>[src]

pub fn pcdet(&mut self) -> PCDET_W<'_>[src]

Bit 1 - Port connect detected

pub fn pena(&mut self) -> PENA_W<'_>[src]

Bit 2 - Port enable

pub fn penchng(&mut self) -> PENCHNG_W<'_>[src]

Bit 3 - Port enable/disable change

pub fn pocchng(&mut self) -> POCCHNG_W<'_>[src]

Bit 5 - Port overcurrent change

pub fn pres(&mut self) -> PRES_W<'_>[src]

Bit 6 - Port resume

pub fn psusp(&mut self) -> PSUSP_W<'_>[src]

Bit 7 - Port suspend

pub fn prst(&mut self) -> PRST_W<'_>[src]

Bit 8 - Port reset

pub fn ppwr(&mut self) -> PPWR_W<'_>[src]

Bit 12 - Port power

pub fn ptctl(&mut self) -> PTCTL_W<'_>[src]

Bits 13:16 - Port test control

impl W<u32, Reg<u32, _OTG_HS_HCCHAR0>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR1>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR2>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR3>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR4>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR5>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR6>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR7>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR8>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR9>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR10>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCCHAR11>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT0>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT1>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT2>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT3>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT4>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT5>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT6>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT7>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT8>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT9>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT10>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT11>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT0>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT1>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT2>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT3>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT4>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT5>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT6>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT7>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT8>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT9>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT10>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINT11>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK0>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK1>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK2>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK3>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK4>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK5>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK6>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK7>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK8>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK9>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK10>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK11>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - response received interrupt mask

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error mask

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error mask

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ0>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ1>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ2>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ3>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ4>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ5>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ6>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ7>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ8>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ9>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ10>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ11>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA0>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA1>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA2>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA3>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA4>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA5>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA6>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA7>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA8>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA9>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA10>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCDMA11>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCCHAR12>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT12>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT12>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK12>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ12>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA12>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCCHAR13>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT13>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT13>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK13>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALLM response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ13>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA13>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCCHAR14>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT14>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT14>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK14>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stallm(&mut self) -> STALLM_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAKM response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACKM response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ14>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA14>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_HCCHAR15>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn epnum(&mut self) -> EPNUM_W<'_>[src]

Bits 11:14 - Endpoint number

pub fn epdir(&mut self) -> EPDIR_W<'_>[src]

Bit 15 - Endpoint direction

pub fn lsdev(&mut self) -> LSDEV_W<'_>[src]

Bit 17 - Low-speed device

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn mc(&mut self) -> MC_W<'_>[src]

Bits 20:21 - Multi Count (MC) / Error Count (EC)

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 22:28 - Device address

pub fn oddfrm(&mut self) -> ODDFRM_W<'_>[src]

Bit 29 - Odd frame

pub fn chdis(&mut self) -> CHDIS_W<'_>[src]

Bit 30 - Channel disable

pub fn chena(&mut self) -> CHENA_W<'_>[src]

Bit 31 - Channel enable

impl W<u32, Reg<u32, _OTG_HS_HCSPLT15>>[src]

pub fn prtaddr(&mut self) -> PRTADDR_W<'_>[src]

Bits 0:6 - Port address

pub fn hubaddr(&mut self) -> HUBADDR_W<'_>[src]

Bits 7:13 - Hub address

pub fn xactpos(&mut self) -> XACTPOS_W<'_>[src]

Bits 14:15 - XACTPOS

pub fn complsplt(&mut self) -> COMPLSPLT_W<'_>[src]

Bit 16 - Do complete split

pub fn spliten(&mut self) -> SPLITEN_W<'_>[src]

Bit 31 - Split enable

impl W<u32, Reg<u32, _OTG_HS_HCINT15>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed

pub fn chh(&mut self) -> CHH_W<'_>[src]

Bit 1 - Channel halted

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 4 - NAK response received interrupt

pub fn ack(&mut self) -> ACK_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerr(&mut self) -> TXERR_W<'_>[src]

Bit 7 - Transaction error

pub fn bberr(&mut self) -> BBERR_W<'_>[src]

Bit 8 - Babble error

pub fn frmor(&mut self) -> FRMOR_W<'_>[src]

Bit 9 - Frame overrun

pub fn dterr(&mut self) -> DTERR_W<'_>[src]

Bit 10 - Data toggle error

impl W<u32, Reg<u32, _OTG_HS_HCINTMSK15>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed mask

pub fn chhm(&mut self) -> CHHM_W<'_>[src]

Bit 1 - Channel halted mask

pub fn ahberr(&mut self) -> AHBERR_W<'_>[src]

Bit 2 - AHB error

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 3 - STALL response received interrupt mask

pub fn nakm(&mut self) -> NAKM_W<'_>[src]

Bit 4 - NAK response received interrupt mask

pub fn ackm(&mut self) -> ACKM_W<'_>[src]

Bit 5 - ACK response received/transmitted interrupt mask

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 6 - Response received interrupt

pub fn txerrm(&mut self) -> TXERRM_W<'_>[src]

Bit 7 - Transaction error

pub fn bberrm(&mut self) -> BBERRM_W<'_>[src]

Bit 8 - Babble error

pub fn frmorm(&mut self) -> FRMORM_W<'_>[src]

Bit 9 - Frame overrun mask

pub fn dterrm(&mut self) -> DTERRM_W<'_>[src]

Bit 10 - Data toggle error mask

impl W<u32, Reg<u32, _OTG_HS_HCTSIZ15>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn dpid(&mut self) -> DPID_W<'_>[src]

Bits 29:30 - Data PID

impl W<u32, Reg<u32, _OTG_HS_HCDMA15>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DCFG>>[src]

pub fn dspd(&mut self) -> DSPD_W<'_>[src]

Bits 0:1 - Device speed

pub fn nzlsohsk(&mut self) -> NZLSOHSK_W<'_>[src]

Bit 2 - Nonzero-length status OUT handshake

pub fn dad(&mut self) -> DAD_W<'_>[src]

Bits 4:10 - Device address

pub fn pfivl(&mut self) -> PFIVL_W<'_>[src]

Bits 11:12 - Periodic (micro)frame interval

pub fn perschivl(&mut self) -> PERSCHIVL_W<'_>[src]

Bits 24:25 - Periodic scheduling interval

impl W<u32, Reg<u32, _OTG_HS_DCTL>>[src]

pub fn rwusig(&mut self) -> RWUSIG_W<'_>[src]

Bit 0 - Remote wakeup signaling

pub fn sdis(&mut self) -> SDIS_W<'_>[src]

Bit 1 - Soft disconnect

pub fn tctl(&mut self) -> TCTL_W<'_>[src]

Bits 4:6 - Test control

pub fn sginak(&mut self) -> SGINAK_W<'_>[src]

Bit 7 - Set global IN NAK

pub fn cginak(&mut self) -> CGINAK_W<'_>[src]

Bit 8 - Clear global IN NAK

pub fn sgonak(&mut self) -> SGONAK_W<'_>[src]

Bit 9 - Set global OUT NAK

pub fn cgonak(&mut self) -> CGONAK_W<'_>[src]

Bit 10 - Clear global OUT NAK

pub fn poprgdne(&mut self) -> POPRGDNE_W<'_>[src]

Bit 11 - Power-on programming done

impl W<u32, Reg<u32, _OTG_HS_DIEPMSK>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>[src]

Bit 1 - Endpoint disabled interrupt mask

pub fn tom(&mut self) -> TOM_W<'_>[src]

Bit 3 - Timeout condition mask (nonisochronous endpoints)

pub fn ittxfemsk(&mut self) -> ITTXFEMSK_W<'_>[src]

Bit 4 - IN token received when TxFIFO empty mask

pub fn inepnmm(&mut self) -> INEPNMM_W<'_>[src]

Bit 5 - IN token received with EP mismatch mask

pub fn inepnem(&mut self) -> INEPNEM_W<'_>[src]

Bit 6 - IN endpoint NAK effective mask

pub fn txfurm(&mut self) -> TXFURM_W<'_>[src]

Bit 8 - FIFO underrun mask

pub fn bim(&mut self) -> BIM_W<'_>[src]

Bit 9 - BNA interrupt mask

impl W<u32, Reg<u32, _OTG_HS_DOEPMSK>>[src]

pub fn xfrcm(&mut self) -> XFRCM_W<'_>[src]

Bit 0 - Transfer completed interrupt mask

pub fn epdm(&mut self) -> EPDM_W<'_>[src]

Bit 1 - Endpoint disabled interrupt mask

pub fn stupm(&mut self) -> STUPM_W<'_>[src]

Bit 3 - SETUP phase done mask

pub fn otepdm(&mut self) -> OTEPDM_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled mask

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received mask

pub fn opem(&mut self) -> OPEM_W<'_>[src]

Bit 8 - OUT packet error mask

pub fn boim(&mut self) -> BOIM_W<'_>[src]

Bit 9 - BNA interrupt mask

impl W<u32, Reg<u32, _OTG_HS_DAINTMSK>>[src]

pub fn iepm(&mut self) -> IEPM_W<'_>[src]

Bits 0:15 - IN EP interrupt mask bits

pub fn oepm(&mut self) -> OEPM_W<'_>[src]

Bits 16:31 - OUT EP interrupt mask bits

impl W<u32, Reg<u32, _OTG_HS_DVBUSDIS>>[src]

pub fn vbusdt(&mut self) -> VBUSDT_W<'_>[src]

Bits 0:15 - Device VBUS discharge time

impl W<u32, Reg<u32, _OTG_HS_DVBUSPULSE>>[src]

pub fn dvbusp(&mut self) -> DVBUSP_W<'_>[src]

Bits 0:11 - Device VBUS pulsing time

impl W<u32, Reg<u32, _OTG_HS_DTHRCTL>>[src]

pub fn nonisothren(&mut self) -> NONISOTHREN_W<'_>[src]

Bit 0 - Nonisochronous IN endpoints threshold enable

pub fn isothren(&mut self) -> ISOTHREN_W<'_>[src]

Bit 1 - ISO IN endpoint threshold enable

pub fn txthrlen(&mut self) -> TXTHRLEN_W<'_>[src]

Bits 2:10 - Transmit threshold length

pub fn rxthren(&mut self) -> RXTHREN_W<'_>[src]

Bit 16 - Receive threshold enable

pub fn rxthrlen(&mut self) -> RXTHRLEN_W<'_>[src]

Bits 17:25 - Receive threshold length

pub fn arpen(&mut self) -> ARPEN_W<'_>[src]

Bit 27 - Arbiter parking enable

impl W<u32, Reg<u32, _OTG_HS_DIEPEMPMSK>>[src]

pub fn ineptxfem(&mut self) -> INEPTXFEM_W<'_>[src]

Bits 0:15 - IN EP Tx FIFO empty interrupt mask bits

impl W<u32, Reg<u32, _OTG_HS_DEACHINT>>[src]

pub fn iep1int(&mut self) -> IEP1INT_W<'_>[src]

Bit 1 - IN endpoint 1interrupt bit

pub fn oep1int(&mut self) -> OEP1INT_W<'_>[src]

Bit 17 - OUT endpoint 1 interrupt bit

impl W<u32, Reg<u32, _OTG_HS_DEACHINTMSK>>[src]

pub fn iep1intm(&mut self) -> IEP1INTM_W<'_>[src]

Bit 1 - IN Endpoint 1 interrupt mask bit

pub fn oep1intm(&mut self) -> OEP1INTM_W<'_>[src]

Bit 17 - OUT Endpoint 1 interrupt mask bit

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL0>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL1>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL2>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL3>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL4>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL5>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL6>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPCTL7>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn txfnum(&mut self) -> TXFNUM_W<'_>[src]

Bits 22:25 - TxFIFO number

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DIEPINT0>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT1>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT2>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT3>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT4>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT5>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT6>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPINT7>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn toc(&mut self) -> TOC_W<'_>[src]

Bit 3 - Timeout condition

pub fn ittxfe(&mut self) -> ITTXFE_W<'_>[src]

Bit 4 - IN token received when TxFIFO is empty

pub fn inepne(&mut self) -> INEPNE_W<'_>[src]

Bit 6 - IN endpoint NAK effective

pub fn txfifoudrn(&mut self) -> TXFIFOUDRN_W<'_>[src]

Bit 8 - Transmit Fifo Underrun

pub fn bna(&mut self) -> BNA_W<'_>[src]

Bit 9 - Buffer not available interrupt

pub fn pktdrpsts(&mut self) -> PKTDRPSTS_W<'_>[src]

Bit 11 - Packet dropped status

pub fn berr(&mut self) -> BERR_W<'_>[src]

Bit 12 - Babble error interrupt

pub fn nak(&mut self) -> NAK_W<'_>[src]

Bit 13 - NAK interrupt

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ0>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:6 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:20 - Packet count

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA1>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA2>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA3>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA4>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPDMA5>>[src]

pub fn dmaaddr(&mut self) -> DMAADDR_W<'_>[src]

Bits 0:31 - DMA address

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ1>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ2>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ3>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ4>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ5>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL0>>[src]

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL1>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL2>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL3>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPINT0>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT1>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT2>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT3>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT4>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT5>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT6>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPINT7>>[src]

pub fn xfrc(&mut self) -> XFRC_W<'_>[src]

Bit 0 - Transfer completed interrupt

pub fn epdisd(&mut self) -> EPDISD_W<'_>[src]

Bit 1 - Endpoint disabled interrupt

pub fn stup(&mut self) -> STUP_W<'_>[src]

Bit 3 - SETUP phase done

pub fn otepdis(&mut self) -> OTEPDIS_W<'_>[src]

Bit 4 - OUT token received when endpoint disabled

pub fn b2bstup(&mut self) -> B2BSTUP_W<'_>[src]

Bit 6 - Back-to-back SETUP packets received

pub fn nyet(&mut self) -> NYET_W<'_>[src]

Bit 14 - NYET interrupt

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ0>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:6 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bit 19 - Packet count

pub fn stupcnt(&mut self) -> STUPCNT_W<'_>[src]

Bits 29:30 - SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ1>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ2>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ3>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ4>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ6>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DTXFSTS6>>[src]

pub fn ineptfsav(&mut self) -> INEPTFSAV_W<'_>[src]

Bits 0:15 - IN endpoint TxFIFO space avail

impl W<u32, Reg<u32, _OTG_HS_DIEPTSIZ7>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn mcnt(&mut self) -> MCNT_W<'_>[src]

Bits 29:30 - Multi count

impl W<u32, Reg<u32, _OTG_HS_DTXFSTS7>>[src]

pub fn ineptfsav(&mut self) -> INEPTFSAV_W<'_>[src]

Bits 0:15 - IN endpoint TxFIFO space avail

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL4>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL5>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL6>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPCTL7>>[src]

pub fn mpsiz(&mut self) -> MPSIZ_W<'_>[src]

Bits 0:10 - Maximum packet size

pub fn usbaep(&mut self) -> USBAEP_W<'_>[src]

Bit 15 - USB active endpoint

pub fn eptyp(&mut self) -> EPTYP_W<'_>[src]

Bits 18:19 - Endpoint type

pub fn snpm(&mut self) -> SNPM_W<'_>[src]

Bit 20 - Snoop mode

pub fn stall(&mut self) -> STALL_W<'_>[src]

Bit 21 - STALL handshake

pub fn cnak(&mut self) -> CNAK_W<'_>[src]

Bit 26 - Clear NAK

pub fn snak(&mut self) -> SNAK_W<'_>[src]

Bit 27 - Set NAK

pub fn sd0pid_sevnfrm(&mut self) -> SD0PID_SEVNFRM_W<'_>[src]

Bit 28 - Set DATA0 PID/Set even frame

pub fn soddfrm(&mut self) -> SODDFRM_W<'_>[src]

Bit 29 - Set odd frame

pub fn epdis(&mut self) -> EPDIS_W<'_>[src]

Bit 30 - Endpoint disable

pub fn epena(&mut self) -> EPENA_W<'_>[src]

Bit 31 - Endpoint enable

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ5>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ6>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_DOEPTSIZ7>>[src]

pub fn xfrsiz(&mut self) -> XFRSIZ_W<'_>[src]

Bits 0:18 - Transfer size

pub fn pktcnt(&mut self) -> PKTCNT_W<'_>[src]

Bits 19:28 - Packet count

pub fn rxdpid_stupcnt(&mut self) -> RXDPID_STUPCNT_W<'_>[src]

Bits 29:30 - Received data PID/SETUP packet count

impl W<u32, Reg<u32, _OTG_HS_PCGCR>>[src]

pub fn stppclk(&mut self) -> STPPCLK_W<'_>[src]

Bit 0 - Stop PHY clock

pub fn gatehclk(&mut self) -> GATEHCLK_W<'_>[src]

Bit 1 - Gate HCLK

pub fn physusp(&mut self) -> PHYSUSP_W<'_>[src]

Bit 4 - PHY suspended

impl W<u32, Reg<u32, _DSI_CR>>[src]

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - Enable

impl W<u32, Reg<u32, _DSI_CCR>>[src]

pub fn txeckdiv(&mut self) -> TXECKDIV_W<'_>[src]

Bits 0:7 - TX Escape Clock Division

pub fn tockdiv(&mut self) -> TOCKDIV_W<'_>[src]

Bits 8:15 - Timeout Clock Division

impl W<u32, Reg<u32, _DSI_LVCIDR>>[src]

pub fn vcid(&mut self) -> VCID_W<'_>[src]

Bits 0:1 - Virtual Channel ID

impl W<u32, Reg<u32, _DSI_LCOLCR>>[src]

pub fn colc(&mut self) -> COLC_W<'_>[src]

Bits 0:3 - Color Coding

pub fn lpe(&mut self) -> LPE_W<'_>[src]

Bit 8 - Loosely Packet Enable

impl W<u32, Reg<u32, _DSI_LPCR>>[src]

pub fn dep(&mut self) -> DEP_W<'_>[src]

Bit 0 - Data Enable Polarity

pub fn vsp(&mut self) -> VSP_W<'_>[src]

Bit 1 - VSYNC Polarity

pub fn hsp(&mut self) -> HSP_W<'_>[src]

Bit 2 - HSYNC Polarity

impl W<u32, Reg<u32, _DSI_LPMCR>>[src]

pub fn vlpsize(&mut self) -> VLPSIZE_W<'_>[src]

Bits 0:7 - VACT Largest Packet Size

pub fn lpsize(&mut self) -> LPSIZE_W<'_>[src]

Bits 16:23 - Largest Packet Size

impl W<u32, Reg<u32, _DSI_PCR>>[src]

pub fn ettxe(&mut self) -> ETTXE_W<'_>[src]

Bit 0 - EoTp Transmission Enable

pub fn etrxe(&mut self) -> ETRXE_W<'_>[src]

Bit 1 - EoTp Reception Enable

pub fn btae(&mut self) -> BTAE_W<'_>[src]

Bit 2 - Bus Turn Around Enable

pub fn eccrxe(&mut self) -> ECCRXE_W<'_>[src]

Bit 3 - ECC Reception Enable

pub fn crcrxe(&mut self) -> CRCRXE_W<'_>[src]

Bit 4 - CRC Reception Enable

impl W<u32, Reg<u32, _DSI_GVCIDR>>[src]

pub fn vcid(&mut self) -> VCID_W<'_>[src]

Bits 0:1 - Virtual Channel ID

impl W<u32, Reg<u32, _DSI_MCR>>[src]

pub fn cmdm(&mut self) -> CMDM_W<'_>[src]

Bit 0 - Command mode

impl W<u32, Reg<u32, _DSI_VMCR>>[src]

pub fn vmt(&mut self) -> VMT_W<'_>[src]

Bits 0:1 - Video mode Type

pub fn lpvsae(&mut self) -> LPVSAE_W<'_>[src]

Bit 8 - Low-Power Vertical Sync Active Enable

pub fn lpvbpe(&mut self) -> LPVBPE_W<'_>[src]

Bit 9 - Low-power Vertical Back-Porch Enable

pub fn lpvfpe(&mut self) -> LPVFPE_W<'_>[src]

Bit 10 - Low-power Vertical Front-porch Enable

pub fn lpvae(&mut self) -> LPVAE_W<'_>[src]

Bit 11 - Low-Power Vertical Active Enable

pub fn lphbpe(&mut self) -> LPHBPE_W<'_>[src]

Bit 12 - Low-Power Horizontal Back-Porch Enable

pub fn lphfpe(&mut self) -> LPHFPE_W<'_>[src]

Bit 13 - Low-Power Horizontal Front-Porch Enable

pub fn fbtaae(&mut self) -> FBTAAE_W<'_>[src]

Bit 14 - Frame Bus-Turn-Around Acknowledge Enable

pub fn lpce(&mut self) -> LPCE_W<'_>[src]

Bit 15 - Low-Power Command Enable

pub fn pge(&mut self) -> PGE_W<'_>[src]

Bit 16 - Pattern Generator Enable

pub fn pgm(&mut self) -> PGM_W<'_>[src]

Bit 20 - Pattern Generator mode

pub fn pgo(&mut self) -> PGO_W<'_>[src]

Bit 24 - Pattern Generator Orientation

impl W<u32, Reg<u32, _DSI_VPCR>>[src]

pub fn vpsize(&mut self) -> VPSIZE_W<'_>[src]

Bits 0:13 - Video Packet Size

impl W<u32, Reg<u32, _DSI_VCCR>>[src]

pub fn numc(&mut self) -> NUMC_W<'_>[src]

Bits 0:12 - Number of Chunks

impl W<u32, Reg<u32, _DSI_VNPCR>>[src]

pub fn npsize(&mut self) -> NPSIZE_W<'_>[src]

Bits 0:12 - Null Packet Size

impl W<u32, Reg<u32, _DSI_VHSACR>>[src]

pub fn hsa(&mut self) -> HSA_W<'_>[src]

Bits 0:11 - Horizontal Synchronism Active duration

impl W<u32, Reg<u32, _DSI_VHBPCR>>[src]

pub fn hbp(&mut self) -> HBP_W<'_>[src]

Bits 0:11 - Horizontal Back-Porch duration

impl W<u32, Reg<u32, _DSI_VLCR>>[src]

pub fn hline(&mut self) -> HLINE_W<'_>[src]

Bits 0:14 - Horizontal Line duration

impl W<u32, Reg<u32, _DSI_VVSACR>>[src]

pub fn vsa(&mut self) -> VSA_W<'_>[src]

Bits 0:9 - Vertical Synchronism Active duration

impl W<u32, Reg<u32, _DSI_VVBPCR>>[src]

pub fn vbp(&mut self) -> VBP_W<'_>[src]

Bits 0:9 - Vertical Back-Porch duration

impl W<u32, Reg<u32, _DSI_VVFPCR>>[src]

pub fn vfp(&mut self) -> VFP_W<'_>[src]

Bits 0:9 - Vertical Front-Porch duration

impl W<u32, Reg<u32, _DSI_VVACR>>[src]

pub fn va(&mut self) -> VA_W<'_>[src]

Bits 0:13 - Vertical Active duration

impl W<u32, Reg<u32, _DSI_LCCR>>[src]

pub fn cmdsize(&mut self) -> CMDSIZE_W<'_>[src]

Bits 0:15 - Command Size

impl W<u32, Reg<u32, _DSI_CMCR>>[src]

pub fn teare(&mut self) -> TEARE_W<'_>[src]

Bit 0 - Tearing Effect Acknowledge Request Enable

pub fn are(&mut self) -> ARE_W<'_>[src]

Bit 1 - Acknowledge Request Enable

pub fn gsw0tx(&mut self) -> GSW0TX_W<'_>[src]

Bit 8 - Generic Short Write Zero parameters Transmission

pub fn gsw1tx(&mut self) -> GSW1TX_W<'_>[src]

Bit 9 - Generic Short Write One parameters Transmission

pub fn gsw2tx(&mut self) -> GSW2TX_W<'_>[src]

Bit 10 - Generic Short Write Two parameters Transmission

pub fn gsr0tx(&mut self) -> GSR0TX_W<'_>[src]

Bit 11 - Generic Short Read Zero parameters Transmission

pub fn gsr1tx(&mut self) -> GSR1TX_W<'_>[src]

Bit 12 - Generic Short Read One parameters Transmission

pub fn gsr2tx(&mut self) -> GSR2TX_W<'_>[src]

Bit 13 - Generic Short Read Two parameters Transmission

pub fn glwtx(&mut self) -> GLWTX_W<'_>[src]

Bit 14 - Generic Long Write Transmission

pub fn dsw0tx(&mut self) -> DSW0TX_W<'_>[src]

Bit 16 - DCS Short Write Zero parameter Transmission

pub fn dsw1tx(&mut self) -> DSW1TX_W<'_>[src]

Bit 17 - DCS Short Read One parameter Transmission

pub fn dsr0tx(&mut self) -> DSR0TX_W<'_>[src]

Bit 18 - DCS Short Read Zero parameter Transmission

pub fn dlwtx(&mut self) -> DLWTX_W<'_>[src]

Bit 19 - DCS Long Write Transmission

pub fn mrdps(&mut self) -> MRDPS_W<'_>[src]

Bit 24 - Maximum Read Packet Size

impl W<u32, Reg<u32, _DSI_GHCR>>[src]

pub fn dt(&mut self) -> DT_W<'_>[src]

Bits 0:5 - Type

pub fn vcid(&mut self) -> VCID_W<'_>[src]

Bits 6:7 - Channel

pub fn wclsb(&mut self) -> WCLSB_W<'_>[src]

Bits 8:15 - WordCount LSB

pub fn wcmsb(&mut self) -> WCMSB_W<'_>[src]

Bits 16:23 - WordCount MSB

impl W<u32, Reg<u32, _DSI_GPDR>>[src]

pub fn data1(&mut self) -> DATA1_W<'_>[src]

Bits 0:7 - Payload Byte 1

pub fn data2(&mut self) -> DATA2_W<'_>[src]

Bits 8:15 - Payload Byte 2

pub fn data3(&mut self) -> DATA3_W<'_>[src]

Bits 16:23 - Payload Byte 3

pub fn data4(&mut self) -> DATA4_W<'_>[src]

Bits 24:31 - Payload Byte 4

impl W<u32, Reg<u32, _DSI_TCCR0>>[src]

pub fn lprx_tocnt(&mut self) -> LPRX_TOCNT_W<'_>[src]

Bits 0:15 - Low-power Reception Timeout Counter

pub fn hstx_tocnt(&mut self) -> HSTX_TOCNT_W<'_>[src]

Bits 16:31 - High-Speed Transmission Timeout Counter

impl W<u32, Reg<u32, _DSI_TCCR1>>[src]

pub fn hsrd_tocnt(&mut self) -> HSRD_TOCNT_W<'_>[src]

Bits 0:15 - High-Speed Read Timeout Counter

impl W<u32, Reg<u32, _DSI_TCCR2>>[src]

pub fn lprd_tocnt(&mut self) -> LPRD_TOCNT_W<'_>[src]

Bits 0:15 - Low-Power Read Timeout Counter

impl W<u32, Reg<u32, _DSI_TCCR3>>[src]

pub fn hswr_tocnt(&mut self) -> HSWR_TOCNT_W<'_>[src]

Bits 0:15 - High-Speed Write Timeout Counter

pub fn pm(&mut self) -> PM_W<'_>[src]

Bit 24 - Presp mode

impl W<u32, Reg<u32, _DSI_TCCR4>>[src]

pub fn lswr_tocnt(&mut self) -> LSWR_TOCNT_W<'_>[src]

Bits 0:15 - Low-Power Write Timeout Counter

impl W<u32, Reg<u32, _DSI_TCCR5>>[src]

pub fn bta_tocnt(&mut self) -> BTA_TOCNT_W<'_>[src]

Bits 0:15 - Bus-Turn-Around Timeout Counter

impl W<u32, Reg<u32, _DSI_CLCR>>[src]

pub fn dpcc(&mut self) -> DPCC_W<'_>[src]

Bit 0 - D-PHY Clock Control

pub fn acr(&mut self) -> ACR_W<'_>[src]

Bit 1 - Automatic Clock lane Control

impl W<u32, Reg<u32, _DSI_CLTCR>>[src]

pub fn lp2hs_time(&mut self) -> LP2HS_TIME_W<'_>[src]

Bits 0:9 - Low-Power to High-Speed Time

pub fn hs2lp_time(&mut self) -> HS2LP_TIME_W<'_>[src]

Bits 16:25 - High-Speed to Low-Power Time

impl W<u32, Reg<u32, _DSI_DLTCR>>[src]

pub fn mrd_time(&mut self) -> MRD_TIME_W<'_>[src]

Bits 0:14 - Maximum Read Time

pub fn lp2hs_time(&mut self) -> LP2HS_TIME_W<'_>[src]

Bits 16:23 - Low-Power To High-Speed Time

pub fn hs2lp_time(&mut self) -> HS2LP_TIME_W<'_>[src]

Bits 24:31 - High-Speed To Low-Power Time

impl W<u32, Reg<u32, _DSI_PCTLR>>[src]

pub fn den(&mut self) -> DEN_W<'_>[src]

Bit 1 - Digital Enable

pub fn cke(&mut self) -> CKE_W<'_>[src]

Bit 2 - Clock Enable

impl W<u32, Reg<u32, _DSI_PCONFR>>[src]

pub fn nl(&mut self) -> NL_W<'_>[src]

Bits 0:1 - Number of Lanes

pub fn sw_time(&mut self) -> SW_TIME_W<'_>[src]

Bits 8:15 - Stop Wait Time

impl W<u32, Reg<u32, _DSI_PUCR>>[src]

pub fn urcl(&mut self) -> URCL_W<'_>[src]

Bit 0 - ULPS Request on Clock Lane

pub fn uecl(&mut self) -> UECL_W<'_>[src]

Bit 1 - ULPS Exit on Clock Lane

pub fn urdl(&mut self) -> URDL_W<'_>[src]

Bit 2 - ULPS Request on Data Lane

pub fn uedl(&mut self) -> UEDL_W<'_>[src]

Bit 3 - ULPS Exit on Data Lane

impl W<u32, Reg<u32, _DSI_PTTCR>>[src]

pub fn tx_trig(&mut self) -> TX_TRIG_W<'_>[src]

Bits 0:3 - Transmission Trigger

impl W<u32, Reg<u32, _DSI_IER0>>[src]

pub fn ae0ie(&mut self) -> AE0IE_W<'_>[src]

Bit 0 - Acknowledge Error 0 Interrupt Enable

pub fn ae1ie(&mut self) -> AE1IE_W<'_>[src]

Bit 1 - Acknowledge Error 1 Interrupt Enable

pub fn ae2ie(&mut self) -> AE2IE_W<'_>[src]

Bit 2 - Acknowledge Error 2 Interrupt Enable

pub fn ae3ie(&mut self) -> AE3IE_W<'_>[src]

Bit 3 - Acknowledge Error 3 Interrupt Enable

pub fn ae4ie(&mut self) -> AE4IE_W<'_>[src]

Bit 4 - Acknowledge Error 4 Interrupt Enable

pub fn ae5ie(&mut self) -> AE5IE_W<'_>[src]

Bit 5 - Acknowledge Error 5 Interrupt Enable

pub fn ae6ie(&mut self) -> AE6IE_W<'_>[src]

Bit 6 - Acknowledge Error 6 Interrupt Enable

pub fn ae7ie(&mut self) -> AE7IE_W<'_>[src]

Bit 7 - Acknowledge Error 7 Interrupt Enable

pub fn ae8ie(&mut self) -> AE8IE_W<'_>[src]

Bit 8 - Acknowledge Error 8 Interrupt Enable

pub fn ae9ie(&mut self) -> AE9IE_W<'_>[src]

Bit 9 - Acknowledge Error 9 Interrupt Enable

pub fn ae10ie(&mut self) -> AE10IE_W<'_>[src]

Bit 10 - Acknowledge Error 10 Interrupt Enable

pub fn ae11ie(&mut self) -> AE11IE_W<'_>[src]

Bit 11 - Acknowledge Error 11 Interrupt Enable

pub fn ae12ie(&mut self) -> AE12IE_W<'_>[src]

Bit 12 - Acknowledge Error 12 Interrupt Enable

pub fn ae13ie(&mut self) -> AE13IE_W<'_>[src]

Bit 13 - Acknowledge Error 13 Interrupt Enable

pub fn ae14ie(&mut self) -> AE14IE_W<'_>[src]

Bit 14 - Acknowledge Error 14 Interrupt Enable

pub fn ae15ie(&mut self) -> AE15IE_W<'_>[src]

Bit 15 - Acknowledge Error 15 Interrupt Enable

pub fn pe0ie(&mut self) -> PE0IE_W<'_>[src]

Bit 16 - PHY Error 0 Interrupt Enable

pub fn pe1ie(&mut self) -> PE1IE_W<'_>[src]

Bit 17 - PHY Error 1 Interrupt Enable

pub fn pe2ie(&mut self) -> PE2IE_W<'_>[src]

Bit 18 - PHY Error 2 Interrupt Enable

pub fn pe3ie(&mut self) -> PE3IE_W<'_>[src]

Bit 19 - PHY Error 3 Interrupt Enable

pub fn pe4ie(&mut self) -> PE4IE_W<'_>[src]

Bit 20 - PHY Error 4 Interrupt Enable

impl W<u32, Reg<u32, _DSI_IER1>>[src]

pub fn tohstxie(&mut self) -> TOHSTXIE_W<'_>[src]

Bit 0 - Timeout High-Speed Transmission Interrupt Enable

pub fn tolprxie(&mut self) -> TOLPRXIE_W<'_>[src]

Bit 1 - Timeout Low-Power Reception Interrupt Enable

pub fn eccseie(&mut self) -> ECCSEIE_W<'_>[src]

Bit 2 - ECC Single-bit Error Interrupt Enable

pub fn eccmeie(&mut self) -> ECCMEIE_W<'_>[src]

Bit 3 - ECC Multi-bit Error Interrupt Enable

pub fn crceie(&mut self) -> CRCEIE_W<'_>[src]

Bit 4 - CRC Error Interrupt Enable

pub fn pseie(&mut self) -> PSEIE_W<'_>[src]

Bit 5 - Packet Size Error Interrupt Enable

pub fn eotpeie(&mut self) -> EOTPEIE_W<'_>[src]

Bit 6 - EoTp Error Interrupt Enable

pub fn lpwreie(&mut self) -> LPWREIE_W<'_>[src]

Bit 7 - LTDC Payload Write Error Interrupt Enable

pub fn gcwreie(&mut self) -> GCWREIE_W<'_>[src]

Bit 8 - Generic Command Write Error Interrupt Enable

pub fn gpwreie(&mut self) -> GPWREIE_W<'_>[src]

Bit 9 - Generic Payload Write Error Interrupt Enable

pub fn gptxeie(&mut self) -> GPTXEIE_W<'_>[src]

Bit 10 - Generic Payload Transmit Error Interrupt Enable

pub fn gprdeie(&mut self) -> GPRDEIE_W<'_>[src]

Bit 11 - Generic Payload Read Error Interrupt Enable

pub fn gprxeie(&mut self) -> GPRXEIE_W<'_>[src]

Bit 12 - Generic Payload Receive Error Interrupt Enable

impl W<u32, Reg<u32, _DSI_FIR0>>[src]

pub fn fae0(&mut self) -> FAE0_W<'_>[src]

Bit 0 - Force Acknowledge Error 0

pub fn fae1(&mut self) -> FAE1_W<'_>[src]

Bit 1 - Force Acknowledge Error 1

pub fn fae2(&mut self) -> FAE2_W<'_>[src]

Bit 2 - Force Acknowledge Error 2

pub fn fae3(&mut self) -> FAE3_W<'_>[src]

Bit 3 - Force Acknowledge Error 3

pub fn fae4(&mut self) -> FAE4_W<'_>[src]

Bit 4 - Force Acknowledge Error 4

pub fn fae5(&mut self) -> FAE5_W<'_>[src]

Bit 5 - Force Acknowledge Error 5

pub fn fae6(&mut self) -> FAE6_W<'_>[src]

Bit 6 - Force Acknowledge Error 6

pub fn fae7(&mut self) -> FAE7_W<'_>[src]

Bit 7 - Force Acknowledge Error 7

pub fn fae8(&mut self) -> FAE8_W<'_>[src]

Bit 8 - Force Acknowledge Error 8

pub fn fae9(&mut self) -> FAE9_W<'_>[src]

Bit 9 - Force Acknowledge Error 9

pub fn fae10(&mut self) -> FAE10_W<'_>[src]

Bit 10 - Force Acknowledge Error 10

pub fn fae11(&mut self) -> FAE11_W<'_>[src]

Bit 11 - Force Acknowledge Error 11

pub fn fae12(&mut self) -> FAE12_W<'_>[src]

Bit 12 - Force Acknowledge Error 12

pub fn fae13(&mut self) -> FAE13_W<'_>[src]

Bit 13 - Force Acknowledge Error 13

pub fn fae14(&mut self) -> FAE14_W<'_>[src]

Bit 14 - Force Acknowledge Error 14

pub fn fae15(&mut self) -> FAE15_W<'_>[src]

Bit 15 - Force Acknowledge Error 15

pub fn fpe0(&mut self) -> FPE0_W<'_>[src]

Bit 16 - Force PHY Error 0

pub fn fpe1(&mut self) -> FPE1_W<'_>[src]

Bit 17 - Force PHY Error 1

pub fn fpe2(&mut self) -> FPE2_W<'_>[src]

Bit 18 - Force PHY Error 2

pub fn fpe3(&mut self) -> FPE3_W<'_>[src]

Bit 19 - Force PHY Error 3

pub fn fpe4(&mut self) -> FPE4_W<'_>[src]

Bit 20 - Force PHY Error 4

impl W<u32, Reg<u32, _DSI_FIR1>>[src]

pub fn ftohstx(&mut self) -> FTOHSTX_W<'_>[src]

Bit 0 - Force Timeout High-Speed Transmission

pub fn ftolprx(&mut self) -> FTOLPRX_W<'_>[src]

Bit 1 - Force Timeout Low-Power Reception

pub fn feccse(&mut self) -> FECCSE_W<'_>[src]

Bit 2 - Force ECC Single-bit Error

pub fn feccme(&mut self) -> FECCME_W<'_>[src]

Bit 3 - Force ECC Multi-bit Error

pub fn fcrce(&mut self) -> FCRCE_W<'_>[src]

Bit 4 - Force CRC Error

pub fn fpse(&mut self) -> FPSE_W<'_>[src]

Bit 5 - Force Packet Size Error

pub fn feotpe(&mut self) -> FEOTPE_W<'_>[src]

Bit 6 - Force EoTp Error

pub fn flpwre(&mut self) -> FLPWRE_W<'_>[src]

Bit 7 - Force LTDC Payload Write Error

pub fn fgcwre(&mut self) -> FGCWRE_W<'_>[src]

Bit 8 - Force Generic Command Write Error

pub fn fgpwre(&mut self) -> FGPWRE_W<'_>[src]

Bit 9 - Force Generic Payload Write Error

pub fn fgptxe(&mut self) -> FGPTXE_W<'_>[src]

Bit 10 - Force Generic Payload Transmit Error

pub fn fgprde(&mut self) -> FGPRDE_W<'_>[src]

Bit 11 - Force Generic Payload Read Error

pub fn fgprxe(&mut self) -> FGPRXE_W<'_>[src]

Bit 12 - Force Generic Payload Receive Error

impl W<u32, Reg<u32, _DSI_VSCR>>[src]

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - Enable

pub fn ur(&mut self) -> UR_W<'_>[src]

Bit 8 - Update Register

impl W<u32, Reg<u32, _DSI_WCFGR>>[src]

pub fn vspol(&mut self) -> VSPOL_W<'_>[src]

Bit 7 - VSync Polarity

pub fn ar(&mut self) -> AR_W<'_>[src]

Bit 6 - Automatic Refresh

pub fn tepol(&mut self) -> TEPOL_W<'_>[src]

Bit 5 - TE Polarity

pub fn tesrc(&mut self) -> TESRC_W<'_>[src]

Bit 4 - TE Source

pub fn colmux(&mut self) -> COLMUX_W<'_>[src]

Bits 1:3 - Color Multiplexing

pub fn dsim(&mut self) -> DSIM_W<'_>[src]

Bit 0 - DSI Mode

impl W<u32, Reg<u32, _DSI_WCR>>[src]

pub fn dsien(&mut self) -> DSIEN_W<'_>[src]

Bit 3 - DSI Enable

pub fn ltdcen(&mut self) -> LTDCEN_W<'_>[src]

Bit 2 - LTDC Enable

pub fn shtdn(&mut self) -> SHTDN_W<'_>[src]

Bit 1 - Shutdown

pub fn colm(&mut self) -> COLM_W<'_>[src]

Bit 0 - Color Mode

impl W<u32, Reg<u32, _DSI_WIER>>[src]

pub fn rrie(&mut self) -> RRIE_W<'_>[src]

Bit 13 - Regulator Ready Interrupt Enable

pub fn plluie(&mut self) -> PLLUIE_W<'_>[src]

Bit 10 - PLL Unlock Interrupt Enable

pub fn plllie(&mut self) -> PLLLIE_W<'_>[src]

Bit 9 - PLL Lock Interrupt Enable

pub fn erie(&mut self) -> ERIE_W<'_>[src]

Bit 1 - End of Refresh Interrupt Enable

pub fn teie(&mut self) -> TEIE_W<'_>[src]

Bit 0 - Tearing Effect Interrupt Enable

impl W<u32, Reg<u32, _DSI_WIFCR>>[src]

pub fn crrif(&mut self) -> CRRIF_W<'_>[src]

Bit 13 - Clear Regulator Ready Interrupt Flag

pub fn cplluif(&mut self) -> CPLLUIF_W<'_>[src]

Bit 10 - Clear PLL Unlock Interrupt Flag

pub fn cplllif(&mut self) -> CPLLLIF_W<'_>[src]

Bit 9 - Clear PLL Lock Interrupt Flag

pub fn cerif(&mut self) -> CERIF_W<'_>[src]

Bit 1 - Clear End of Refresh Interrupt Flag

pub fn cteif(&mut self) -> CTEIF_W<'_>[src]

Bit 0 - Clear Tearing Effect Interrupt Flag

impl W<u32, Reg<u32, _DSI_WPCR1>>[src]

pub fn tclkposten(&mut self) -> TCLKPOSTEN_W<'_>[src]

Bit 27 - custom time for tCLK-POST Enable

pub fn tlpxcen(&mut self) -> TLPXCEN_W<'_>[src]

Bit 26 - custom time for tLPX for Clock lane Enable

pub fn thsexiten(&mut self) -> THSEXITEN_W<'_>[src]

Bit 25 - custom time for tHS-EXIT Enable

pub fn tlpxden(&mut self) -> TLPXDEN_W<'_>[src]

Bit 24 - custom time for tLPX for Data lanes Enable

pub fn thszeroen(&mut self) -> THSZEROEN_W<'_>[src]

Bit 23 - custom time for tHS-ZERO Enable

pub fn thstrailen(&mut self) -> THSTRAILEN_W<'_>[src]

Bit 22 - custom time for tHS-TRAIL Enable

pub fn thsprepen(&mut self) -> THSPREPEN_W<'_>[src]

Bit 21 - custom time for tHS-PREPARE Enable

pub fn tclkzeroen(&mut self) -> TCLKZEROEN_W<'_>[src]

Bit 20 - custom time for tCLK-ZERO Enable

pub fn tclkprepen(&mut self) -> TCLKPREPEN_W<'_>[src]

Bit 19 - custom time for tCLK-PREPARE Enable

pub fn pden(&mut self) -> PDEN_W<'_>[src]

Bit 18 - Pull-Down Enable

pub fn tddl(&mut self) -> TDDL_W<'_>[src]

Bit 16 - Turn Disable Data Lanes

pub fn cdoffdl(&mut self) -> CDOFFDL_W<'_>[src]

Bit 14 - Contention Detection OFF on Data Lanes

pub fn ftxsmdl(&mut self) -> FTXSMDL_W<'_>[src]

Bit 13 - Force in TX Stop Mode the Data Lanes

pub fn ftxsmcl(&mut self) -> FTXSMCL_W<'_>[src]

Bit 12 - Force in TX Stop Mode the Clock Lane

pub fn hsidl1(&mut self) -> HSIDL1_W<'_>[src]

Bit 11 - Invert the High-Speed data signal on Data Lane 1

pub fn hsidl0(&mut self) -> HSIDL0_W<'_>[src]

Bit 10 - Invert the Hight-Speed data signal on Data Lane 0

pub fn hsicl(&mut self) -> HSICL_W<'_>[src]

Bit 9 - Invert Hight-Speed data signal on Clock Lane

pub fn swdl1(&mut self) -> SWDL1_W<'_>[src]

Bit 8 - Swap Data Lane 1 pins

pub fn swdl0(&mut self) -> SWDL0_W<'_>[src]

Bit 7 - Swap Data Lane 0 pins

pub fn swcl(&mut self) -> SWCL_W<'_>[src]

Bit 6 - Swap Clock Lane pins

pub fn uix4(&mut self) -> UIX4_W<'_>[src]

Bits 0:5 - Unit Interval multiplied by 4

impl W<u32, Reg<u32, _DSI_WPCR2>>[src]

pub fn lprxft(&mut self) -> LPRXFT_W<'_>[src]

Bits 25:26 - Low-Power RX low-pass Filtering Tuning

pub fn flprxlpm(&mut self) -> FLPRXLPM_W<'_>[src]

Bit 22 - Forces LP Receiver in Low-Power Mode

pub fn hstxsrcdl(&mut self) -> HSTXSRCDL_W<'_>[src]

Bits 18:19 - High-Speed Transmission Slew Rate Control on Data Lanes

pub fn hstxsrccl(&mut self) -> HSTXSRCCL_W<'_>[src]

Bits 16:17 - High-Speed Transmission Slew Rate Control on Clock Lane

pub fn sdcc(&mut self) -> SDCC_W<'_>[src]

Bit 12 - SDD Control

pub fn lpsrdl(&mut self) -> LPSRDL_W<'_>[src]

Bits 8:9 - Low-Power transmission Slew Rate Compensation on Data Lanes

pub fn lpsrcl(&mut self) -> LPSRCL_W<'_>[src]

Bits 6:7 - Low-Power transmission Slew Rate Compensation on Clock Lane

pub fn hstxdll(&mut self) -> HSTXDLL_W<'_>[src]

Bits 2:3 - High-Speed Transmission Delay on Data Lanes

pub fn hstxdcl(&mut self) -> HSTXDCL_W<'_>[src]

Bits 0:1 - High-Speed Transmission Delay on Clock Lane

impl W<u32, Reg<u32, _DSI_WPCR3>>[src]

pub fn thstrail(&mut self) -> THSTRAIL_W<'_>[src]

Bits 24:31 - tHSTRAIL

pub fn thsprep(&mut self) -> THSPREP_W<'_>[src]

Bits 16:23 - tHS-PREPARE

pub fn tclkzeo(&mut self) -> TCLKZEO_W<'_>[src]

Bits 8:15 - tCLK-ZERO

pub fn tclkprep(&mut self) -> TCLKPREP_W<'_>[src]

Bits 0:7 - tCLK-PREPARE

impl W<u32, Reg<u32, _DSI_WPCR4>>[src]

pub fn tlpxc(&mut self) -> TLPXC_W<'_>[src]

Bits 24:31 - tLPXC for Clock lane

pub fn thsexit(&mut self) -> THSEXIT_W<'_>[src]

Bits 16:23 - tHSEXIT

pub fn tlpxd(&mut self) -> TLPXD_W<'_>[src]

Bits 8:15 - tLPX for Data lanes

pub fn thszero(&mut self) -> THSZERO_W<'_>[src]

Bits 0:7 - tHS-ZERO

impl W<u32, Reg<u32, _DSI_WPCR5>>[src]

pub fn thszero(&mut self) -> THSZERO_W<'_>[src]

Bits 0:7 - tCLK-POST

impl W<u32, Reg<u32, _DSI_WRPCR>>[src]

pub fn regen(&mut self) -> REGEN_W<'_>[src]

Bit 24 - Regulator Enable

pub fn odf(&mut self) -> ODF_W<'_>[src]

Bits 16:17 - PLL Output Division Factor

pub fn idf(&mut self) -> IDF_W<'_>[src]

Bits 11:14 - PLL Input Division Factor

pub fn ndiv(&mut self) -> NDIV_W<'_>[src]

Bits 2:8 - PLL Loop Division Factor

pub fn pllen(&mut self) -> PLLEN_W<'_>[src]

Bit 0 - PLL Enable

impl W<u32, Reg<u32, _CSR>>[src]

pub fn enable(&mut self) -> ENABLE_W<'_>[src]

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>[src]

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>[src]

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>[src]

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _RVR>>[src]

pub fn reload(&mut self) -> RELOAD_W<'_>[src]

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _CVR>>[src]

pub fn current(&mut self) -> CURRENT_W<'_>[src]

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>[src]

pub fn tenms(&mut self) -> TENMS_W<'_>[src]

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>[src]

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>[src]

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>[src]

pub fn intid(&mut self) -> INTID_W<'_>[src]

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>[src]

pub fn cp(&mut self) -> CP_W<'_>[src]

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>[src]

pub fn disfold(&mut self) -> DISFOLD_W<'_>[src]

Bit 2 - DISFOLD

pub fn fpexcodis(&mut self) -> FPEXCODIS_W<'_>[src]

Bit 10 - FPEXCODIS

pub fn disramode(&mut self) -> DISRAMODE_W<'_>[src]

Bit 11 - DISRAMODE

pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W<'_>[src]

Bit 12 - DISITMATBFLUSH

impl W<u32, Reg<u32, _ITCMCR>>[src]

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - EN

pub fn rmw(&mut self) -> RMW_W<'_>[src]

Bit 1 - RMW

pub fn reten(&mut self) -> RETEN_W<'_>[src]

Bit 2 - RETEN

pub fn sz(&mut self) -> SZ_W<'_>[src]

Bits 3:6 - SZ

impl W<u32, Reg<u32, _DTCMCR>>[src]

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - EN

pub fn rmw(&mut self) -> RMW_W<'_>[src]

Bit 1 - RMW

pub fn reten(&mut self) -> RETEN_W<'_>[src]

Bit 2 - RETEN

pub fn sz(&mut self) -> SZ_W<'_>[src]

Bits 3:6 - SZ

impl W<u32, Reg<u32, _AHBPCR>>[src]

pub fn en(&mut self) -> EN_W<'_>[src]

Bit 0 - EN

pub fn sz(&mut self) -> SZ_W<'_>[src]

Bits 1:3 - SZ

impl W<u32, Reg<u32, _CACR>>[src]

pub fn siwt(&mut self) -> SIWT_W<'_>[src]

Bit 0 - SIWT

pub fn eccen(&mut self) -> ECCEN_W<'_>[src]

Bit 1 - ECCEN

pub fn forcewt(&mut self) -> FORCEWT_W<'_>[src]

Bit 2 - FORCEWT

impl W<u32, Reg<u32, _AHBSCR>>[src]

pub fn ctl(&mut self) -> CTL_W<'_>[src]

Bits 0:1 - CTL

pub fn tpri(&mut self) -> TPRI_W<'_>[src]

Bits 2:10 - TPRI

pub fn initcount(&mut self) -> INITCOUNT_W<'_>[src]

Bits 11:15 - INITCOUNT

impl W<u32, Reg<u32, _ABFSR>>[src]

pub fn itcm(&mut self) -> ITCM_W<'_>[src]

Bit 0 - ITCM

pub fn dtcm(&mut self) -> DTCM_W<'_>[src]

Bit 1 - DTCM

pub fn ahbp(&mut self) -> AHBP_W<'_>[src]

Bit 2 - AHBP

pub fn axim(&mut self) -> AXIM_W<'_>[src]

Bit 3 - AXIM

pub fn eppb(&mut self) -> EPPB_W<'_>[src]

Bit 4 - EPPB

pub fn aximtype(&mut self) -> AXIMTYPE_W<'_>[src]

Bits 8:9 - AXIMTYPE

impl W<u32, Reg<u32, _CCR>>[src]

pub fn tsvrefe(&mut self) -> TSVREFE_W<'_>[src]

Bit 23 - Temperature sensor and V_REFINT enable

pub fn vbate(&mut self) -> VBATE_W<'_>[src]

Bit 22 - V_BAT enable

pub fn adcpre(&mut self) -> ADCPRE_W<'_>[src]

Bits 16:17 - ADC prescaler

pub fn dma(&mut self) -> DMA_W<'_>[src]

Bits 14:15 - Direct memory access mode for multi ADC mode

pub fn dds(&mut self) -> DDS_W<'_>[src]

Bit 13 - DMA disable selection (for multi-ADC mode)

pub fn delay(&mut self) -> DELAY_W<'_>[src]

Bits 8:11 - Delay between 2 sampling phases

pub fn multi(&mut self) -> MULTI_W<'_>[src]

Bits 0:3 - Multi ADC mode selection

impl W<u32, Reg<u32, _CR>>[src]

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>[src]

Bit 0 - DBG_SLEEP

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>[src]

Bit 1 - DBG_STOP

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>[src]

Bit 2 - DBG_STANDBY

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>[src]

Bit 5 - TRACE_IOEN

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>[src]

Bits 6:7 - TRACE_MODE

impl W<u32, Reg<u32, _APB1_FZ>>[src]

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>[src]

Bit 0 - DBG_TIM2_STOP

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>[src]

Bit 1 - DBG_TIM3_STOP

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>[src]

Bit 2 - DBG_TIM4_STOP

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>[src]

Bit 3 - DBG_TIM5_STOP

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>[src]

Bit 4 - DBG_TIM6_STOP

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>[src]

Bit 5 - DBG_TIM7_STOP

pub fn dbg_tim12_stop(&mut self) -> DBG_TIM12_STOP_W<'_>[src]

Bit 6 - DBG_TIM12_STOP

pub fn dbg_tim13_stop(&mut self) -> DBG_TIM13_STOP_W<'_>[src]

Bit 7 - DBG_TIM13_STOP

pub fn dbg_tim14_stop(&mut self) -> DBG_TIM14_STOP_W<'_>[src]

Bit 8 - DBG_TIM14_STOP

pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W<'_>[src]

Bit 9 - DBG_LPTIM1_STOP

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>[src]

Bit 10 - DBG_RTC_STOP

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>[src]

Bit 11 - DBG_WWDG_STOP

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>[src]

Bit 12 - DBG_IWDG_STOP

pub fn dbg_can3_stop(&mut self) -> DBG_CAN3_STOP_W<'_>[src]

Bit 13 - DBG_CAN3_STOP

pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W<'_>[src]

Bit 21 - DBG_I2C1_SMBUS_TIMEOUT

pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W<'_>[src]

Bit 22 - DBG_I2C2_SMBUS_TIMEOUT

pub fn dbg_i2c3_smbus_timeout(&mut self) -> DBG_I2C3_SMBUS_TIMEOUT_W<'_>[src]

Bit 23 - DBG_I2C3_SMBUS_TIMEOUT

pub fn dbg_i2c4_smbus_timeout(&mut self) -> DBG_I2C4_SMBUS_TIMEOUT_W<'_>[src]

Bit 24 - DBG_I2C4SMBUS_TIMEOUT

pub fn dbg_can1_stop(&mut self) -> DBG_CAN1_STOP_W<'_>[src]

Bit 25 - DBG_CAN1_STOP

pub fn dbg_can2_stop(&mut self) -> DBG_CAN2_STOP_W<'_>[src]

Bit 26 - DBG_CAN2_STOP

impl W<u32, Reg<u32, _APB2_FZ>>[src]

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>[src]

Bit 0 - TIM1 counter stopped when core is halted

pub fn dbg_tim8_stop(&mut self) -> DBG_TIM8_STOP_W<'_>[src]

Bit 1 - TIM8 counter stopped when core is halted

pub fn dbg_tim9_stop(&mut self) -> DBG_TIM9_STOP_W<'_>[src]

Bit 16 - TIM9 counter stopped when core is halted

pub fn dbg_tim10_stop(&mut self) -> DBG_TIM10_STOP_W<'_>[src]

Bit 17 - TIM10 counter stopped when core is halted

pub fn dbg_tim11_stop(&mut self) -> DBG_TIM11_STOP_W<'_>[src]

Bit 18 - TIM11 counter stopped when core is halted

Auto Trait Implementations

impl<U, REG> Send for W<U, REG> where
    REG: Send,
    U: Send, [src]

impl<U, REG> Sync for W<U, REG> where
    REG: Sync,
    U: Sync, [src]

impl<U, REG> Unpin for W<U, REG> where
    REG: Unpin,
    U: Unpin, [src]

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.