Enum stm32f7::stm32f7x9::rcc::pllsaicfgr::PLLSAIP_A

#[repr(u8)]pub enum PLLSAIP_A {
    DIV2,
    DIV4,
    DIV6,
    DIV8,
}

PLLSAI division factor for 48MHz clock

Value on reset: 0

Variants

DIV2

0: PLL*P=2

DIV4

1: PLL*P=4

DIV6

2: PLL*P=6

DIV8

3: PLL*P=8

Trait Implementations

impl Clone for PLLSAIP_A

fn clone(&self) -> PLLSAIP_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for PLLSAIP_A

impl Debug for PLLSAIP_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<PLLSAIP_A> for u8

fn from(variant: PLLSAIP_A) -> Self

Performs the conversion.

impl PartialEq<PLLSAIP_A> for PLLSAIP_A

fn eq(&self, other: &PLLSAIP_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for PLLSAIP_A