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#[doc = "Reader of register DFSDM_CHCFG0R1"] pub type R = crate::R<u32, super::DFSDM_CHCFG0R1>; #[doc = "Writer for register DFSDM_CHCFG0R1"] pub type W = crate::W<u32, super::DFSDM_CHCFG0R1>; #[doc = "Register DFSDM_CHCFG0R1 `reset()`'s with value 0"] impl crate::ResetValue for super::DFSDM_CHCFG0R1 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `SITP`"] pub type SITP_R = crate::R<u8, u8>; #[doc = "Write proxy for field `SITP`"] pub struct SITP_W<'a> { w: &'a mut W, } impl<'a> SITP_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); self.w } } #[doc = "Reader of field `SPICKSEL`"] pub type SPICKSEL_R = crate::R<u8, u8>; #[doc = "Write proxy for field `SPICKSEL`"] pub struct SPICKSEL_W<'a> { w: &'a mut W, } impl<'a> SPICKSEL_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2); self.w } } #[doc = "Reader of field `SCDEN`"] pub type SCDEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SCDEN`"] pub struct SCDEN_W<'a> { w: &'a mut W, } impl<'a> SCDEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); self.w } } #[doc = "Reader of field `CKABEN`"] pub type CKABEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CKABEN`"] pub struct CKABEN_W<'a> { w: &'a mut W, } impl<'a> CKABEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6); self.w } } #[doc = "Reader of field `CHEN`"] pub type CHEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CHEN`"] pub struct CHEN_W<'a> { w: &'a mut W, } impl<'a> CHEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); self.w } } #[doc = "Reader of field `CHINSEL`"] pub type CHINSEL_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CHINSEL`"] pub struct CHINSEL_W<'a> { w: &'a mut W, } impl<'a> CHINSEL_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `DATMPX`"] pub type DATMPX_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DATMPX`"] pub struct DATMPX_W<'a> { w: &'a mut W, } impl<'a> DATMPX_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12); self.w } } #[doc = "Reader of field `DATPACK`"] pub type DATPACK_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DATPACK`"] pub struct DATPACK_W<'a> { w: &'a mut W, } impl<'a> DATPACK_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14); self.w } } #[doc = "Reader of field `CKOUTDIV`"] pub type CKOUTDIV_R = crate::R<u8, u8>; #[doc = "Write proxy for field `CKOUTDIV`"] pub struct CKOUTDIV_W<'a> { w: &'a mut W, } impl<'a> CKOUTDIV_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16); self.w } } #[doc = "Reader of field `CKOUTSRC`"] pub type CKOUTSRC_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CKOUTSRC`"] pub struct CKOUTSRC_W<'a> { w: &'a mut W, } impl<'a> CKOUTSRC_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); self.w } } #[doc = "Reader of field `DFSDMEN`"] pub type DFSDMEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DFSDMEN`"] pub struct DFSDMEN_W<'a> { w: &'a mut W, } impl<'a> DFSDMEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); self.w } } impl R { #[doc = "Bits 0:1 - Serial interface type for channel 0"] #[inline(always)] pub fn sitp(&self) -> SITP_R { SITP_R::new((self.bits & 0x03) as u8) } #[doc = "Bits 2:3 - SPI clock select for channel 0"] #[inline(always)] pub fn spicksel(&self) -> SPICKSEL_R { SPICKSEL_R::new(((self.bits >> 2) & 0x03) as u8) } #[doc = "Bit 5 - Short-circuit detector enable on channel 0"] #[inline(always)] pub fn scden(&self) -> SCDEN_R { SCDEN_R::new(((self.bits >> 5) & 0x01) != 0) } #[doc = "Bit 6 - Clock absence detector enable on channel 0"] #[inline(always)] pub fn ckaben(&self) -> CKABEN_R { CKABEN_R::new(((self.bits >> 6) & 0x01) != 0) } #[doc = "Bit 7 - Channel 0 enable"] #[inline(always)] pub fn chen(&self) -> CHEN_R { CHEN_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bit 8 - Channel inputs selection"] #[inline(always)] pub fn chinsel(&self) -> CHINSEL_R { CHINSEL_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bits 12:13 - Input data multiplexer for channel 0"] #[inline(always)] pub fn datmpx(&self) -> DATMPX_R { DATMPX_R::new(((self.bits >> 12) & 0x03) as u8) } #[doc = "Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register"] #[inline(always)] pub fn datpack(&self) -> DATPACK_R { DATPACK_R::new(((self.bits >> 14) & 0x03) as u8) } #[doc = "Bits 16:23 - Output serial clock divider"] #[inline(always)] pub fn ckoutdiv(&self) -> CKOUTDIV_R { CKOUTDIV_R::new(((self.bits >> 16) & 0xff) as u8) } #[doc = "Bit 30 - Output serial clock source selection"] #[inline(always)] pub fn ckoutsrc(&self) -> CKOUTSRC_R { CKOUTSRC_R::new(((self.bits >> 30) & 0x01) != 0) } #[doc = "Bit 31 - Global enable for DFSDM interface"] #[inline(always)] pub fn dfsdmen(&self) -> DFSDMEN_R { DFSDMEN_R::new(((self.bits >> 31) & 0x01) != 0) } } impl W { #[doc = "Bits 0:1 - Serial interface type for channel 0"] #[inline(always)] pub fn sitp(&mut self) -> SITP_W { SITP_W { w: self } } #[doc = "Bits 2:3 - SPI clock select for channel 0"] #[inline(always)] pub fn spicksel(&mut self) -> SPICKSEL_W { SPICKSEL_W { w: self } } #[doc = "Bit 5 - Short-circuit detector enable on channel 0"] #[inline(always)] pub fn scden(&mut self) -> SCDEN_W { SCDEN_W { w: self } } #[doc = "Bit 6 - Clock absence detector enable on channel 0"] #[inline(always)] pub fn ckaben(&mut self) -> CKABEN_W { CKABEN_W { w: self } } #[doc = "Bit 7 - Channel 0 enable"] #[inline(always)] pub fn chen(&mut self) -> CHEN_W { CHEN_W { w: self } } #[doc = "Bit 8 - Channel inputs selection"] #[inline(always)] pub fn chinsel(&mut self) -> CHINSEL_W { CHINSEL_W { w: self } } #[doc = "Bits 12:13 - Input data multiplexer for channel 0"] #[inline(always)] pub fn datmpx(&mut self) -> DATMPX_W { DATMPX_W { w: self } } #[doc = "Bits 14:15 - Data packing mode in DFSDM_CHDATINyR register"] #[inline(always)] pub fn datpack(&mut self) -> DATPACK_W { DATPACK_W { w: self } } #[doc = "Bits 16:23 - Output serial clock divider"] #[inline(always)] pub fn ckoutdiv(&mut self) -> CKOUTDIV_W { CKOUTDIV_W { w: self } } #[doc = "Bit 30 - Output serial clock source selection"] #[inline(always)] pub fn ckoutsrc(&mut self) -> CKOUTSRC_W { CKOUTSRC_W { w: self } } #[doc = "Bit 31 - Global enable for DFSDM interface"] #[inline(always)] pub fn dfsdmen(&mut self) -> DFSDMEN_W { DFSDMEN_W { w: self } } }