stm32f7_staging/stm32f779/tim3/
dier.rs

1///Register `DIER` reader
2pub type R = crate::R<DIERrs>;
3///Register `DIER` writer
4pub type W = crate::W<DIERrs>;
5/**Update interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum UIE {
11    ///0: Update interrupt disabled
12    Disabled = 0,
13    ///1: Update interrupt enabled
14    Enabled = 1,
15}
16impl From<UIE> for bool {
17    #[inline(always)]
18    fn from(variant: UIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `UIE` reader - Update interrupt enable
23pub type UIE_R = crate::BitReader<UIE>;
24impl UIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> UIE {
28        match self.bits {
29            false => UIE::Disabled,
30            true => UIE::Enabled,
31        }
32    }
33    ///Update interrupt disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == UIE::Disabled
37    }
38    ///Update interrupt enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == UIE::Enabled
42    }
43}
44///Field `UIE` writer - Update interrupt enable
45pub type UIE_W<'a, REG> = crate::BitWriter<'a, REG, UIE>;
46impl<'a, REG> UIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Update interrupt disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(UIE::Disabled)
54    }
55    ///Update interrupt enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(UIE::Enabled)
59    }
60}
61/**Capture/Compare %s interrupt enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1IE {
67    ///0: CCx interrupt disabled
68    Disabled = 0,
69    ///1: CCx interrupt enabled
70    Enabled = 1,
71}
72impl From<CC1IE> for bool {
73    #[inline(always)]
74    fn from(variant: CC1IE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCIE(1-4)` reader - Capture/Compare %s interrupt enable
79pub type CCIE_R = crate::BitReader<CC1IE>;
80impl CCIE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1IE {
84        match self.bits {
85            false => CC1IE::Disabled,
86            true => CC1IE::Enabled,
87        }
88    }
89    ///CCx interrupt disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == CC1IE::Disabled
93    }
94    ///CCx interrupt enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == CC1IE::Enabled
98    }
99}
100///Field `CCIE(1-4)` writer - Capture/Compare %s interrupt enable
101pub type CCIE_W<'a, REG> = crate::BitWriter<'a, REG, CC1IE>;
102impl<'a, REG> CCIE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///CCx interrupt disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1IE::Disabled)
110    }
111    ///CCx interrupt enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1IE::Enabled)
115    }
116}
117/**Trigger interrupt enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum TIE {
123    ///0: Trigger interrupt disabled
124    Disabled = 0,
125    ///1: Trigger interrupt enabled
126    Enabled = 1,
127}
128impl From<TIE> for bool {
129    #[inline(always)]
130    fn from(variant: TIE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `TIE` reader - Trigger interrupt enable
135pub type TIE_R = crate::BitReader<TIE>;
136impl TIE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> TIE {
140        match self.bits {
141            false => TIE::Disabled,
142            true => TIE::Enabled,
143        }
144    }
145    ///Trigger interrupt disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == TIE::Disabled
149    }
150    ///Trigger interrupt enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == TIE::Enabled
154    }
155}
156///Field `TIE` writer - Trigger interrupt enable
157pub type TIE_W<'a, REG> = crate::BitWriter<'a, REG, TIE>;
158impl<'a, REG> TIE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Trigger interrupt disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(TIE::Disabled)
166    }
167    ///Trigger interrupt enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(TIE::Enabled)
171    }
172}
173/**Update DMA request enable
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum UDE {
179    ///0: Update DMA request disabled
180    Disabled = 0,
181    ///1: Update DMA request enabled
182    Enabled = 1,
183}
184impl From<UDE> for bool {
185    #[inline(always)]
186    fn from(variant: UDE) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `UDE` reader - Update DMA request enable
191pub type UDE_R = crate::BitReader<UDE>;
192impl UDE_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> UDE {
196        match self.bits {
197            false => UDE::Disabled,
198            true => UDE::Enabled,
199        }
200    }
201    ///Update DMA request disabled
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == UDE::Disabled
205    }
206    ///Update DMA request enabled
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == UDE::Enabled
210    }
211}
212///Field `UDE` writer - Update DMA request enable
213pub type UDE_W<'a, REG> = crate::BitWriter<'a, REG, UDE>;
214impl<'a, REG> UDE_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Update DMA request disabled
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(UDE::Disabled)
222    }
223    ///Update DMA request enabled
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(UDE::Enabled)
227    }
228}
229/**Capture/Compare %s DMA request enable
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum CC1DE {
235    ///0: CCx DMA request disabled
236    Disabled = 0,
237    ///1: CCx DMA request enabled
238    Enabled = 1,
239}
240impl From<CC1DE> for bool {
241    #[inline(always)]
242    fn from(variant: CC1DE) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `CCDE(1-4)` reader - Capture/Compare %s DMA request enable
247pub type CCDE_R = crate::BitReader<CC1DE>;
248impl CCDE_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> CC1DE {
252        match self.bits {
253            false => CC1DE::Disabled,
254            true => CC1DE::Enabled,
255        }
256    }
257    ///CCx DMA request disabled
258    #[inline(always)]
259    pub fn is_disabled(&self) -> bool {
260        *self == CC1DE::Disabled
261    }
262    ///CCx DMA request enabled
263    #[inline(always)]
264    pub fn is_enabled(&self) -> bool {
265        *self == CC1DE::Enabled
266    }
267}
268///Field `CCDE(1-4)` writer - Capture/Compare %s DMA request enable
269pub type CCDE_W<'a, REG> = crate::BitWriter<'a, REG, CC1DE>;
270impl<'a, REG> CCDE_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///CCx DMA request disabled
275    #[inline(always)]
276    pub fn disabled(self) -> &'a mut crate::W<REG> {
277        self.variant(CC1DE::Disabled)
278    }
279    ///CCx DMA request enabled
280    #[inline(always)]
281    pub fn enabled(self) -> &'a mut crate::W<REG> {
282        self.variant(CC1DE::Enabled)
283    }
284}
285/**Trigger DMA request enable
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum TDE {
291    ///0: Trigger DMA request disabled
292    Disabled = 0,
293    ///1: Trigger DMA request enabled
294    Enabled = 1,
295}
296impl From<TDE> for bool {
297    #[inline(always)]
298    fn from(variant: TDE) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `TDE` reader - Trigger DMA request enable
303pub type TDE_R = crate::BitReader<TDE>;
304impl TDE_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> TDE {
308        match self.bits {
309            false => TDE::Disabled,
310            true => TDE::Enabled,
311        }
312    }
313    ///Trigger DMA request disabled
314    #[inline(always)]
315    pub fn is_disabled(&self) -> bool {
316        *self == TDE::Disabled
317    }
318    ///Trigger DMA request enabled
319    #[inline(always)]
320    pub fn is_enabled(&self) -> bool {
321        *self == TDE::Enabled
322    }
323}
324///Field `TDE` writer - Trigger DMA request enable
325pub type TDE_W<'a, REG> = crate::BitWriter<'a, REG, TDE>;
326impl<'a, REG> TDE_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///Trigger DMA request disabled
331    #[inline(always)]
332    pub fn disabled(self) -> &'a mut crate::W<REG> {
333        self.variant(TDE::Disabled)
334    }
335    ///Trigger DMA request enabled
336    #[inline(always)]
337    pub fn enabled(self) -> &'a mut crate::W<REG> {
338        self.variant(TDE::Enabled)
339    }
340}
341impl R {
342    ///Bit 0 - Update interrupt enable
343    #[inline(always)]
344    pub fn uie(&self) -> UIE_R {
345        UIE_R::new((self.bits & 1) != 0)
346    }
347    ///Capture/Compare (1-4) interrupt enable
348    ///
349    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IE` field.</div>
350    #[inline(always)]
351    pub fn ccie(&self, n: u8) -> CCIE_R {
352        #[allow(clippy::no_effect)]
353        [(); 4][n as usize];
354        CCIE_R::new(((self.bits >> (n + 1)) & 1) != 0)
355    }
356    ///Iterator for array of:
357    ///Capture/Compare (1-4) interrupt enable
358    #[inline(always)]
359    pub fn ccie_iter(&self) -> impl Iterator<Item = CCIE_R> + '_ {
360        (0..4).map(move |n| CCIE_R::new(((self.bits >> (n + 1)) & 1) != 0))
361    }
362    ///Bit 1 - Capture/Compare 1 interrupt enable
363    #[inline(always)]
364    pub fn cc1ie(&self) -> CCIE_R {
365        CCIE_R::new(((self.bits >> 1) & 1) != 0)
366    }
367    ///Bit 2 - Capture/Compare 2 interrupt enable
368    #[inline(always)]
369    pub fn cc2ie(&self) -> CCIE_R {
370        CCIE_R::new(((self.bits >> 2) & 1) != 0)
371    }
372    ///Bit 3 - Capture/Compare 3 interrupt enable
373    #[inline(always)]
374    pub fn cc3ie(&self) -> CCIE_R {
375        CCIE_R::new(((self.bits >> 3) & 1) != 0)
376    }
377    ///Bit 4 - Capture/Compare 4 interrupt enable
378    #[inline(always)]
379    pub fn cc4ie(&self) -> CCIE_R {
380        CCIE_R::new(((self.bits >> 4) & 1) != 0)
381    }
382    ///Bit 6 - Trigger interrupt enable
383    #[inline(always)]
384    pub fn tie(&self) -> TIE_R {
385        TIE_R::new(((self.bits >> 6) & 1) != 0)
386    }
387    ///Bit 8 - Update DMA request enable
388    #[inline(always)]
389    pub fn ude(&self) -> UDE_R {
390        UDE_R::new(((self.bits >> 8) & 1) != 0)
391    }
392    ///Capture/Compare (1-4) DMA request enable
393    ///
394    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1DE` field.</div>
395    #[inline(always)]
396    pub fn ccde(&self, n: u8) -> CCDE_R {
397        #[allow(clippy::no_effect)]
398        [(); 4][n as usize];
399        CCDE_R::new(((self.bits >> (n + 9)) & 1) != 0)
400    }
401    ///Iterator for array of:
402    ///Capture/Compare (1-4) DMA request enable
403    #[inline(always)]
404    pub fn ccde_iter(&self) -> impl Iterator<Item = CCDE_R> + '_ {
405        (0..4).map(move |n| CCDE_R::new(((self.bits >> (n + 9)) & 1) != 0))
406    }
407    ///Bit 9 - Capture/Compare 1 DMA request enable
408    #[inline(always)]
409    pub fn cc1de(&self) -> CCDE_R {
410        CCDE_R::new(((self.bits >> 9) & 1) != 0)
411    }
412    ///Bit 10 - Capture/Compare 2 DMA request enable
413    #[inline(always)]
414    pub fn cc2de(&self) -> CCDE_R {
415        CCDE_R::new(((self.bits >> 10) & 1) != 0)
416    }
417    ///Bit 11 - Capture/Compare 3 DMA request enable
418    #[inline(always)]
419    pub fn cc3de(&self) -> CCDE_R {
420        CCDE_R::new(((self.bits >> 11) & 1) != 0)
421    }
422    ///Bit 12 - Capture/Compare 4 DMA request enable
423    #[inline(always)]
424    pub fn cc4de(&self) -> CCDE_R {
425        CCDE_R::new(((self.bits >> 12) & 1) != 0)
426    }
427    ///Bit 14 - Trigger DMA request enable
428    #[inline(always)]
429    pub fn tde(&self) -> TDE_R {
430        TDE_R::new(((self.bits >> 14) & 1) != 0)
431    }
432}
433impl core::fmt::Debug for R {
434    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
435        f.debug_struct("DIER")
436            .field("tde", &self.tde())
437            .field("cc1de", &self.cc1de())
438            .field("cc2de", &self.cc2de())
439            .field("cc3de", &self.cc3de())
440            .field("cc4de", &self.cc4de())
441            .field("ude", &self.ude())
442            .field("tie", &self.tie())
443            .field("cc1ie", &self.cc1ie())
444            .field("cc2ie", &self.cc2ie())
445            .field("cc3ie", &self.cc3ie())
446            .field("cc4ie", &self.cc4ie())
447            .field("uie", &self.uie())
448            .finish()
449    }
450}
451impl W {
452    ///Bit 0 - Update interrupt enable
453    #[inline(always)]
454    pub fn uie(&mut self) -> UIE_W<DIERrs> {
455        UIE_W::new(self, 0)
456    }
457    ///Capture/Compare (1-4) interrupt enable
458    ///
459    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IE` field.</div>
460    #[inline(always)]
461    pub fn ccie(&mut self, n: u8) -> CCIE_W<DIERrs> {
462        #[allow(clippy::no_effect)]
463        [(); 4][n as usize];
464        CCIE_W::new(self, n + 1)
465    }
466    ///Bit 1 - Capture/Compare 1 interrupt enable
467    #[inline(always)]
468    pub fn cc1ie(&mut self) -> CCIE_W<DIERrs> {
469        CCIE_W::new(self, 1)
470    }
471    ///Bit 2 - Capture/Compare 2 interrupt enable
472    #[inline(always)]
473    pub fn cc2ie(&mut self) -> CCIE_W<DIERrs> {
474        CCIE_W::new(self, 2)
475    }
476    ///Bit 3 - Capture/Compare 3 interrupt enable
477    #[inline(always)]
478    pub fn cc3ie(&mut self) -> CCIE_W<DIERrs> {
479        CCIE_W::new(self, 3)
480    }
481    ///Bit 4 - Capture/Compare 4 interrupt enable
482    #[inline(always)]
483    pub fn cc4ie(&mut self) -> CCIE_W<DIERrs> {
484        CCIE_W::new(self, 4)
485    }
486    ///Bit 6 - Trigger interrupt enable
487    #[inline(always)]
488    pub fn tie(&mut self) -> TIE_W<DIERrs> {
489        TIE_W::new(self, 6)
490    }
491    ///Bit 8 - Update DMA request enable
492    #[inline(always)]
493    pub fn ude(&mut self) -> UDE_W<DIERrs> {
494        UDE_W::new(self, 8)
495    }
496    ///Capture/Compare (1-4) DMA request enable
497    ///
498    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1DE` field.</div>
499    #[inline(always)]
500    pub fn ccde(&mut self, n: u8) -> CCDE_W<DIERrs> {
501        #[allow(clippy::no_effect)]
502        [(); 4][n as usize];
503        CCDE_W::new(self, n + 9)
504    }
505    ///Bit 9 - Capture/Compare 1 DMA request enable
506    #[inline(always)]
507    pub fn cc1de(&mut self) -> CCDE_W<DIERrs> {
508        CCDE_W::new(self, 9)
509    }
510    ///Bit 10 - Capture/Compare 2 DMA request enable
511    #[inline(always)]
512    pub fn cc2de(&mut self) -> CCDE_W<DIERrs> {
513        CCDE_W::new(self, 10)
514    }
515    ///Bit 11 - Capture/Compare 3 DMA request enable
516    #[inline(always)]
517    pub fn cc3de(&mut self) -> CCDE_W<DIERrs> {
518        CCDE_W::new(self, 11)
519    }
520    ///Bit 12 - Capture/Compare 4 DMA request enable
521    #[inline(always)]
522    pub fn cc4de(&mut self) -> CCDE_W<DIERrs> {
523        CCDE_W::new(self, 12)
524    }
525    ///Bit 14 - Trigger DMA request enable
526    #[inline(always)]
527    pub fn tde(&mut self) -> TDE_W<DIERrs> {
528        TDE_W::new(self, 14)
529    }
530}
531/**DMA/Interrupt enable register
532
533You can [`read`](crate::Reg::read) this register and get [`dier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
534
535See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:DIER)*/
536pub struct DIERrs;
537impl crate::RegisterSpec for DIERrs {
538    type Ux = u32;
539}
540///`read()` method returns [`dier::R`](R) reader structure
541impl crate::Readable for DIERrs {}
542///`write(|w| ..)` method takes [`dier::W`](W) writer structure
543impl crate::Writable for DIERrs {
544    type Safety = crate::Unsafe;
545}
546///`reset()` method sets DIER to value 0
547impl crate::Resettable for DIERrs {}
stm32f7_staging/stm32f779/tim3/dier.rs

stm32f7_staging/stm32f779/tim3/
dier.rs
