stm32f7_staging/stm32f779/
tim3.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    _reserved12: [u8; 0x04],
18    ccr: [CCR; 4],
19    _reserved13: [u8; 0x04],
20    dcr: DCR,
21    dmar: DMAR,
22}
23impl RegisterBlock {
24    ///0x00 - control register 1
25    #[inline(always)]
26    pub const fn cr1(&self) -> &CR1 {
27        &self.cr1
28    }
29    ///0x04 - control register 2
30    #[inline(always)]
31    pub const fn cr2(&self) -> &CR2 {
32        &self.cr2
33    }
34    ///0x08 - slave mode control register
35    #[inline(always)]
36    pub const fn smcr(&self) -> &SMCR {
37        &self.smcr
38    }
39    ///0x0c - DMA/Interrupt enable register
40    #[inline(always)]
41    pub const fn dier(&self) -> &DIER {
42        &self.dier
43    }
44    ///0x10 - status register
45    #[inline(always)]
46    pub const fn sr(&self) -> &SR {
47        &self.sr
48    }
49    ///0x14 - event generation register
50    #[inline(always)]
51    pub const fn egr(&self) -> &EGR {
52        &self.egr
53    }
54    ///0x18 - capture/compare mode register 1 (input mode)
55    #[inline(always)]
56    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
57        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
58    }
59    ///0x18 - capture/compare mode register 1 (output mode)
60    #[inline(always)]
61    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
62        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
63    }
64    ///0x1c - capture/compare mode register 2 (input mode)
65    #[inline(always)]
66    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
67        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
68    }
69    ///0x1c - capture/compare mode register 2 (output mode)
70    #[inline(always)]
71    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
72        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
73    }
74    ///0x20 - capture/compare enable register
75    #[inline(always)]
76    pub const fn ccer(&self) -> &CCER {
77        &self.ccer
78    }
79    ///0x24 - counter
80    #[inline(always)]
81    pub const fn cnt(&self) -> &CNT {
82        &self.cnt
83    }
84    ///0x28 - prescaler
85    #[inline(always)]
86    pub const fn psc(&self) -> &PSC {
87        &self.psc
88    }
89    ///0x2c - auto-reload register
90    #[inline(always)]
91    pub const fn arr(&self) -> &ARR {
92        &self.arr
93    }
94    ///0x34..0x44 - capture/compare register
95    ///
96    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
97    #[inline(always)]
98    pub const fn ccr(&self, n: usize) -> &CCR {
99        &self.ccr[n]
100    }
101    ///Iterator for array of:
102    ///0x34..0x44 - capture/compare register
103    #[inline(always)]
104    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
105        self.ccr.iter()
106    }
107    ///0x34 - capture/compare register
108    #[inline(always)]
109    pub const fn ccr1(&self) -> &CCR {
110        self.ccr(0)
111    }
112    ///0x38 - capture/compare register
113    #[inline(always)]
114    pub const fn ccr2(&self) -> &CCR {
115        self.ccr(1)
116    }
117    ///0x3c - capture/compare register
118    #[inline(always)]
119    pub const fn ccr3(&self) -> &CCR {
120        self.ccr(2)
121    }
122    ///0x40 - capture/compare register
123    #[inline(always)]
124    pub const fn ccr4(&self) -> &CCR {
125        self.ccr(3)
126    }
127    ///0x48 - DMA control register
128    #[inline(always)]
129    pub const fn dcr(&self) -> &DCR {
130        &self.dcr
131    }
132    ///0x4c - DMA address for full transfer
133    #[inline(always)]
134    pub const fn dmar(&self) -> &DMAR {
135        &self.dmar
136    }
137}
138/**CR1 (rw) register accessor: control register 1
139
140You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
141
142See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:CR1)
143
144For information about available fields see [`mod@cr1`] module*/
145pub type CR1 = crate::Reg<cr1::CR1rs>;
146///control register 1
147pub mod cr1;
148/**CR2 (rw) register accessor: control register 2
149
150You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
151
152See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:CR2)
153
154For information about available fields see [`mod@cr2`] module*/
155pub type CR2 = crate::Reg<cr2::CR2rs>;
156///control register 2
157pub mod cr2;
158/**SMCR (rw) register accessor: slave mode control register
159
160You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:SMCR)
163
164For information about available fields see [`mod@smcr`] module*/
165pub type SMCR = crate::Reg<smcr::SMCRrs>;
166///slave mode control register
167pub mod smcr;
168/**DIER (rw) register accessor: DMA/Interrupt enable register
169
170You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
171
172See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:DIER)
173
174For information about available fields see [`mod@dier`] module*/
175pub type DIER = crate::Reg<dier::DIERrs>;
176///DMA/Interrupt enable register
177pub mod dier;
178/**SR (rw) register accessor: status register
179
180You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
181
182See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:SR)
183
184For information about available fields see [`mod@sr`] module*/
185pub type SR = crate::Reg<sr::SRrs>;
186///status register
187pub mod sr;
188/**EGR (w) register accessor: event generation register
189
190You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
191
192See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:EGR)
193
194For information about available fields see [`mod@egr`] module*/
195pub type EGR = crate::Reg<egr::EGRrs>;
196///event generation register
197pub mod egr;
198/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
199
200You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
201
202See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:CCMR1_Output)
203
204For information about available fields see [`mod@ccmr1_output`] module*/
205#[doc(alias = "CCMR1_Output")]
206pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
207///capture/compare mode register 1 (output mode)
208pub mod ccmr1_output;
209/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
210
211You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
212
213See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:CCMR1_Input)
214
215For information about available fields see [`mod@ccmr1_input`] module*/
216#[doc(alias = "CCMR1_Input")]
217pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
218///capture/compare mode register 1 (input mode)
219pub mod ccmr1_input;
220/**CCMR2_Output (rw) register accessor: capture/compare mode register 2 (output mode)
221
222You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
223
224See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:CCMR2_Output)
225
226For information about available fields see [`mod@ccmr2_output`] module*/
227#[doc(alias = "CCMR2_Output")]
228pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUTrs>;
229///capture/compare mode register 2 (output mode)
230pub mod ccmr2_output;
231/**CCMR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)
232
233You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
234
235See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:CCMR2_Input)
236
237For information about available fields see [`mod@ccmr2_input`] module*/
238#[doc(alias = "CCMR2_Input")]
239pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUTrs>;
240///capture/compare mode register 2 (input mode)
241pub mod ccmr2_input;
242/**CCER (rw) register accessor: capture/compare enable register
243
244You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
245
246See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:CCER)
247
248For information about available fields see [`mod@ccer`] module*/
249pub type CCER = crate::Reg<ccer::CCERrs>;
250///capture/compare enable register
251pub mod ccer;
252/**CNT (rw) register accessor: counter
253
254You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
255
256See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:CNT)
257
258For information about available fields see [`mod@cnt`] module*/
259pub type CNT = crate::Reg<cnt::CNTrs>;
260///counter
261pub mod cnt;
262/**PSC (rw) register accessor: prescaler
263
264You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
265
266See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:PSC)
267
268For information about available fields see [`mod@psc`] module*/
269pub type PSC = crate::Reg<psc::PSCrs>;
270///prescaler
271pub mod psc;
272/**ARR (rw) register accessor: auto-reload register
273
274You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
275
276See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:ARR)
277
278For information about available fields see [`mod@arr`] module*/
279pub type ARR = crate::Reg<arr::ARRrs>;
280///auto-reload register
281pub mod arr;
282/**CCR (rw) register accessor: capture/compare register
283
284You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
285
286See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:CCR[1])
287
288For information about available fields see [`mod@ccr`] module*/
289pub type CCR = crate::Reg<ccr::CCRrs>;
290///capture/compare register
291pub mod ccr;
292/**DCR (rw) register accessor: DMA control register
293
294You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
295
296See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:DCR)
297
298For information about available fields see [`mod@dcr`] module*/
299pub type DCR = crate::Reg<dcr::DCRrs>;
300///DMA control register
301pub mod dcr;
302/**DMAR (rw) register accessor: DMA address for full transfer
303
304You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
305
306See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM3:DMAR)
307
308For information about available fields see [`mod@dmar`] module*/
309pub type DMAR = crate::Reg<dmar::DMARrs>;
310///DMA address for full transfer
311pub mod dmar;
stm32f7_staging/stm32f779/tim3.rs

stm32f7_staging/stm32f779/
tim3.rs
