stm32f7_staging/stm32f779/tim2/
smcr.rs

1///Register `SMCR` reader
2pub type R = crate::R<SMCRrs>;
3///Register `SMCR` writer
4pub type W = crate::W<SMCRrs>;
5/**Slave mode selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum SMS {
12    ///0: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
13    Disabled = 0,
14    ///1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
15    EncoderMode1 = 1,
16    ///2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
17    EncoderMode2 = 2,
18    ///3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
19    EncoderMode3 = 3,
20    ///4: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
21    ResetMode = 4,
22    ///5: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
23    GatedMode = 5,
24    ///6: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
25    TriggerMode = 6,
26    ///7: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
27    ExtClockMode = 7,
28}
29impl From<SMS> for u8 {
30    #[inline(always)]
31    fn from(variant: SMS) -> Self {
32        variant as _
33    }
34}
35impl crate::FieldSpec for SMS {
36    type Ux = u8;
37}
38impl crate::IsEnum for SMS {}
39///Field `SMS` reader - Slave mode selection
40pub type SMS_R = crate::FieldReader<SMS>;
41impl SMS_R {
42    ///Get enumerated values variant
43    #[inline(always)]
44    pub const fn variant(&self) -> SMS {
45        match self.bits {
46            0 => SMS::Disabled,
47            1 => SMS::EncoderMode1,
48            2 => SMS::EncoderMode2,
49            3 => SMS::EncoderMode3,
50            4 => SMS::ResetMode,
51            5 => SMS::GatedMode,
52            6 => SMS::TriggerMode,
53            7 => SMS::ExtClockMode,
54            _ => unreachable!(),
55        }
56    }
57    ///Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
58    #[inline(always)]
59    pub fn is_disabled(&self) -> bool {
60        *self == SMS::Disabled
61    }
62    ///Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
63    #[inline(always)]
64    pub fn is_encoder_mode_1(&self) -> bool {
65        *self == SMS::EncoderMode1
66    }
67    ///Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
68    #[inline(always)]
69    pub fn is_encoder_mode_2(&self) -> bool {
70        *self == SMS::EncoderMode2
71    }
72    ///Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
73    #[inline(always)]
74    pub fn is_encoder_mode_3(&self) -> bool {
75        *self == SMS::EncoderMode3
76    }
77    ///Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
78    #[inline(always)]
79    pub fn is_reset_mode(&self) -> bool {
80        *self == SMS::ResetMode
81    }
82    ///Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
83    #[inline(always)]
84    pub fn is_gated_mode(&self) -> bool {
85        *self == SMS::GatedMode
86    }
87    ///Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
88    #[inline(always)]
89    pub fn is_trigger_mode(&self) -> bool {
90        *self == SMS::TriggerMode
91    }
92    ///External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
93    #[inline(always)]
94    pub fn is_ext_clock_mode(&self) -> bool {
95        *self == SMS::ExtClockMode
96    }
97}
98///Field `SMS` writer - Slave mode selection
99pub type SMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SMS, crate::Safe>;
100impl<'a, REG> SMS_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103    REG::Ux: From<u8>,
104{
105    ///Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
106    #[inline(always)]
107    pub fn disabled(self) -> &'a mut crate::W<REG> {
108        self.variant(SMS::Disabled)
109    }
110    ///Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
111    #[inline(always)]
112    pub fn encoder_mode_1(self) -> &'a mut crate::W<REG> {
113        self.variant(SMS::EncoderMode1)
114    }
115    ///Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
116    #[inline(always)]
117    pub fn encoder_mode_2(self) -> &'a mut crate::W<REG> {
118        self.variant(SMS::EncoderMode2)
119    }
120    ///Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
121    #[inline(always)]
122    pub fn encoder_mode_3(self) -> &'a mut crate::W<REG> {
123        self.variant(SMS::EncoderMode3)
124    }
125    ///Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
126    #[inline(always)]
127    pub fn reset_mode(self) -> &'a mut crate::W<REG> {
128        self.variant(SMS::ResetMode)
129    }
130    ///Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
131    #[inline(always)]
132    pub fn gated_mode(self) -> &'a mut crate::W<REG> {
133        self.variant(SMS::GatedMode)
134    }
135    ///Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
136    #[inline(always)]
137    pub fn trigger_mode(self) -> &'a mut crate::W<REG> {
138        self.variant(SMS::TriggerMode)
139    }
140    ///External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
141    #[inline(always)]
142    pub fn ext_clock_mode(self) -> &'a mut crate::W<REG> {
143        self.variant(SMS::ExtClockMode)
144    }
145}
146/**Trigger selection
147
148Value on reset: 0*/
149#[cfg_attr(feature = "defmt", derive(defmt::Format))]
150#[derive(Clone, Copy, Debug, PartialEq, Eq)]
151#[repr(u8)]
152pub enum TS {
153    ///0: Internal Trigger 0 (ITR0)
154    Itr0 = 0,
155    ///1: Internal Trigger 1 (ITR1)
156    Itr1 = 1,
157    ///2: Internal Trigger 2 (ITR2)
158    Itr2 = 2,
159    ///4: TI1 Edge Detector (TI1F_ED)
160    Ti1fEd = 4,
161    ///5: Filtered Timer Input 1 (TI1FP1)
162    Ti1fp1 = 5,
163    ///6: Filtered Timer Input 2 (TI2FP2)
164    Ti2fp2 = 6,
165    ///7: External Trigger input (ETRF)
166    Etrf = 7,
167}
168impl From<TS> for u8 {
169    #[inline(always)]
170    fn from(variant: TS) -> Self {
171        variant as _
172    }
173}
174impl crate::FieldSpec for TS {
175    type Ux = u8;
176}
177impl crate::IsEnum for TS {}
178///Field `TS` reader - Trigger selection
179pub type TS_R = crate::FieldReader<TS>;
180impl TS_R {
181    ///Get enumerated values variant
182    #[inline(always)]
183    pub const fn variant(&self) -> Option<TS> {
184        match self.bits {
185            0 => Some(TS::Itr0),
186            1 => Some(TS::Itr1),
187            2 => Some(TS::Itr2),
188            4 => Some(TS::Ti1fEd),
189            5 => Some(TS::Ti1fp1),
190            6 => Some(TS::Ti2fp2),
191            7 => Some(TS::Etrf),
192            _ => None,
193        }
194    }
195    ///Internal Trigger 0 (ITR0)
196    #[inline(always)]
197    pub fn is_itr0(&self) -> bool {
198        *self == TS::Itr0
199    }
200    ///Internal Trigger 1 (ITR1)
201    #[inline(always)]
202    pub fn is_itr1(&self) -> bool {
203        *self == TS::Itr1
204    }
205    ///Internal Trigger 2 (ITR2)
206    #[inline(always)]
207    pub fn is_itr2(&self) -> bool {
208        *self == TS::Itr2
209    }
210    ///TI1 Edge Detector (TI1F_ED)
211    #[inline(always)]
212    pub fn is_ti1f_ed(&self) -> bool {
213        *self == TS::Ti1fEd
214    }
215    ///Filtered Timer Input 1 (TI1FP1)
216    #[inline(always)]
217    pub fn is_ti1fp1(&self) -> bool {
218        *self == TS::Ti1fp1
219    }
220    ///Filtered Timer Input 2 (TI2FP2)
221    #[inline(always)]
222    pub fn is_ti2fp2(&self) -> bool {
223        *self == TS::Ti2fp2
224    }
225    ///External Trigger input (ETRF)
226    #[inline(always)]
227    pub fn is_etrf(&self) -> bool {
228        *self == TS::Etrf
229    }
230}
231///Field `TS` writer - Trigger selection
232pub type TS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, TS>;
233impl<'a, REG> TS_W<'a, REG>
234where
235    REG: crate::Writable + crate::RegisterSpec,
236    REG::Ux: From<u8>,
237{
238    ///Internal Trigger 0 (ITR0)
239    #[inline(always)]
240    pub fn itr0(self) -> &'a mut crate::W<REG> {
241        self.variant(TS::Itr0)
242    }
243    ///Internal Trigger 1 (ITR1)
244    #[inline(always)]
245    pub fn itr1(self) -> &'a mut crate::W<REG> {
246        self.variant(TS::Itr1)
247    }
248    ///Internal Trigger 2 (ITR2)
249    #[inline(always)]
250    pub fn itr2(self) -> &'a mut crate::W<REG> {
251        self.variant(TS::Itr2)
252    }
253    ///TI1 Edge Detector (TI1F_ED)
254    #[inline(always)]
255    pub fn ti1f_ed(self) -> &'a mut crate::W<REG> {
256        self.variant(TS::Ti1fEd)
257    }
258    ///Filtered Timer Input 1 (TI1FP1)
259    #[inline(always)]
260    pub fn ti1fp1(self) -> &'a mut crate::W<REG> {
261        self.variant(TS::Ti1fp1)
262    }
263    ///Filtered Timer Input 2 (TI2FP2)
264    #[inline(always)]
265    pub fn ti2fp2(self) -> &'a mut crate::W<REG> {
266        self.variant(TS::Ti2fp2)
267    }
268    ///External Trigger input (ETRF)
269    #[inline(always)]
270    pub fn etrf(self) -> &'a mut crate::W<REG> {
271        self.variant(TS::Etrf)
272    }
273}
274/**Master/Slave mode
275
276Value on reset: 0*/
277#[cfg_attr(feature = "defmt", derive(defmt::Format))]
278#[derive(Clone, Copy, Debug, PartialEq, Eq)]
279pub enum MSM {
280    ///0: No action
281    NoSync = 0,
282    ///1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
283    Sync = 1,
284}
285impl From<MSM> for bool {
286    #[inline(always)]
287    fn from(variant: MSM) -> Self {
288        variant as u8 != 0
289    }
290}
291///Field `MSM` reader - Master/Slave mode
292pub type MSM_R = crate::BitReader<MSM>;
293impl MSM_R {
294    ///Get enumerated values variant
295    #[inline(always)]
296    pub const fn variant(&self) -> MSM {
297        match self.bits {
298            false => MSM::NoSync,
299            true => MSM::Sync,
300        }
301    }
302    ///No action
303    #[inline(always)]
304    pub fn is_no_sync(&self) -> bool {
305        *self == MSM::NoSync
306    }
307    ///The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
308    #[inline(always)]
309    pub fn is_sync(&self) -> bool {
310        *self == MSM::Sync
311    }
312}
313///Field `MSM` writer - Master/Slave mode
314pub type MSM_W<'a, REG> = crate::BitWriter<'a, REG, MSM>;
315impl<'a, REG> MSM_W<'a, REG>
316where
317    REG: crate::Writable + crate::RegisterSpec,
318{
319    ///No action
320    #[inline(always)]
321    pub fn no_sync(self) -> &'a mut crate::W<REG> {
322        self.variant(MSM::NoSync)
323    }
324    ///The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
325    #[inline(always)]
326    pub fn sync(self) -> &'a mut crate::W<REG> {
327        self.variant(MSM::Sync)
328    }
329}
330/**External trigger filter
331
332Value on reset: 0*/
333#[cfg_attr(feature = "defmt", derive(defmt::Format))]
334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
335#[repr(u8)]
336pub enum ETF {
337    ///0: No filter, sampling is done at fDTS
338    NoFilter = 0,
339    ///1: fSAMPLING=fCK_INT, N=2
340    FckIntN2 = 1,
341    ///2: fSAMPLING=fCK_INT, N=4
342    FckIntN4 = 2,
343    ///3: fSAMPLING=fCK_INT, N=8
344    FckIntN8 = 3,
345    ///4: fSAMPLING=fDTS/2, N=6
346    FdtsDiv2N6 = 4,
347    ///5: fSAMPLING=fDTS/2, N=8
348    FdtsDiv2N8 = 5,
349    ///6: fSAMPLING=fDTS/4, N=6
350    FdtsDiv4N6 = 6,
351    ///7: fSAMPLING=fDTS/4, N=8
352    FdtsDiv4N8 = 7,
353    ///8: fSAMPLING=fDTS/8, N=6
354    FdtsDiv8N6 = 8,
355    ///9: fSAMPLING=fDTS/8, N=8
356    FdtsDiv8N8 = 9,
357    ///10: fSAMPLING=fDTS/16, N=5
358    FdtsDiv16N5 = 10,
359    ///11: fSAMPLING=fDTS/16, N=6
360    FdtsDiv16N6 = 11,
361    ///12: fSAMPLING=fDTS/16, N=8
362    FdtsDiv16N8 = 12,
363    ///13: fSAMPLING=fDTS/32, N=5
364    FdtsDiv32N5 = 13,
365    ///14: fSAMPLING=fDTS/32, N=6
366    FdtsDiv32N6 = 14,
367    ///15: fSAMPLING=fDTS/32, N=8
368    FdtsDiv32N8 = 15,
369}
370impl From<ETF> for u8 {
371    #[inline(always)]
372    fn from(variant: ETF) -> Self {
373        variant as _
374    }
375}
376impl crate::FieldSpec for ETF {
377    type Ux = u8;
378}
379impl crate::IsEnum for ETF {}
380///Field `ETF` reader - External trigger filter
381pub type ETF_R = crate::FieldReader<ETF>;
382impl ETF_R {
383    ///Get enumerated values variant
384    #[inline(always)]
385    pub const fn variant(&self) -> ETF {
386        match self.bits {
387            0 => ETF::NoFilter,
388            1 => ETF::FckIntN2,
389            2 => ETF::FckIntN4,
390            3 => ETF::FckIntN8,
391            4 => ETF::FdtsDiv2N6,
392            5 => ETF::FdtsDiv2N8,
393            6 => ETF::FdtsDiv4N6,
394            7 => ETF::FdtsDiv4N8,
395            8 => ETF::FdtsDiv8N6,
396            9 => ETF::FdtsDiv8N8,
397            10 => ETF::FdtsDiv16N5,
398            11 => ETF::FdtsDiv16N6,
399            12 => ETF::FdtsDiv16N8,
400            13 => ETF::FdtsDiv32N5,
401            14 => ETF::FdtsDiv32N6,
402            15 => ETF::FdtsDiv32N8,
403            _ => unreachable!(),
404        }
405    }
406    ///No filter, sampling is done at fDTS
407    #[inline(always)]
408    pub fn is_no_filter(&self) -> bool {
409        *self == ETF::NoFilter
410    }
411    ///fSAMPLING=fCK_INT, N=2
412    #[inline(always)]
413    pub fn is_fck_int_n2(&self) -> bool {
414        *self == ETF::FckIntN2
415    }
416    ///fSAMPLING=fCK_INT, N=4
417    #[inline(always)]
418    pub fn is_fck_int_n4(&self) -> bool {
419        *self == ETF::FckIntN4
420    }
421    ///fSAMPLING=fCK_INT, N=8
422    #[inline(always)]
423    pub fn is_fck_int_n8(&self) -> bool {
424        *self == ETF::FckIntN8
425    }
426    ///fSAMPLING=fDTS/2, N=6
427    #[inline(always)]
428    pub fn is_fdts_div2_n6(&self) -> bool {
429        *self == ETF::FdtsDiv2N6
430    }
431    ///fSAMPLING=fDTS/2, N=8
432    #[inline(always)]
433    pub fn is_fdts_div2_n8(&self) -> bool {
434        *self == ETF::FdtsDiv2N8
435    }
436    ///fSAMPLING=fDTS/4, N=6
437    #[inline(always)]
438    pub fn is_fdts_div4_n6(&self) -> bool {
439        *self == ETF::FdtsDiv4N6
440    }
441    ///fSAMPLING=fDTS/4, N=8
442    #[inline(always)]
443    pub fn is_fdts_div4_n8(&self) -> bool {
444        *self == ETF::FdtsDiv4N8
445    }
446    ///fSAMPLING=fDTS/8, N=6
447    #[inline(always)]
448    pub fn is_fdts_div8_n6(&self) -> bool {
449        *self == ETF::FdtsDiv8N6
450    }
451    ///fSAMPLING=fDTS/8, N=8
452    #[inline(always)]
453    pub fn is_fdts_div8_n8(&self) -> bool {
454        *self == ETF::FdtsDiv8N8
455    }
456    ///fSAMPLING=fDTS/16, N=5
457    #[inline(always)]
458    pub fn is_fdts_div16_n5(&self) -> bool {
459        *self == ETF::FdtsDiv16N5
460    }
461    ///fSAMPLING=fDTS/16, N=6
462    #[inline(always)]
463    pub fn is_fdts_div16_n6(&self) -> bool {
464        *self == ETF::FdtsDiv16N6
465    }
466    ///fSAMPLING=fDTS/16, N=8
467    #[inline(always)]
468    pub fn is_fdts_div16_n8(&self) -> bool {
469        *self == ETF::FdtsDiv16N8
470    }
471    ///fSAMPLING=fDTS/32, N=5
472    #[inline(always)]
473    pub fn is_fdts_div32_n5(&self) -> bool {
474        *self == ETF::FdtsDiv32N5
475    }
476    ///fSAMPLING=fDTS/32, N=6
477    #[inline(always)]
478    pub fn is_fdts_div32_n6(&self) -> bool {
479        *self == ETF::FdtsDiv32N6
480    }
481    ///fSAMPLING=fDTS/32, N=8
482    #[inline(always)]
483    pub fn is_fdts_div32_n8(&self) -> bool {
484        *self == ETF::FdtsDiv32N8
485    }
486}
487///Field `ETF` writer - External trigger filter
488pub type ETF_W<'a, REG> = crate::FieldWriter<'a, REG, 4, ETF, crate::Safe>;
489impl<'a, REG> ETF_W<'a, REG>
490where
491    REG: crate::Writable + crate::RegisterSpec,
492    REG::Ux: From<u8>,
493{
494    ///No filter, sampling is done at fDTS
495    #[inline(always)]
496    pub fn no_filter(self) -> &'a mut crate::W<REG> {
497        self.variant(ETF::NoFilter)
498    }
499    ///fSAMPLING=fCK_INT, N=2
500    #[inline(always)]
501    pub fn fck_int_n2(self) -> &'a mut crate::W<REG> {
502        self.variant(ETF::FckIntN2)
503    }
504    ///fSAMPLING=fCK_INT, N=4
505    #[inline(always)]
506    pub fn fck_int_n4(self) -> &'a mut crate::W<REG> {
507        self.variant(ETF::FckIntN4)
508    }
509    ///fSAMPLING=fCK_INT, N=8
510    #[inline(always)]
511    pub fn fck_int_n8(self) -> &'a mut crate::W<REG> {
512        self.variant(ETF::FckIntN8)
513    }
514    ///fSAMPLING=fDTS/2, N=6
515    #[inline(always)]
516    pub fn fdts_div2_n6(self) -> &'a mut crate::W<REG> {
517        self.variant(ETF::FdtsDiv2N6)
518    }
519    ///fSAMPLING=fDTS/2, N=8
520    #[inline(always)]
521    pub fn fdts_div2_n8(self) -> &'a mut crate::W<REG> {
522        self.variant(ETF::FdtsDiv2N8)
523    }
524    ///fSAMPLING=fDTS/4, N=6
525    #[inline(always)]
526    pub fn fdts_div4_n6(self) -> &'a mut crate::W<REG> {
527        self.variant(ETF::FdtsDiv4N6)
528    }
529    ///fSAMPLING=fDTS/4, N=8
530    #[inline(always)]
531    pub fn fdts_div4_n8(self) -> &'a mut crate::W<REG> {
532        self.variant(ETF::FdtsDiv4N8)
533    }
534    ///fSAMPLING=fDTS/8, N=6
535    #[inline(always)]
536    pub fn fdts_div8_n6(self) -> &'a mut crate::W<REG> {
537        self.variant(ETF::FdtsDiv8N6)
538    }
539    ///fSAMPLING=fDTS/8, N=8
540    #[inline(always)]
541    pub fn fdts_div8_n8(self) -> &'a mut crate::W<REG> {
542        self.variant(ETF::FdtsDiv8N8)
543    }
544    ///fSAMPLING=fDTS/16, N=5
545    #[inline(always)]
546    pub fn fdts_div16_n5(self) -> &'a mut crate::W<REG> {
547        self.variant(ETF::FdtsDiv16N5)
548    }
549    ///fSAMPLING=fDTS/16, N=6
550    #[inline(always)]
551    pub fn fdts_div16_n6(self) -> &'a mut crate::W<REG> {
552        self.variant(ETF::FdtsDiv16N6)
553    }
554    ///fSAMPLING=fDTS/16, N=8
555    #[inline(always)]
556    pub fn fdts_div16_n8(self) -> &'a mut crate::W<REG> {
557        self.variant(ETF::FdtsDiv16N8)
558    }
559    ///fSAMPLING=fDTS/32, N=5
560    #[inline(always)]
561    pub fn fdts_div32_n5(self) -> &'a mut crate::W<REG> {
562        self.variant(ETF::FdtsDiv32N5)
563    }
564    ///fSAMPLING=fDTS/32, N=6
565    #[inline(always)]
566    pub fn fdts_div32_n6(self) -> &'a mut crate::W<REG> {
567        self.variant(ETF::FdtsDiv32N6)
568    }
569    ///fSAMPLING=fDTS/32, N=8
570    #[inline(always)]
571    pub fn fdts_div32_n8(self) -> &'a mut crate::W<REG> {
572        self.variant(ETF::FdtsDiv32N8)
573    }
574}
575/**External trigger prescaler
576
577Value on reset: 0*/
578#[cfg_attr(feature = "defmt", derive(defmt::Format))]
579#[derive(Clone, Copy, Debug, PartialEq, Eq)]
580#[repr(u8)]
581pub enum ETPS {
582    ///0: Prescaler OFF
583    Div1 = 0,
584    ///1: ETRP frequency divided by 2
585    Div2 = 1,
586    ///2: ETRP frequency divided by 4
587    Div4 = 2,
588    ///3: ETRP frequency divided by 8
589    Div8 = 3,
590}
591impl From<ETPS> for u8 {
592    #[inline(always)]
593    fn from(variant: ETPS) -> Self {
594        variant as _
595    }
596}
597impl crate::FieldSpec for ETPS {
598    type Ux = u8;
599}
600impl crate::IsEnum for ETPS {}
601///Field `ETPS` reader - External trigger prescaler
602pub type ETPS_R = crate::FieldReader<ETPS>;
603impl ETPS_R {
604    ///Get enumerated values variant
605    #[inline(always)]
606    pub const fn variant(&self) -> ETPS {
607        match self.bits {
608            0 => ETPS::Div1,
609            1 => ETPS::Div2,
610            2 => ETPS::Div4,
611            3 => ETPS::Div8,
612            _ => unreachable!(),
613        }
614    }
615    ///Prescaler OFF
616    #[inline(always)]
617    pub fn is_div1(&self) -> bool {
618        *self == ETPS::Div1
619    }
620    ///ETRP frequency divided by 2
621    #[inline(always)]
622    pub fn is_div2(&self) -> bool {
623        *self == ETPS::Div2
624    }
625    ///ETRP frequency divided by 4
626    #[inline(always)]
627    pub fn is_div4(&self) -> bool {
628        *self == ETPS::Div4
629    }
630    ///ETRP frequency divided by 8
631    #[inline(always)]
632    pub fn is_div8(&self) -> bool {
633        *self == ETPS::Div8
634    }
635}
636///Field `ETPS` writer - External trigger prescaler
637pub type ETPS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ETPS, crate::Safe>;
638impl<'a, REG> ETPS_W<'a, REG>
639where
640    REG: crate::Writable + crate::RegisterSpec,
641    REG::Ux: From<u8>,
642{
643    ///Prescaler OFF
644    #[inline(always)]
645    pub fn div1(self) -> &'a mut crate::W<REG> {
646        self.variant(ETPS::Div1)
647    }
648    ///ETRP frequency divided by 2
649    #[inline(always)]
650    pub fn div2(self) -> &'a mut crate::W<REG> {
651        self.variant(ETPS::Div2)
652    }
653    ///ETRP frequency divided by 4
654    #[inline(always)]
655    pub fn div4(self) -> &'a mut crate::W<REG> {
656        self.variant(ETPS::Div4)
657    }
658    ///ETRP frequency divided by 8
659    #[inline(always)]
660    pub fn div8(self) -> &'a mut crate::W<REG> {
661        self.variant(ETPS::Div8)
662    }
663}
664/**External clock enable
665
666Value on reset: 0*/
667#[cfg_attr(feature = "defmt", derive(defmt::Format))]
668#[derive(Clone, Copy, Debug, PartialEq, Eq)]
669pub enum ECE {
670    ///0: External clock mode 2 disabled
671    Disabled = 0,
672    ///1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
673    Enabled = 1,
674}
675impl From<ECE> for bool {
676    #[inline(always)]
677    fn from(variant: ECE) -> Self {
678        variant as u8 != 0
679    }
680}
681///Field `ECE` reader - External clock enable
682pub type ECE_R = crate::BitReader<ECE>;
683impl ECE_R {
684    ///Get enumerated values variant
685    #[inline(always)]
686    pub const fn variant(&self) -> ECE {
687        match self.bits {
688            false => ECE::Disabled,
689            true => ECE::Enabled,
690        }
691    }
692    ///External clock mode 2 disabled
693    #[inline(always)]
694    pub fn is_disabled(&self) -> bool {
695        *self == ECE::Disabled
696    }
697    ///External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
698    #[inline(always)]
699    pub fn is_enabled(&self) -> bool {
700        *self == ECE::Enabled
701    }
702}
703///Field `ECE` writer - External clock enable
704pub type ECE_W<'a, REG> = crate::BitWriter<'a, REG, ECE>;
705impl<'a, REG> ECE_W<'a, REG>
706where
707    REG: crate::Writable + crate::RegisterSpec,
708{
709    ///External clock mode 2 disabled
710    #[inline(always)]
711    pub fn disabled(self) -> &'a mut crate::W<REG> {
712        self.variant(ECE::Disabled)
713    }
714    ///External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
715    #[inline(always)]
716    pub fn enabled(self) -> &'a mut crate::W<REG> {
717        self.variant(ECE::Enabled)
718    }
719}
720/**External trigger polarity
721
722Value on reset: 0*/
723#[cfg_attr(feature = "defmt", derive(defmt::Format))]
724#[derive(Clone, Copy, Debug, PartialEq, Eq)]
725pub enum ETP {
726    ///0: ETR is noninverted, active at high level or rising edge
727    NotInverted = 0,
728    ///1: ETR is inverted, active at low level or falling edge
729    Inverted = 1,
730}
731impl From<ETP> for bool {
732    #[inline(always)]
733    fn from(variant: ETP) -> Self {
734        variant as u8 != 0
735    }
736}
737///Field `ETP` reader - External trigger polarity
738pub type ETP_R = crate::BitReader<ETP>;
739impl ETP_R {
740    ///Get enumerated values variant
741    #[inline(always)]
742    pub const fn variant(&self) -> ETP {
743        match self.bits {
744            false => ETP::NotInverted,
745            true => ETP::Inverted,
746        }
747    }
748    ///ETR is noninverted, active at high level or rising edge
749    #[inline(always)]
750    pub fn is_not_inverted(&self) -> bool {
751        *self == ETP::NotInverted
752    }
753    ///ETR is inverted, active at low level or falling edge
754    #[inline(always)]
755    pub fn is_inverted(&self) -> bool {
756        *self == ETP::Inverted
757    }
758}
759///Field `ETP` writer - External trigger polarity
760pub type ETP_W<'a, REG> = crate::BitWriter<'a, REG, ETP>;
761impl<'a, REG> ETP_W<'a, REG>
762where
763    REG: crate::Writable + crate::RegisterSpec,
764{
765    ///ETR is noninverted, active at high level or rising edge
766    #[inline(always)]
767    pub fn not_inverted(self) -> &'a mut crate::W<REG> {
768        self.variant(ETP::NotInverted)
769    }
770    ///ETR is inverted, active at low level or falling edge
771    #[inline(always)]
772    pub fn inverted(self) -> &'a mut crate::W<REG> {
773        self.variant(ETP::Inverted)
774    }
775}
776///Field `SMS_3` reader - Slave mode selection - bit 3
777pub type SMS_3_R = crate::BitReader;
778///Field `SMS_3` writer - Slave mode selection - bit 3
779pub type SMS_3_W<'a, REG> = crate::BitWriter<'a, REG>;
780impl R {
781    ///Bits 0:2 - Slave mode selection
782    #[inline(always)]
783    pub fn sms(&self) -> SMS_R {
784        SMS_R::new((self.bits & 7) as u8)
785    }
786    ///Bits 4:6 - Trigger selection
787    #[inline(always)]
788    pub fn ts(&self) -> TS_R {
789        TS_R::new(((self.bits >> 4) & 7) as u8)
790    }
791    ///Bit 7 - Master/Slave mode
792    #[inline(always)]
793    pub fn msm(&self) -> MSM_R {
794        MSM_R::new(((self.bits >> 7) & 1) != 0)
795    }
796    ///Bits 8:11 - External trigger filter
797    #[inline(always)]
798    pub fn etf(&self) -> ETF_R {
799        ETF_R::new(((self.bits >> 8) & 0x0f) as u8)
800    }
801    ///Bits 12:13 - External trigger prescaler
802    #[inline(always)]
803    pub fn etps(&self) -> ETPS_R {
804        ETPS_R::new(((self.bits >> 12) & 3) as u8)
805    }
806    ///Bit 14 - External clock enable
807    #[inline(always)]
808    pub fn ece(&self) -> ECE_R {
809        ECE_R::new(((self.bits >> 14) & 1) != 0)
810    }
811    ///Bit 15 - External trigger polarity
812    #[inline(always)]
813    pub fn etp(&self) -> ETP_R {
814        ETP_R::new(((self.bits >> 15) & 1) != 0)
815    }
816    ///Bit 16 - Slave mode selection - bit 3
817    #[inline(always)]
818    pub fn sms_3(&self) -> SMS_3_R {
819        SMS_3_R::new(((self.bits >> 16) & 1) != 0)
820    }
821}
822impl core::fmt::Debug for R {
823    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
824        f.debug_struct("SMCR")
825            .field("etp", &self.etp())
826            .field("ece", &self.ece())
827            .field("etps", &self.etps())
828            .field("etf", &self.etf())
829            .field("msm", &self.msm())
830            .field("ts", &self.ts())
831            .field("sms", &self.sms())
832            .field("sms_3", &self.sms_3())
833            .finish()
834    }
835}
836impl W {
837    ///Bits 0:2 - Slave mode selection
838    #[inline(always)]
839    pub fn sms(&mut self) -> SMS_W<SMCRrs> {
840        SMS_W::new(self, 0)
841    }
842    ///Bits 4:6 - Trigger selection
843    #[inline(always)]
844    pub fn ts(&mut self) -> TS_W<SMCRrs> {
845        TS_W::new(self, 4)
846    }
847    ///Bit 7 - Master/Slave mode
848    #[inline(always)]
849    pub fn msm(&mut self) -> MSM_W<SMCRrs> {
850        MSM_W::new(self, 7)
851    }
852    ///Bits 8:11 - External trigger filter
853    #[inline(always)]
854    pub fn etf(&mut self) -> ETF_W<SMCRrs> {
855        ETF_W::new(self, 8)
856    }
857    ///Bits 12:13 - External trigger prescaler
858    #[inline(always)]
859    pub fn etps(&mut self) -> ETPS_W<SMCRrs> {
860        ETPS_W::new(self, 12)
861    }
862    ///Bit 14 - External clock enable
863    #[inline(always)]
864    pub fn ece(&mut self) -> ECE_W<SMCRrs> {
865        ECE_W::new(self, 14)
866    }
867    ///Bit 15 - External trigger polarity
868    #[inline(always)]
869    pub fn etp(&mut self) -> ETP_W<SMCRrs> {
870        ETP_W::new(self, 15)
871    }
872    ///Bit 16 - Slave mode selection - bit 3
873    #[inline(always)]
874    pub fn sms_3(&mut self) -> SMS_3_W<SMCRrs> {
875        SMS_3_W::new(self, 16)
876    }
877}
878/**slave mode control register
879
880You can [`read`](crate::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
881
882See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM2:SMCR)*/
883pub struct SMCRrs;
884impl crate::RegisterSpec for SMCRrs {
885    type Ux = u32;
886}
887///`read()` method returns [`smcr::R`](R) reader structure
888impl crate::Readable for SMCRrs {}
889///`write(|w| ..)` method takes [`smcr::W`](W) writer structure
890impl crate::Writable for SMCRrs {
891    type Safety = crate::Unsafe;
892}
893///`reset()` method sets SMCR to value 0
894impl crate::Resettable for SMCRrs {}
stm32f7_staging/stm32f779/tim2/smcr.rs

stm32f7_staging/stm32f779/tim2/
smcr.rs
