stm32f7_staging/stm32f779/tim1/
ccer.rs

1///Register `CCER` reader
2pub type R = crate::R<CCERrs>;
3///Register `CCER` writer
4pub type W = crate::W<CCERrs>;
5/**Capture/Compare %s output enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CC1E {
11    ///0: Capture disabled
12    Disabled = 0,
13    ///1: Capture enabled
14    Enabled = 1,
15}
16impl From<CC1E> for bool {
17    #[inline(always)]
18    fn from(variant: CC1E) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCE(1-6)` reader - Capture/Compare %s output enable
23pub type CCE_R = crate::BitReader<CC1E>;
24impl CCE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CC1E {
28        match self.bits {
29            false => CC1E::Disabled,
30            true => CC1E::Enabled,
31        }
32    }
33    ///Capture disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CC1E::Disabled
37    }
38    ///Capture enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CC1E::Enabled
42    }
43}
44///Field `CCE(1-6)` writer - Capture/Compare %s output enable
45pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CC1E>;
46impl<'a, REG> CCE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Capture disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CC1E::Disabled)
54    }
55    ///Capture enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CC1E::Enabled)
59    }
60}
61/**Capture/Compare %s output Polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1P {
67    ///0: Noninverted/rising edge
68    RisingEdge = 0,
69    ///1: Inverted/falling edge
70    FallingEdge = 1,
71}
72impl From<CC1P> for bool {
73    #[inline(always)]
74    fn from(variant: CC1P) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCP(1-6)` reader - Capture/Compare %s output Polarity
79pub type CCP_R = crate::BitReader<CC1P>;
80impl CCP_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1P {
84        match self.bits {
85            false => CC1P::RisingEdge,
86            true => CC1P::FallingEdge,
87        }
88    }
89    ///Noninverted/rising edge
90    #[inline(always)]
91    pub fn is_rising_edge(&self) -> bool {
92        *self == CC1P::RisingEdge
93    }
94    ///Inverted/falling edge
95    #[inline(always)]
96    pub fn is_falling_edge(&self) -> bool {
97        *self == CC1P::FallingEdge
98    }
99}
100///Field `CCP(1-6)` writer - Capture/Compare %s output Polarity
101pub type CCP_W<'a, REG> = crate::BitWriter<'a, REG, CC1P>;
102impl<'a, REG> CCP_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Noninverted/rising edge
107    #[inline(always)]
108    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1P::RisingEdge)
110    }
111    ///Inverted/falling edge
112    #[inline(always)]
113    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1P::FallingEdge)
115    }
116}
117/**Capture/Compare %s complementary output enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum CC1NE {
123    ///0: Complementary output disabled
124    Disabled = 0,
125    ///1: Complementary output enabled
126    Enabled = 1,
127}
128impl From<CC1NE> for bool {
129    #[inline(always)]
130    fn from(variant: CC1NE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `CCNE(1-3)` reader - Capture/Compare %s complementary output enable
135pub type CCNE_R = crate::BitReader<CC1NE>;
136impl CCNE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> CC1NE {
140        match self.bits {
141            false => CC1NE::Disabled,
142            true => CC1NE::Enabled,
143        }
144    }
145    ///Complementary output disabled
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == CC1NE::Disabled
149    }
150    ///Complementary output enabled
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == CC1NE::Enabled
154    }
155}
156///Field `CCNE(1-3)` writer - Capture/Compare %s complementary output enable
157pub type CCNE_W<'a, REG> = crate::BitWriter<'a, REG, CC1NE>;
158impl<'a, REG> CCNE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Complementary output disabled
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(CC1NE::Disabled)
166    }
167    ///Complementary output enabled
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(CC1NE::Enabled)
171    }
172}
173/**Capture/Compare %s output Polarity
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum CC1NP {
179    ///0: OCxN active high
180    ActiveHigh = 0,
181    ///1: OCxN active low
182    ActiveLow = 1,
183}
184impl From<CC1NP> for bool {
185    #[inline(always)]
186    fn from(variant: CC1NP) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `CCNP(1-4)` reader - Capture/Compare %s output Polarity
191pub type CCNP_R = crate::BitReader<CC1NP>;
192impl CCNP_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> CC1NP {
196        match self.bits {
197            false => CC1NP::ActiveHigh,
198            true => CC1NP::ActiveLow,
199        }
200    }
201    ///OCxN active high
202    #[inline(always)]
203    pub fn is_active_high(&self) -> bool {
204        *self == CC1NP::ActiveHigh
205    }
206    ///OCxN active low
207    #[inline(always)]
208    pub fn is_active_low(&self) -> bool {
209        *self == CC1NP::ActiveLow
210    }
211}
212///Field `CCNP(1-4)` writer - Capture/Compare %s output Polarity
213pub type CCNP_W<'a, REG> = crate::BitWriter<'a, REG, CC1NP>;
214impl<'a, REG> CCNP_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///OCxN active high
219    #[inline(always)]
220    pub fn active_high(self) -> &'a mut crate::W<REG> {
221        self.variant(CC1NP::ActiveHigh)
222    }
223    ///OCxN active low
224    #[inline(always)]
225    pub fn active_low(self) -> &'a mut crate::W<REG> {
226        self.variant(CC1NP::ActiveLow)
227    }
228}
229impl R {
230    ///Capture/Compare (1-6) output enable
231    ///
232    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
233    #[inline(always)]
234    pub fn cce(&self, n: u8) -> CCE_R {
235        #[allow(clippy::no_effect)]
236        [(); 6][n as usize];
237        CCE_R::new(((self.bits >> (n * 4)) & 1) != 0)
238    }
239    ///Iterator for array of:
240    ///Capture/Compare (1-6) output enable
241    #[inline(always)]
242    pub fn cce_iter(&self) -> impl Iterator<Item = CCE_R> + '_ {
243        (0..6).map(move |n| CCE_R::new(((self.bits >> (n * 4)) & 1) != 0))
244    }
245    ///Bit 0 - Capture/Compare 1 output enable
246    #[inline(always)]
247    pub fn cc1e(&self) -> CCE_R {
248        CCE_R::new((self.bits & 1) != 0)
249    }
250    ///Bit 4 - Capture/Compare 2 output enable
251    #[inline(always)]
252    pub fn cc2e(&self) -> CCE_R {
253        CCE_R::new(((self.bits >> 4) & 1) != 0)
254    }
255    ///Bit 8 - Capture/Compare 3 output enable
256    #[inline(always)]
257    pub fn cc3e(&self) -> CCE_R {
258        CCE_R::new(((self.bits >> 8) & 1) != 0)
259    }
260    ///Bit 12 - Capture/Compare 4 output enable
261    #[inline(always)]
262    pub fn cc4e(&self) -> CCE_R {
263        CCE_R::new(((self.bits >> 12) & 1) != 0)
264    }
265    ///Bit 16 - Capture/Compare 5 output enable
266    #[inline(always)]
267    pub fn cc5e(&self) -> CCE_R {
268        CCE_R::new(((self.bits >> 16) & 1) != 0)
269    }
270    ///Bit 20 - Capture/Compare 6 output enable
271    #[inline(always)]
272    pub fn cc6e(&self) -> CCE_R {
273        CCE_R::new(((self.bits >> 20) & 1) != 0)
274    }
275    ///Capture/Compare (1-6) output Polarity
276    ///
277    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
278    #[inline(always)]
279    pub fn ccp(&self, n: u8) -> CCP_R {
280        #[allow(clippy::no_effect)]
281        [(); 6][n as usize];
282        CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
283    }
284    ///Iterator for array of:
285    ///Capture/Compare (1-6) output Polarity
286    #[inline(always)]
287    pub fn ccp_iter(&self) -> impl Iterator<Item = CCP_R> + '_ {
288        (0..6).map(move |n| CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0))
289    }
290    ///Bit 1 - Capture/Compare 1 output Polarity
291    #[inline(always)]
292    pub fn cc1p(&self) -> CCP_R {
293        CCP_R::new(((self.bits >> 1) & 1) != 0)
294    }
295    ///Bit 5 - Capture/Compare 2 output Polarity
296    #[inline(always)]
297    pub fn cc2p(&self) -> CCP_R {
298        CCP_R::new(((self.bits >> 5) & 1) != 0)
299    }
300    ///Bit 9 - Capture/Compare 3 output Polarity
301    #[inline(always)]
302    pub fn cc3p(&self) -> CCP_R {
303        CCP_R::new(((self.bits >> 9) & 1) != 0)
304    }
305    ///Bit 13 - Capture/Compare 4 output Polarity
306    #[inline(always)]
307    pub fn cc4p(&self) -> CCP_R {
308        CCP_R::new(((self.bits >> 13) & 1) != 0)
309    }
310    ///Bit 17 - Capture/Compare 5 output Polarity
311    #[inline(always)]
312    pub fn cc5p(&self) -> CCP_R {
313        CCP_R::new(((self.bits >> 17) & 1) != 0)
314    }
315    ///Bit 21 - Capture/Compare 6 output Polarity
316    #[inline(always)]
317    pub fn cc6p(&self) -> CCP_R {
318        CCP_R::new(((self.bits >> 21) & 1) != 0)
319    }
320    ///Capture/Compare (1-3) complementary output enable
321    ///
322    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NE` field.</div>
323    #[inline(always)]
324    pub fn ccne(&self, n: u8) -> CCNE_R {
325        #[allow(clippy::no_effect)]
326        [(); 3][n as usize];
327        CCNE_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0)
328    }
329    ///Iterator for array of:
330    ///Capture/Compare (1-3) complementary output enable
331    #[inline(always)]
332    pub fn ccne_iter(&self) -> impl Iterator<Item = CCNE_R> + '_ {
333        (0..3).map(move |n| CCNE_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0))
334    }
335    ///Bit 2 - Capture/Compare 1 complementary output enable
336    #[inline(always)]
337    pub fn cc1ne(&self) -> CCNE_R {
338        CCNE_R::new(((self.bits >> 2) & 1) != 0)
339    }
340    ///Bit 6 - Capture/Compare 2 complementary output enable
341    #[inline(always)]
342    pub fn cc2ne(&self) -> CCNE_R {
343        CCNE_R::new(((self.bits >> 6) & 1) != 0)
344    }
345    ///Bit 10 - Capture/Compare 3 complementary output enable
346    #[inline(always)]
347    pub fn cc3ne(&self) -> CCNE_R {
348        CCNE_R::new(((self.bits >> 10) & 1) != 0)
349    }
350    ///Capture/Compare (1-4) output Polarity
351    ///
352    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
353    #[inline(always)]
354    pub fn ccnp(&self, n: u8) -> CCNP_R {
355        #[allow(clippy::no_effect)]
356        [(); 4][n as usize];
357        CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0)
358    }
359    ///Iterator for array of:
360    ///Capture/Compare (1-4) output Polarity
361    #[inline(always)]
362    pub fn ccnp_iter(&self) -> impl Iterator<Item = CCNP_R> + '_ {
363        (0..4).map(move |n| CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0))
364    }
365    ///Bit 3 - Capture/Compare 1 output Polarity
366    #[inline(always)]
367    pub fn cc1np(&self) -> CCNP_R {
368        CCNP_R::new(((self.bits >> 3) & 1) != 0)
369    }
370    ///Bit 7 - Capture/Compare 2 output Polarity
371    #[inline(always)]
372    pub fn cc2np(&self) -> CCNP_R {
373        CCNP_R::new(((self.bits >> 7) & 1) != 0)
374    }
375    ///Bit 11 - Capture/Compare 3 output Polarity
376    #[inline(always)]
377    pub fn cc3np(&self) -> CCNP_R {
378        CCNP_R::new(((self.bits >> 11) & 1) != 0)
379    }
380    ///Bit 15 - Capture/Compare 4 output Polarity
381    #[inline(always)]
382    pub fn cc4np(&self) -> CCNP_R {
383        CCNP_R::new(((self.bits >> 15) & 1) != 0)
384    }
385}
386impl core::fmt::Debug for R {
387    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
388        f.debug_struct("CCER")
389            .field("cc1p", &self.cc1p())
390            .field("cc2p", &self.cc2p())
391            .field("cc3p", &self.cc3p())
392            .field("cc4p", &self.cc4p())
393            .field("cc5p", &self.cc5p())
394            .field("cc6p", &self.cc6p())
395            .field("cc1e", &self.cc1e())
396            .field("cc2e", &self.cc2e())
397            .field("cc3e", &self.cc3e())
398            .field("cc4e", &self.cc4e())
399            .field("cc5e", &self.cc5e())
400            .field("cc6e", &self.cc6e())
401            .field("cc1np", &self.cc1np())
402            .field("cc2np", &self.cc2np())
403            .field("cc3np", &self.cc3np())
404            .field("cc4np", &self.cc4np())
405            .field("cc1ne", &self.cc1ne())
406            .field("cc2ne", &self.cc2ne())
407            .field("cc3ne", &self.cc3ne())
408            .finish()
409    }
410}
411impl W {
412    ///Capture/Compare (1-6) output enable
413    ///
414    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
415    #[inline(always)]
416    pub fn cce(&mut self, n: u8) -> CCE_W<CCERrs> {
417        #[allow(clippy::no_effect)]
418        [(); 6][n as usize];
419        CCE_W::new(self, n * 4)
420    }
421    ///Bit 0 - Capture/Compare 1 output enable
422    #[inline(always)]
423    pub fn cc1e(&mut self) -> CCE_W<CCERrs> {
424        CCE_W::new(self, 0)
425    }
426    ///Bit 4 - Capture/Compare 2 output enable
427    #[inline(always)]
428    pub fn cc2e(&mut self) -> CCE_W<CCERrs> {
429        CCE_W::new(self, 4)
430    }
431    ///Bit 8 - Capture/Compare 3 output enable
432    #[inline(always)]
433    pub fn cc3e(&mut self) -> CCE_W<CCERrs> {
434        CCE_W::new(self, 8)
435    }
436    ///Bit 12 - Capture/Compare 4 output enable
437    #[inline(always)]
438    pub fn cc4e(&mut self) -> CCE_W<CCERrs> {
439        CCE_W::new(self, 12)
440    }
441    ///Bit 16 - Capture/Compare 5 output enable
442    #[inline(always)]
443    pub fn cc5e(&mut self) -> CCE_W<CCERrs> {
444        CCE_W::new(self, 16)
445    }
446    ///Bit 20 - Capture/Compare 6 output enable
447    #[inline(always)]
448    pub fn cc6e(&mut self) -> CCE_W<CCERrs> {
449        CCE_W::new(self, 20)
450    }
451    ///Capture/Compare (1-6) output Polarity
452    ///
453    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
454    #[inline(always)]
455    pub fn ccp(&mut self, n: u8) -> CCP_W<CCERrs> {
456        #[allow(clippy::no_effect)]
457        [(); 6][n as usize];
458        CCP_W::new(self, n * 4 + 1)
459    }
460    ///Bit 1 - Capture/Compare 1 output Polarity
461    #[inline(always)]
462    pub fn cc1p(&mut self) -> CCP_W<CCERrs> {
463        CCP_W::new(self, 1)
464    }
465    ///Bit 5 - Capture/Compare 2 output Polarity
466    #[inline(always)]
467    pub fn cc2p(&mut self) -> CCP_W<CCERrs> {
468        CCP_W::new(self, 5)
469    }
470    ///Bit 9 - Capture/Compare 3 output Polarity
471    #[inline(always)]
472    pub fn cc3p(&mut self) -> CCP_W<CCERrs> {
473        CCP_W::new(self, 9)
474    }
475    ///Bit 13 - Capture/Compare 4 output Polarity
476    #[inline(always)]
477    pub fn cc4p(&mut self) -> CCP_W<CCERrs> {
478        CCP_W::new(self, 13)
479    }
480    ///Bit 17 - Capture/Compare 5 output Polarity
481    #[inline(always)]
482    pub fn cc5p(&mut self) -> CCP_W<CCERrs> {
483        CCP_W::new(self, 17)
484    }
485    ///Bit 21 - Capture/Compare 6 output Polarity
486    #[inline(always)]
487    pub fn cc6p(&mut self) -> CCP_W<CCERrs> {
488        CCP_W::new(self, 21)
489    }
490    ///Capture/Compare (1-3) complementary output enable
491    ///
492    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NE` field.</div>
493    #[inline(always)]
494    pub fn ccne(&mut self, n: u8) -> CCNE_W<CCERrs> {
495        #[allow(clippy::no_effect)]
496        [(); 3][n as usize];
497        CCNE_W::new(self, n * 4 + 2)
498    }
499    ///Bit 2 - Capture/Compare 1 complementary output enable
500    #[inline(always)]
501    pub fn cc1ne(&mut self) -> CCNE_W<CCERrs> {
502        CCNE_W::new(self, 2)
503    }
504    ///Bit 6 - Capture/Compare 2 complementary output enable
505    #[inline(always)]
506    pub fn cc2ne(&mut self) -> CCNE_W<CCERrs> {
507        CCNE_W::new(self, 6)
508    }
509    ///Bit 10 - Capture/Compare 3 complementary output enable
510    #[inline(always)]
511    pub fn cc3ne(&mut self) -> CCNE_W<CCERrs> {
512        CCNE_W::new(self, 10)
513    }
514    ///Capture/Compare (1-4) output Polarity
515    ///
516    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
517    #[inline(always)]
518    pub fn ccnp(&mut self, n: u8) -> CCNP_W<CCERrs> {
519        #[allow(clippy::no_effect)]
520        [(); 4][n as usize];
521        CCNP_W::new(self, n * 4 + 3)
522    }
523    ///Bit 3 - Capture/Compare 1 output Polarity
524    #[inline(always)]
525    pub fn cc1np(&mut self) -> CCNP_W<CCERrs> {
526        CCNP_W::new(self, 3)
527    }
528    ///Bit 7 - Capture/Compare 2 output Polarity
529    #[inline(always)]
530    pub fn cc2np(&mut self) -> CCNP_W<CCERrs> {
531        CCNP_W::new(self, 7)
532    }
533    ///Bit 11 - Capture/Compare 3 output Polarity
534    #[inline(always)]
535    pub fn cc3np(&mut self) -> CCNP_W<CCERrs> {
536        CCNP_W::new(self, 11)
537    }
538    ///Bit 15 - Capture/Compare 4 output Polarity
539    #[inline(always)]
540    pub fn cc4np(&mut self) -> CCNP_W<CCERrs> {
541        CCNP_W::new(self, 15)
542    }
543}
544/**capture/compare enable register
545
546You can [`read`](crate::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
547
548See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#TIM1:CCER)*/
549pub struct CCERrs;
550impl crate::RegisterSpec for CCERrs {
551    type Ux = u32;
552}
553///`read()` method returns [`ccer::R`](R) reader structure
554impl crate::Readable for CCERrs {}
555///`write(|w| ..)` method takes [`ccer::W`](W) writer structure
556impl crate::Writable for CCERrs {
557    type Safety = crate::Unsafe;
558}
559///`reset()` method sets CCER to value 0
560impl crate::Resettable for CCERrs {}
stm32f7_staging/stm32f779/tim1/ccer.rs

stm32f7_staging/stm32f779/tim1/
ccer.rs
