stm32f7_staging/stm32f779/rtc/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**Wakeup clock selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum WUCKSEL {
12    ///0: RTC/16 clock is selected
13    Div16 = 0,
14    ///1: RTC/8 clock is selected
15    Div8 = 1,
16    ///2: RTC/4 clock is selected
17    Div4 = 2,
18    ///3: RTC/2 clock is selected
19    Div2 = 3,
20    ///4: ck_spre (usually 1 Hz) clock is selected
21    ClockSpare = 4,
22    ///6: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
23    ClockSpareWithOffset = 6,
24}
25impl From<WUCKSEL> for u8 {
26    #[inline(always)]
27    fn from(variant: WUCKSEL) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for WUCKSEL {
32    type Ux = u8;
33}
34impl crate::IsEnum for WUCKSEL {}
35///Field `WUCKSEL` reader - Wakeup clock selection
36pub type WUCKSEL_R = crate::FieldReader<WUCKSEL>;
37impl WUCKSEL_R {
38    ///Get enumerated values variant
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<WUCKSEL> {
41        match self.bits {
42            0 => Some(WUCKSEL::Div16),
43            1 => Some(WUCKSEL::Div8),
44            2 => Some(WUCKSEL::Div4),
45            3 => Some(WUCKSEL::Div2),
46            4 => Some(WUCKSEL::ClockSpare),
47            6 => Some(WUCKSEL::ClockSpareWithOffset),
48            _ => None,
49        }
50    }
51    ///RTC/16 clock is selected
52    #[inline(always)]
53    pub fn is_div16(&self) -> bool {
54        *self == WUCKSEL::Div16
55    }
56    ///RTC/8 clock is selected
57    #[inline(always)]
58    pub fn is_div8(&self) -> bool {
59        *self == WUCKSEL::Div8
60    }
61    ///RTC/4 clock is selected
62    #[inline(always)]
63    pub fn is_div4(&self) -> bool {
64        *self == WUCKSEL::Div4
65    }
66    ///RTC/2 clock is selected
67    #[inline(always)]
68    pub fn is_div2(&self) -> bool {
69        *self == WUCKSEL::Div2
70    }
71    ///ck_spre (usually 1 Hz) clock is selected
72    #[inline(always)]
73    pub fn is_clock_spare(&self) -> bool {
74        *self == WUCKSEL::ClockSpare
75    }
76    ///ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
77    #[inline(always)]
78    pub fn is_clock_spare_with_offset(&self) -> bool {
79        *self == WUCKSEL::ClockSpareWithOffset
80    }
81}
82///Field `WUCKSEL` writer - Wakeup clock selection
83pub type WUCKSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, WUCKSEL>;
84impl<'a, REG> WUCKSEL_W<'a, REG>
85where
86    REG: crate::Writable + crate::RegisterSpec,
87    REG::Ux: From<u8>,
88{
89    ///RTC/16 clock is selected
90    #[inline(always)]
91    pub fn div16(self) -> &'a mut crate::W<REG> {
92        self.variant(WUCKSEL::Div16)
93    }
94    ///RTC/8 clock is selected
95    #[inline(always)]
96    pub fn div8(self) -> &'a mut crate::W<REG> {
97        self.variant(WUCKSEL::Div8)
98    }
99    ///RTC/4 clock is selected
100    #[inline(always)]
101    pub fn div4(self) -> &'a mut crate::W<REG> {
102        self.variant(WUCKSEL::Div4)
103    }
104    ///RTC/2 clock is selected
105    #[inline(always)]
106    pub fn div2(self) -> &'a mut crate::W<REG> {
107        self.variant(WUCKSEL::Div2)
108    }
109    ///ck_spre (usually 1 Hz) clock is selected
110    #[inline(always)]
111    pub fn clock_spare(self) -> &'a mut crate::W<REG> {
112        self.variant(WUCKSEL::ClockSpare)
113    }
114    ///ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
115    #[inline(always)]
116    pub fn clock_spare_with_offset(self) -> &'a mut crate::W<REG> {
117        self.variant(WUCKSEL::ClockSpareWithOffset)
118    }
119}
120/**Time-stamp event active edge
121
122Value on reset: 0*/
123#[cfg_attr(feature = "defmt", derive(defmt::Format))]
124#[derive(Clone, Copy, Debug, PartialEq, Eq)]
125pub enum TSEDGE {
126    ///0: RTC_TS input rising edge generates a time-stamp event
127    RisingEdge = 0,
128    ///1: RTC_TS input falling edge generates a time-stamp event
129    FallingEdge = 1,
130}
131impl From<TSEDGE> for bool {
132    #[inline(always)]
133    fn from(variant: TSEDGE) -> Self {
134        variant as u8 != 0
135    }
136}
137///Field `TSEDGE` reader - Time-stamp event active edge
138pub type TSEDGE_R = crate::BitReader<TSEDGE>;
139impl TSEDGE_R {
140    ///Get enumerated values variant
141    #[inline(always)]
142    pub const fn variant(&self) -> TSEDGE {
143        match self.bits {
144            false => TSEDGE::RisingEdge,
145            true => TSEDGE::FallingEdge,
146        }
147    }
148    ///RTC_TS input rising edge generates a time-stamp event
149    #[inline(always)]
150    pub fn is_rising_edge(&self) -> bool {
151        *self == TSEDGE::RisingEdge
152    }
153    ///RTC_TS input falling edge generates a time-stamp event
154    #[inline(always)]
155    pub fn is_falling_edge(&self) -> bool {
156        *self == TSEDGE::FallingEdge
157    }
158}
159///Field `TSEDGE` writer - Time-stamp event active edge
160pub type TSEDGE_W<'a, REG> = crate::BitWriter<'a, REG, TSEDGE>;
161impl<'a, REG> TSEDGE_W<'a, REG>
162where
163    REG: crate::Writable + crate::RegisterSpec,
164{
165    ///RTC_TS input rising edge generates a time-stamp event
166    #[inline(always)]
167    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
168        self.variant(TSEDGE::RisingEdge)
169    }
170    ///RTC_TS input falling edge generates a time-stamp event
171    #[inline(always)]
172    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
173        self.variant(TSEDGE::FallingEdge)
174    }
175}
176/**Reference clock detection enable (50 or 60 Hz)
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum REFCKON {
182    ///0: RTC_REFIN detection disabled
183    Disabled = 0,
184    ///1: RTC_REFIN detection enabled
185    Enabled = 1,
186}
187impl From<REFCKON> for bool {
188    #[inline(always)]
189    fn from(variant: REFCKON) -> Self {
190        variant as u8 != 0
191    }
192}
193///Field `REFCKON` reader - Reference clock detection enable (50 or 60 Hz)
194pub type REFCKON_R = crate::BitReader<REFCKON>;
195impl REFCKON_R {
196    ///Get enumerated values variant
197    #[inline(always)]
198    pub const fn variant(&self) -> REFCKON {
199        match self.bits {
200            false => REFCKON::Disabled,
201            true => REFCKON::Enabled,
202        }
203    }
204    ///RTC_REFIN detection disabled
205    #[inline(always)]
206    pub fn is_disabled(&self) -> bool {
207        *self == REFCKON::Disabled
208    }
209    ///RTC_REFIN detection enabled
210    #[inline(always)]
211    pub fn is_enabled(&self) -> bool {
212        *self == REFCKON::Enabled
213    }
214}
215///Field `REFCKON` writer - Reference clock detection enable (50 or 60 Hz)
216pub type REFCKON_W<'a, REG> = crate::BitWriter<'a, REG, REFCKON>;
217impl<'a, REG> REFCKON_W<'a, REG>
218where
219    REG: crate::Writable + crate::RegisterSpec,
220{
221    ///RTC_REFIN detection disabled
222    #[inline(always)]
223    pub fn disabled(self) -> &'a mut crate::W<REG> {
224        self.variant(REFCKON::Disabled)
225    }
226    ///RTC_REFIN detection enabled
227    #[inline(always)]
228    pub fn enabled(self) -> &'a mut crate::W<REG> {
229        self.variant(REFCKON::Enabled)
230    }
231}
232/**Bypass the shadow registers
233
234Value on reset: 0*/
235#[cfg_attr(feature = "defmt", derive(defmt::Format))]
236#[derive(Clone, Copy, Debug, PartialEq, Eq)]
237pub enum BYPSHAD {
238    ///0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
239    ShadowReg = 0,
240    ///1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
241    BypassShadowReg = 1,
242}
243impl From<BYPSHAD> for bool {
244    #[inline(always)]
245    fn from(variant: BYPSHAD) -> Self {
246        variant as u8 != 0
247    }
248}
249///Field `BYPSHAD` reader - Bypass the shadow registers
250pub type BYPSHAD_R = crate::BitReader<BYPSHAD>;
251impl BYPSHAD_R {
252    ///Get enumerated values variant
253    #[inline(always)]
254    pub const fn variant(&self) -> BYPSHAD {
255        match self.bits {
256            false => BYPSHAD::ShadowReg,
257            true => BYPSHAD::BypassShadowReg,
258        }
259    }
260    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
261    #[inline(always)]
262    pub fn is_shadow_reg(&self) -> bool {
263        *self == BYPSHAD::ShadowReg
264    }
265    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
266    #[inline(always)]
267    pub fn is_bypass_shadow_reg(&self) -> bool {
268        *self == BYPSHAD::BypassShadowReg
269    }
270}
271///Field `BYPSHAD` writer - Bypass the shadow registers
272pub type BYPSHAD_W<'a, REG> = crate::BitWriter<'a, REG, BYPSHAD>;
273impl<'a, REG> BYPSHAD_W<'a, REG>
274where
275    REG: crate::Writable + crate::RegisterSpec,
276{
277    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
278    #[inline(always)]
279    pub fn shadow_reg(self) -> &'a mut crate::W<REG> {
280        self.variant(BYPSHAD::ShadowReg)
281    }
282    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
283    #[inline(always)]
284    pub fn bypass_shadow_reg(self) -> &'a mut crate::W<REG> {
285        self.variant(BYPSHAD::BypassShadowReg)
286    }
287}
288/**Hour format
289
290Value on reset: 0*/
291#[cfg_attr(feature = "defmt", derive(defmt::Format))]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293pub enum FMT {
294    ///0: 24 hour/day format
295    TwentyFourHour = 0,
296    ///1: AM/PM hour format
297    AmPm = 1,
298}
299impl From<FMT> for bool {
300    #[inline(always)]
301    fn from(variant: FMT) -> Self {
302        variant as u8 != 0
303    }
304}
305///Field `FMT` reader - Hour format
306pub type FMT_R = crate::BitReader<FMT>;
307impl FMT_R {
308    ///Get enumerated values variant
309    #[inline(always)]
310    pub const fn variant(&self) -> FMT {
311        match self.bits {
312            false => FMT::TwentyFourHour,
313            true => FMT::AmPm,
314        }
315    }
316    ///24 hour/day format
317    #[inline(always)]
318    pub fn is_twenty_four_hour(&self) -> bool {
319        *self == FMT::TwentyFourHour
320    }
321    ///AM/PM hour format
322    #[inline(always)]
323    pub fn is_am_pm(&self) -> bool {
324        *self == FMT::AmPm
325    }
326}
327///Field `FMT` writer - Hour format
328pub type FMT_W<'a, REG> = crate::BitWriter<'a, REG, FMT>;
329impl<'a, REG> FMT_W<'a, REG>
330where
331    REG: crate::Writable + crate::RegisterSpec,
332{
333    ///24 hour/day format
334    #[inline(always)]
335    pub fn twenty_four_hour(self) -> &'a mut crate::W<REG> {
336        self.variant(FMT::TwentyFourHour)
337    }
338    ///AM/PM hour format
339    #[inline(always)]
340    pub fn am_pm(self) -> &'a mut crate::W<REG> {
341        self.variant(FMT::AmPm)
342    }
343}
344/**Alarm %s enable
345
346Value on reset: 0*/
347#[cfg_attr(feature = "defmt", derive(defmt::Format))]
348#[derive(Clone, Copy, Debug, PartialEq, Eq)]
349pub enum ALRAE {
350    ///0: Alarm disabled
351    Disabled = 0,
352    ///1: Alarm enabled
353    Enabled = 1,
354}
355impl From<ALRAE> for bool {
356    #[inline(always)]
357    fn from(variant: ALRAE) -> Self {
358        variant as u8 != 0
359    }
360}
361///Field `ALRE(A,B)` reader - Alarm %s enable
362pub type ALRE_R = crate::BitReader<ALRAE>;
363impl ALRE_R {
364    ///Get enumerated values variant
365    #[inline(always)]
366    pub const fn variant(&self) -> ALRAE {
367        match self.bits {
368            false => ALRAE::Disabled,
369            true => ALRAE::Enabled,
370        }
371    }
372    ///Alarm disabled
373    #[inline(always)]
374    pub fn is_disabled(&self) -> bool {
375        *self == ALRAE::Disabled
376    }
377    ///Alarm enabled
378    #[inline(always)]
379    pub fn is_enabled(&self) -> bool {
380        *self == ALRAE::Enabled
381    }
382}
383///Field `ALRE(A,B)` writer - Alarm %s enable
384pub type ALRE_W<'a, REG> = crate::BitWriter<'a, REG, ALRAE>;
385impl<'a, REG> ALRE_W<'a, REG>
386where
387    REG: crate::Writable + crate::RegisterSpec,
388{
389    ///Alarm disabled
390    #[inline(always)]
391    pub fn disabled(self) -> &'a mut crate::W<REG> {
392        self.variant(ALRAE::Disabled)
393    }
394    ///Alarm enabled
395    #[inline(always)]
396    pub fn enabled(self) -> &'a mut crate::W<REG> {
397        self.variant(ALRAE::Enabled)
398    }
399}
400/**Wakeup timer enable
401
402Value on reset: 0*/
403#[cfg_attr(feature = "defmt", derive(defmt::Format))]
404#[derive(Clone, Copy, Debug, PartialEq, Eq)]
405pub enum WUTE {
406    ///0: Wakeup timer disabled
407    Disabled = 0,
408    ///1: Wakeup timer enabled
409    Enabled = 1,
410}
411impl From<WUTE> for bool {
412    #[inline(always)]
413    fn from(variant: WUTE) -> Self {
414        variant as u8 != 0
415    }
416}
417///Field `WUTE` reader - Wakeup timer enable
418pub type WUTE_R = crate::BitReader<WUTE>;
419impl WUTE_R {
420    ///Get enumerated values variant
421    #[inline(always)]
422    pub const fn variant(&self) -> WUTE {
423        match self.bits {
424            false => WUTE::Disabled,
425            true => WUTE::Enabled,
426        }
427    }
428    ///Wakeup timer disabled
429    #[inline(always)]
430    pub fn is_disabled(&self) -> bool {
431        *self == WUTE::Disabled
432    }
433    ///Wakeup timer enabled
434    #[inline(always)]
435    pub fn is_enabled(&self) -> bool {
436        *self == WUTE::Enabled
437    }
438}
439///Field `WUTE` writer - Wakeup timer enable
440pub type WUTE_W<'a, REG> = crate::BitWriter<'a, REG, WUTE>;
441impl<'a, REG> WUTE_W<'a, REG>
442where
443    REG: crate::Writable + crate::RegisterSpec,
444{
445    ///Wakeup timer disabled
446    #[inline(always)]
447    pub fn disabled(self) -> &'a mut crate::W<REG> {
448        self.variant(WUTE::Disabled)
449    }
450    ///Wakeup timer enabled
451    #[inline(always)]
452    pub fn enabled(self) -> &'a mut crate::W<REG> {
453        self.variant(WUTE::Enabled)
454    }
455}
456/**Time stamp enable
457
458Value on reset: 0*/
459#[cfg_attr(feature = "defmt", derive(defmt::Format))]
460#[derive(Clone, Copy, Debug, PartialEq, Eq)]
461pub enum TSE {
462    ///0: Timestamp disabled
463    Disabled = 0,
464    ///1: Timestamp enabled
465    Enabled = 1,
466}
467impl From<TSE> for bool {
468    #[inline(always)]
469    fn from(variant: TSE) -> Self {
470        variant as u8 != 0
471    }
472}
473///Field `TSE` reader - Time stamp enable
474pub type TSE_R = crate::BitReader<TSE>;
475impl TSE_R {
476    ///Get enumerated values variant
477    #[inline(always)]
478    pub const fn variant(&self) -> TSE {
479        match self.bits {
480            false => TSE::Disabled,
481            true => TSE::Enabled,
482        }
483    }
484    ///Timestamp disabled
485    #[inline(always)]
486    pub fn is_disabled(&self) -> bool {
487        *self == TSE::Disabled
488    }
489    ///Timestamp enabled
490    #[inline(always)]
491    pub fn is_enabled(&self) -> bool {
492        *self == TSE::Enabled
493    }
494}
495///Field `TSE` writer - Time stamp enable
496pub type TSE_W<'a, REG> = crate::BitWriter<'a, REG, TSE>;
497impl<'a, REG> TSE_W<'a, REG>
498where
499    REG: crate::Writable + crate::RegisterSpec,
500{
501    ///Timestamp disabled
502    #[inline(always)]
503    pub fn disabled(self) -> &'a mut crate::W<REG> {
504        self.variant(TSE::Disabled)
505    }
506    ///Timestamp enabled
507    #[inline(always)]
508    pub fn enabled(self) -> &'a mut crate::W<REG> {
509        self.variant(TSE::Enabled)
510    }
511}
512/**Alarm %s interrupt enable
513
514Value on reset: 0*/
515#[cfg_attr(feature = "defmt", derive(defmt::Format))]
516#[derive(Clone, Copy, Debug, PartialEq, Eq)]
517pub enum ALRAIE {
518    ///0: Alarm Interrupt disabled
519    Disabled = 0,
520    ///1: Alarm Interrupt enabled
521    Enabled = 1,
522}
523impl From<ALRAIE> for bool {
524    #[inline(always)]
525    fn from(variant: ALRAIE) -> Self {
526        variant as u8 != 0
527    }
528}
529///Field `ALRIE(A,B)` reader - Alarm %s interrupt enable
530pub type ALRIE_R = crate::BitReader<ALRAIE>;
531impl ALRIE_R {
532    ///Get enumerated values variant
533    #[inline(always)]
534    pub const fn variant(&self) -> ALRAIE {
535        match self.bits {
536            false => ALRAIE::Disabled,
537            true => ALRAIE::Enabled,
538        }
539    }
540    ///Alarm Interrupt disabled
541    #[inline(always)]
542    pub fn is_disabled(&self) -> bool {
543        *self == ALRAIE::Disabled
544    }
545    ///Alarm Interrupt enabled
546    #[inline(always)]
547    pub fn is_enabled(&self) -> bool {
548        *self == ALRAIE::Enabled
549    }
550}
551///Field `ALRIE(A,B)` writer - Alarm %s interrupt enable
552pub type ALRIE_W<'a, REG> = crate::BitWriter<'a, REG, ALRAIE>;
553impl<'a, REG> ALRIE_W<'a, REG>
554where
555    REG: crate::Writable + crate::RegisterSpec,
556{
557    ///Alarm Interrupt disabled
558    #[inline(always)]
559    pub fn disabled(self) -> &'a mut crate::W<REG> {
560        self.variant(ALRAIE::Disabled)
561    }
562    ///Alarm Interrupt enabled
563    #[inline(always)]
564    pub fn enabled(self) -> &'a mut crate::W<REG> {
565        self.variant(ALRAIE::Enabled)
566    }
567}
568/**Wakeup timer interrupt enable
569
570Value on reset: 0*/
571#[cfg_attr(feature = "defmt", derive(defmt::Format))]
572#[derive(Clone, Copy, Debug, PartialEq, Eq)]
573pub enum WUTIE {
574    ///0: Wakeup timer interrupt disabled
575    Disabled = 0,
576    ///1: Wakeup timer interrupt enabled
577    Enabled = 1,
578}
579impl From<WUTIE> for bool {
580    #[inline(always)]
581    fn from(variant: WUTIE) -> Self {
582        variant as u8 != 0
583    }
584}
585///Field `WUTIE` reader - Wakeup timer interrupt enable
586pub type WUTIE_R = crate::BitReader<WUTIE>;
587impl WUTIE_R {
588    ///Get enumerated values variant
589    #[inline(always)]
590    pub const fn variant(&self) -> WUTIE {
591        match self.bits {
592            false => WUTIE::Disabled,
593            true => WUTIE::Enabled,
594        }
595    }
596    ///Wakeup timer interrupt disabled
597    #[inline(always)]
598    pub fn is_disabled(&self) -> bool {
599        *self == WUTIE::Disabled
600    }
601    ///Wakeup timer interrupt enabled
602    #[inline(always)]
603    pub fn is_enabled(&self) -> bool {
604        *self == WUTIE::Enabled
605    }
606}
607///Field `WUTIE` writer - Wakeup timer interrupt enable
608pub type WUTIE_W<'a, REG> = crate::BitWriter<'a, REG, WUTIE>;
609impl<'a, REG> WUTIE_W<'a, REG>
610where
611    REG: crate::Writable + crate::RegisterSpec,
612{
613    ///Wakeup timer interrupt disabled
614    #[inline(always)]
615    pub fn disabled(self) -> &'a mut crate::W<REG> {
616        self.variant(WUTIE::Disabled)
617    }
618    ///Wakeup timer interrupt enabled
619    #[inline(always)]
620    pub fn enabled(self) -> &'a mut crate::W<REG> {
621        self.variant(WUTIE::Enabled)
622    }
623}
624/**Time-stamp interrupt enable
625
626Value on reset: 0*/
627#[cfg_attr(feature = "defmt", derive(defmt::Format))]
628#[derive(Clone, Copy, Debug, PartialEq, Eq)]
629pub enum TSIE {
630    ///0: Time-stamp Interrupt disabled
631    Disabled = 0,
632    ///1: Time-stamp Interrupt enabled
633    Enabled = 1,
634}
635impl From<TSIE> for bool {
636    #[inline(always)]
637    fn from(variant: TSIE) -> Self {
638        variant as u8 != 0
639    }
640}
641///Field `TSIE` reader - Time-stamp interrupt enable
642pub type TSIE_R = crate::BitReader<TSIE>;
643impl TSIE_R {
644    ///Get enumerated values variant
645    #[inline(always)]
646    pub const fn variant(&self) -> TSIE {
647        match self.bits {
648            false => TSIE::Disabled,
649            true => TSIE::Enabled,
650        }
651    }
652    ///Time-stamp Interrupt disabled
653    #[inline(always)]
654    pub fn is_disabled(&self) -> bool {
655        *self == TSIE::Disabled
656    }
657    ///Time-stamp Interrupt enabled
658    #[inline(always)]
659    pub fn is_enabled(&self) -> bool {
660        *self == TSIE::Enabled
661    }
662}
663///Field `TSIE` writer - Time-stamp interrupt enable
664pub type TSIE_W<'a, REG> = crate::BitWriter<'a, REG, TSIE>;
665impl<'a, REG> TSIE_W<'a, REG>
666where
667    REG: crate::Writable + crate::RegisterSpec,
668{
669    ///Time-stamp Interrupt disabled
670    #[inline(always)]
671    pub fn disabled(self) -> &'a mut crate::W<REG> {
672        self.variant(TSIE::Disabled)
673    }
674    ///Time-stamp Interrupt enabled
675    #[inline(always)]
676    pub fn enabled(self) -> &'a mut crate::W<REG> {
677        self.variant(TSIE::Enabled)
678    }
679}
680/**Add 1 hour (summer time change)
681
682Value on reset: 0*/
683#[cfg_attr(feature = "defmt", derive(defmt::Format))]
684#[derive(Clone, Copy, Debug, PartialEq, Eq)]
685pub enum ADD1HW {
686    ///1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
687    Add1 = 1,
688}
689impl From<ADD1HW> for bool {
690    #[inline(always)]
691    fn from(variant: ADD1HW) -> Self {
692        variant as u8 != 0
693    }
694}
695///Field `ADD1H` reader - Add 1 hour (summer time change)
696pub type ADD1H_R = crate::BitReader<ADD1HW>;
697impl ADD1H_R {
698    ///Get enumerated values variant
699    #[inline(always)]
700    pub const fn variant(&self) -> Option<ADD1HW> {
701        match self.bits {
702            true => Some(ADD1HW::Add1),
703            _ => None,
704        }
705    }
706    ///Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
707    #[inline(always)]
708    pub fn is_add1(&self) -> bool {
709        *self == ADD1HW::Add1
710    }
711}
712///Field `ADD1H` writer - Add 1 hour (summer time change)
713pub type ADD1H_W<'a, REG> = crate::BitWriter<'a, REG, ADD1HW>;
714impl<'a, REG> ADD1H_W<'a, REG>
715where
716    REG: crate::Writable + crate::RegisterSpec,
717{
718    ///Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
719    #[inline(always)]
720    pub fn add1(self) -> &'a mut crate::W<REG> {
721        self.variant(ADD1HW::Add1)
722    }
723}
724/**Subtract 1 hour (winter time change)
725
726Value on reset: 0*/
727#[cfg_attr(feature = "defmt", derive(defmt::Format))]
728#[derive(Clone, Copy, Debug, PartialEq, Eq)]
729pub enum SUB1HW {
730    ///1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
731    Sub1 = 1,
732}
733impl From<SUB1HW> for bool {
734    #[inline(always)]
735    fn from(variant: SUB1HW) -> Self {
736        variant as u8 != 0
737    }
738}
739///Field `SUB1H` reader - Subtract 1 hour (winter time change)
740pub type SUB1H_R = crate::BitReader<SUB1HW>;
741impl SUB1H_R {
742    ///Get enumerated values variant
743    #[inline(always)]
744    pub const fn variant(&self) -> Option<SUB1HW> {
745        match self.bits {
746            true => Some(SUB1HW::Sub1),
747            _ => None,
748        }
749    }
750    ///Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
751    #[inline(always)]
752    pub fn is_sub1(&self) -> bool {
753        *self == SUB1HW::Sub1
754    }
755}
756///Field `SUB1H` writer - Subtract 1 hour (winter time change)
757pub type SUB1H_W<'a, REG> = crate::BitWriter<'a, REG, SUB1HW>;
758impl<'a, REG> SUB1H_W<'a, REG>
759where
760    REG: crate::Writable + crate::RegisterSpec,
761{
762    ///Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
763    #[inline(always)]
764    pub fn sub1(self) -> &'a mut crate::W<REG> {
765        self.variant(SUB1HW::Sub1)
766    }
767}
768/**Backup
769
770Value on reset: 0*/
771#[cfg_attr(feature = "defmt", derive(defmt::Format))]
772#[derive(Clone, Copy, Debug, PartialEq, Eq)]
773pub enum BKP {
774    ///0: Daylight Saving Time change has not been performed
775    DstNotChanged = 0,
776    ///1: Daylight Saving Time change has been performed
777    DstChanged = 1,
778}
779impl From<BKP> for bool {
780    #[inline(always)]
781    fn from(variant: BKP) -> Self {
782        variant as u8 != 0
783    }
784}
785///Field `BKP` reader - Backup
786pub type BKP_R = crate::BitReader<BKP>;
787impl BKP_R {
788    ///Get enumerated values variant
789    #[inline(always)]
790    pub const fn variant(&self) -> BKP {
791        match self.bits {
792            false => BKP::DstNotChanged,
793            true => BKP::DstChanged,
794        }
795    }
796    ///Daylight Saving Time change has not been performed
797    #[inline(always)]
798    pub fn is_dst_not_changed(&self) -> bool {
799        *self == BKP::DstNotChanged
800    }
801    ///Daylight Saving Time change has been performed
802    #[inline(always)]
803    pub fn is_dst_changed(&self) -> bool {
804        *self == BKP::DstChanged
805    }
806}
807///Field `BKP` writer - Backup
808pub type BKP_W<'a, REG> = crate::BitWriter<'a, REG, BKP>;
809impl<'a, REG> BKP_W<'a, REG>
810where
811    REG: crate::Writable + crate::RegisterSpec,
812{
813    ///Daylight Saving Time change has not been performed
814    #[inline(always)]
815    pub fn dst_not_changed(self) -> &'a mut crate::W<REG> {
816        self.variant(BKP::DstNotChanged)
817    }
818    ///Daylight Saving Time change has been performed
819    #[inline(always)]
820    pub fn dst_changed(self) -> &'a mut crate::W<REG> {
821        self.variant(BKP::DstChanged)
822    }
823}
824/**Calibration output selection
825
826Value on reset: 0*/
827#[cfg_attr(feature = "defmt", derive(defmt::Format))]
828#[derive(Clone, Copy, Debug, PartialEq, Eq)]
829pub enum COSEL {
830    ///0: Calibration output is 512 Hz (with default prescaler setting)
831    CalFreq512hz = 0,
832    ///1: Calibration output is 1 Hz (with default prescaler setting)
833    CalFreq1hz = 1,
834}
835impl From<COSEL> for bool {
836    #[inline(always)]
837    fn from(variant: COSEL) -> Self {
838        variant as u8 != 0
839    }
840}
841///Field `COSEL` reader - Calibration output selection
842pub type COSEL_R = crate::BitReader<COSEL>;
843impl COSEL_R {
844    ///Get enumerated values variant
845    #[inline(always)]
846    pub const fn variant(&self) -> COSEL {
847        match self.bits {
848            false => COSEL::CalFreq512hz,
849            true => COSEL::CalFreq1hz,
850        }
851    }
852    ///Calibration output is 512 Hz (with default prescaler setting)
853    #[inline(always)]
854    pub fn is_cal_freq_512hz(&self) -> bool {
855        *self == COSEL::CalFreq512hz
856    }
857    ///Calibration output is 1 Hz (with default prescaler setting)
858    #[inline(always)]
859    pub fn is_cal_freq_1hz(&self) -> bool {
860        *self == COSEL::CalFreq1hz
861    }
862}
863///Field `COSEL` writer - Calibration output selection
864pub type COSEL_W<'a, REG> = crate::BitWriter<'a, REG, COSEL>;
865impl<'a, REG> COSEL_W<'a, REG>
866where
867    REG: crate::Writable + crate::RegisterSpec,
868{
869    ///Calibration output is 512 Hz (with default prescaler setting)
870    #[inline(always)]
871    pub fn cal_freq_512hz(self) -> &'a mut crate::W<REG> {
872        self.variant(COSEL::CalFreq512hz)
873    }
874    ///Calibration output is 1 Hz (with default prescaler setting)
875    #[inline(always)]
876    pub fn cal_freq_1hz(self) -> &'a mut crate::W<REG> {
877        self.variant(COSEL::CalFreq1hz)
878    }
879}
880/**Output polarity
881
882Value on reset: 0*/
883#[cfg_attr(feature = "defmt", derive(defmt::Format))]
884#[derive(Clone, Copy, Debug, PartialEq, Eq)]
885pub enum POL {
886    ///0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
887    High = 0,
888    ///1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
889    Low = 1,
890}
891impl From<POL> for bool {
892    #[inline(always)]
893    fn from(variant: POL) -> Self {
894        variant as u8 != 0
895    }
896}
897///Field `POL` reader - Output polarity
898pub type POL_R = crate::BitReader<POL>;
899impl POL_R {
900    ///Get enumerated values variant
901    #[inline(always)]
902    pub const fn variant(&self) -> POL {
903        match self.bits {
904            false => POL::High,
905            true => POL::Low,
906        }
907    }
908    ///The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
909    #[inline(always)]
910    pub fn is_high(&self) -> bool {
911        *self == POL::High
912    }
913    ///The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
914    #[inline(always)]
915    pub fn is_low(&self) -> bool {
916        *self == POL::Low
917    }
918}
919///Field `POL` writer - Output polarity
920pub type POL_W<'a, REG> = crate::BitWriter<'a, REG, POL>;
921impl<'a, REG> POL_W<'a, REG>
922where
923    REG: crate::Writable + crate::RegisterSpec,
924{
925    ///The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
926    #[inline(always)]
927    pub fn high(self) -> &'a mut crate::W<REG> {
928        self.variant(POL::High)
929    }
930    ///The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
931    #[inline(always)]
932    pub fn low(self) -> &'a mut crate::W<REG> {
933        self.variant(POL::Low)
934    }
935}
936/**Output selection
937
938Value on reset: 0*/
939#[cfg_attr(feature = "defmt", derive(defmt::Format))]
940#[derive(Clone, Copy, Debug, PartialEq, Eq)]
941#[repr(u8)]
942pub enum OSEL {
943    ///0: Output disabled
944    Disabled = 0,
945    ///1: Alarm A output enabled
946    AlarmA = 1,
947    ///2: Alarm B output enabled
948    AlarmB = 2,
949    ///3: Wakeup output enabled
950    Wakeup = 3,
951}
952impl From<OSEL> for u8 {
953    #[inline(always)]
954    fn from(variant: OSEL) -> Self {
955        variant as _
956    }
957}
958impl crate::FieldSpec for OSEL {
959    type Ux = u8;
960}
961impl crate::IsEnum for OSEL {}
962///Field `OSEL` reader - Output selection
963pub type OSEL_R = crate::FieldReader<OSEL>;
964impl OSEL_R {
965    ///Get enumerated values variant
966    #[inline(always)]
967    pub const fn variant(&self) -> OSEL {
968        match self.bits {
969            0 => OSEL::Disabled,
970            1 => OSEL::AlarmA,
971            2 => OSEL::AlarmB,
972            3 => OSEL::Wakeup,
973            _ => unreachable!(),
974        }
975    }
976    ///Output disabled
977    #[inline(always)]
978    pub fn is_disabled(&self) -> bool {
979        *self == OSEL::Disabled
980    }
981    ///Alarm A output enabled
982    #[inline(always)]
983    pub fn is_alarm_a(&self) -> bool {
984        *self == OSEL::AlarmA
985    }
986    ///Alarm B output enabled
987    #[inline(always)]
988    pub fn is_alarm_b(&self) -> bool {
989        *self == OSEL::AlarmB
990    }
991    ///Wakeup output enabled
992    #[inline(always)]
993    pub fn is_wakeup(&self) -> bool {
994        *self == OSEL::Wakeup
995    }
996}
997///Field `OSEL` writer - Output selection
998pub type OSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OSEL, crate::Safe>;
999impl<'a, REG> OSEL_W<'a, REG>
1000where
1001    REG: crate::Writable + crate::RegisterSpec,
1002    REG::Ux: From<u8>,
1003{
1004    ///Output disabled
1005    #[inline(always)]
1006    pub fn disabled(self) -> &'a mut crate::W<REG> {
1007        self.variant(OSEL::Disabled)
1008    }
1009    ///Alarm A output enabled
1010    #[inline(always)]
1011    pub fn alarm_a(self) -> &'a mut crate::W<REG> {
1012        self.variant(OSEL::AlarmA)
1013    }
1014    ///Alarm B output enabled
1015    #[inline(always)]
1016    pub fn alarm_b(self) -> &'a mut crate::W<REG> {
1017        self.variant(OSEL::AlarmB)
1018    }
1019    ///Wakeup output enabled
1020    #[inline(always)]
1021    pub fn wakeup(self) -> &'a mut crate::W<REG> {
1022        self.variant(OSEL::Wakeup)
1023    }
1024}
1025/**Calibration output enable
1026
1027Value on reset: 0*/
1028#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1029#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1030pub enum COE {
1031    ///0: Calibration output disabled
1032    Disabled = 0,
1033    ///1: Calibration output enabled
1034    Enabled = 1,
1035}
1036impl From<COE> for bool {
1037    #[inline(always)]
1038    fn from(variant: COE) -> Self {
1039        variant as u8 != 0
1040    }
1041}
1042///Field `COE` reader - Calibration output enable
1043pub type COE_R = crate::BitReader<COE>;
1044impl COE_R {
1045    ///Get enumerated values variant
1046    #[inline(always)]
1047    pub const fn variant(&self) -> COE {
1048        match self.bits {
1049            false => COE::Disabled,
1050            true => COE::Enabled,
1051        }
1052    }
1053    ///Calibration output disabled
1054    #[inline(always)]
1055    pub fn is_disabled(&self) -> bool {
1056        *self == COE::Disabled
1057    }
1058    ///Calibration output enabled
1059    #[inline(always)]
1060    pub fn is_enabled(&self) -> bool {
1061        *self == COE::Enabled
1062    }
1063}
1064///Field `COE` writer - Calibration output enable
1065pub type COE_W<'a, REG> = crate::BitWriter<'a, REG, COE>;
1066impl<'a, REG> COE_W<'a, REG>
1067where
1068    REG: crate::Writable + crate::RegisterSpec,
1069{
1070    ///Calibration output disabled
1071    #[inline(always)]
1072    pub fn disabled(self) -> &'a mut crate::W<REG> {
1073        self.variant(COE::Disabled)
1074    }
1075    ///Calibration output enabled
1076    #[inline(always)]
1077    pub fn enabled(self) -> &'a mut crate::W<REG> {
1078        self.variant(COE::Enabled)
1079    }
1080}
1081///Field `ITSE` reader - timestamp on internal event enable
1082pub type ITSE_R = crate::BitReader;
1083///Field `ITSE` writer - timestamp on internal event enable
1084pub type ITSE_W<'a, REG> = crate::BitWriter<'a, REG>;
1085impl R {
1086    ///Bits 0:2 - Wakeup clock selection
1087    #[inline(always)]
1088    pub fn wucksel(&self) -> WUCKSEL_R {
1089        WUCKSEL_R::new((self.bits & 7) as u8)
1090    }
1091    ///Bit 3 - Time-stamp event active edge
1092    #[inline(always)]
1093    pub fn tsedge(&self) -> TSEDGE_R {
1094        TSEDGE_R::new(((self.bits >> 3) & 1) != 0)
1095    }
1096    ///Bit 4 - Reference clock detection enable (50 or 60 Hz)
1097    #[inline(always)]
1098    pub fn refckon(&self) -> REFCKON_R {
1099        REFCKON_R::new(((self.bits >> 4) & 1) != 0)
1100    }
1101    ///Bit 5 - Bypass the shadow registers
1102    #[inline(always)]
1103    pub fn bypshad(&self) -> BYPSHAD_R {
1104        BYPSHAD_R::new(((self.bits >> 5) & 1) != 0)
1105    }
1106    ///Bit 6 - Hour format
1107    #[inline(always)]
1108    pub fn fmt(&self) -> FMT_R {
1109        FMT_R::new(((self.bits >> 6) & 1) != 0)
1110    }
1111    ///Alarm (A,B) enable
1112    ///
1113    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAE` field.</div>
1114    #[inline(always)]
1115    pub fn alre(&self, n: u8) -> ALRE_R {
1116        #[allow(clippy::no_effect)]
1117        [(); 2][n as usize];
1118        ALRE_R::new(((self.bits >> (n + 8)) & 1) != 0)
1119    }
1120    ///Iterator for array of:
1121    ///Alarm (A,B) enable
1122    #[inline(always)]
1123    pub fn alre_iter(&self) -> impl Iterator<Item = ALRE_R> + '_ {
1124        (0..2).map(move |n| ALRE_R::new(((self.bits >> (n + 8)) & 1) != 0))
1125    }
1126    ///Bit 8 - Alarm A enable
1127    #[inline(always)]
1128    pub fn alrae(&self) -> ALRE_R {
1129        ALRE_R::new(((self.bits >> 8) & 1) != 0)
1130    }
1131    ///Bit 9 - Alarm B enable
1132    #[inline(always)]
1133    pub fn alrbe(&self) -> ALRE_R {
1134        ALRE_R::new(((self.bits >> 9) & 1) != 0)
1135    }
1136    ///Bit 10 - Wakeup timer enable
1137    #[inline(always)]
1138    pub fn wute(&self) -> WUTE_R {
1139        WUTE_R::new(((self.bits >> 10) & 1) != 0)
1140    }
1141    ///Bit 11 - Time stamp enable
1142    #[inline(always)]
1143    pub fn tse(&self) -> TSE_R {
1144        TSE_R::new(((self.bits >> 11) & 1) != 0)
1145    }
1146    ///Alarm (A,B) interrupt enable
1147    ///
1148    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAIE` field.</div>
1149    #[inline(always)]
1150    pub fn alrie(&self, n: u8) -> ALRIE_R {
1151        #[allow(clippy::no_effect)]
1152        [(); 2][n as usize];
1153        ALRIE_R::new(((self.bits >> (n + 12)) & 1) != 0)
1154    }
1155    ///Iterator for array of:
1156    ///Alarm (A,B) interrupt enable
1157    #[inline(always)]
1158    pub fn alrie_iter(&self) -> impl Iterator<Item = ALRIE_R> + '_ {
1159        (0..2).map(move |n| ALRIE_R::new(((self.bits >> (n + 12)) & 1) != 0))
1160    }
1161    ///Bit 12 - Alarm A interrupt enable
1162    #[inline(always)]
1163    pub fn alraie(&self) -> ALRIE_R {
1164        ALRIE_R::new(((self.bits >> 12) & 1) != 0)
1165    }
1166    ///Bit 13 - Alarm B interrupt enable
1167    #[inline(always)]
1168    pub fn alrbie(&self) -> ALRIE_R {
1169        ALRIE_R::new(((self.bits >> 13) & 1) != 0)
1170    }
1171    ///Bit 14 - Wakeup timer interrupt enable
1172    #[inline(always)]
1173    pub fn wutie(&self) -> WUTIE_R {
1174        WUTIE_R::new(((self.bits >> 14) & 1) != 0)
1175    }
1176    ///Bit 15 - Time-stamp interrupt enable
1177    #[inline(always)]
1178    pub fn tsie(&self) -> TSIE_R {
1179        TSIE_R::new(((self.bits >> 15) & 1) != 0)
1180    }
1181    ///Bit 16 - Add 1 hour (summer time change)
1182    #[inline(always)]
1183    pub fn add1h(&self) -> ADD1H_R {
1184        ADD1H_R::new(((self.bits >> 16) & 1) != 0)
1185    }
1186    ///Bit 17 - Subtract 1 hour (winter time change)
1187    #[inline(always)]
1188    pub fn sub1h(&self) -> SUB1H_R {
1189        SUB1H_R::new(((self.bits >> 17) & 1) != 0)
1190    }
1191    ///Bit 18 - Backup
1192    #[inline(always)]
1193    pub fn bkp(&self) -> BKP_R {
1194        BKP_R::new(((self.bits >> 18) & 1) != 0)
1195    }
1196    ///Bit 19 - Calibration output selection
1197    #[inline(always)]
1198    pub fn cosel(&self) -> COSEL_R {
1199        COSEL_R::new(((self.bits >> 19) & 1) != 0)
1200    }
1201    ///Bit 20 - Output polarity
1202    #[inline(always)]
1203    pub fn pol(&self) -> POL_R {
1204        POL_R::new(((self.bits >> 20) & 1) != 0)
1205    }
1206    ///Bits 21:22 - Output selection
1207    #[inline(always)]
1208    pub fn osel(&self) -> OSEL_R {
1209        OSEL_R::new(((self.bits >> 21) & 3) as u8)
1210    }
1211    ///Bit 23 - Calibration output enable
1212    #[inline(always)]
1213    pub fn coe(&self) -> COE_R {
1214        COE_R::new(((self.bits >> 23) & 1) != 0)
1215    }
1216    ///Bit 24 - timestamp on internal event enable
1217    #[inline(always)]
1218    pub fn itse(&self) -> ITSE_R {
1219        ITSE_R::new(((self.bits >> 24) & 1) != 0)
1220    }
1221}
1222impl core::fmt::Debug for R {
1223    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1224        f.debug_struct("CR")
1225            .field("wucksel", &self.wucksel())
1226            .field("tsedge", &self.tsedge())
1227            .field("refckon", &self.refckon())
1228            .field("bypshad", &self.bypshad())
1229            .field("fmt", &self.fmt())
1230            .field("alrae", &self.alrae())
1231            .field("alrbe", &self.alrbe())
1232            .field("wute", &self.wute())
1233            .field("tse", &self.tse())
1234            .field("alraie", &self.alraie())
1235            .field("alrbie", &self.alrbie())
1236            .field("wutie", &self.wutie())
1237            .field("tsie", &self.tsie())
1238            .field("add1h", &self.add1h())
1239            .field("sub1h", &self.sub1h())
1240            .field("bkp", &self.bkp())
1241            .field("cosel", &self.cosel())
1242            .field("pol", &self.pol())
1243            .field("osel", &self.osel())
1244            .field("coe", &self.coe())
1245            .field("itse", &self.itse())
1246            .finish()
1247    }
1248}
1249impl W {
1250    ///Bits 0:2 - Wakeup clock selection
1251    #[inline(always)]
1252    pub fn wucksel(&mut self) -> WUCKSEL_W<CRrs> {
1253        WUCKSEL_W::new(self, 0)
1254    }
1255    ///Bit 3 - Time-stamp event active edge
1256    #[inline(always)]
1257    pub fn tsedge(&mut self) -> TSEDGE_W<CRrs> {
1258        TSEDGE_W::new(self, 3)
1259    }
1260    ///Bit 4 - Reference clock detection enable (50 or 60 Hz)
1261    #[inline(always)]
1262    pub fn refckon(&mut self) -> REFCKON_W<CRrs> {
1263        REFCKON_W::new(self, 4)
1264    }
1265    ///Bit 5 - Bypass the shadow registers
1266    #[inline(always)]
1267    pub fn bypshad(&mut self) -> BYPSHAD_W<CRrs> {
1268        BYPSHAD_W::new(self, 5)
1269    }
1270    ///Bit 6 - Hour format
1271    #[inline(always)]
1272    pub fn fmt(&mut self) -> FMT_W<CRrs> {
1273        FMT_W::new(self, 6)
1274    }
1275    ///Alarm (A,B) enable
1276    ///
1277    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAE` field.</div>
1278    #[inline(always)]
1279    pub fn alre(&mut self, n: u8) -> ALRE_W<CRrs> {
1280        #[allow(clippy::no_effect)]
1281        [(); 2][n as usize];
1282        ALRE_W::new(self, n + 8)
1283    }
1284    ///Bit 8 - Alarm A enable
1285    #[inline(always)]
1286    pub fn alrae(&mut self) -> ALRE_W<CRrs> {
1287        ALRE_W::new(self, 8)
1288    }
1289    ///Bit 9 - Alarm B enable
1290    #[inline(always)]
1291    pub fn alrbe(&mut self) -> ALRE_W<CRrs> {
1292        ALRE_W::new(self, 9)
1293    }
1294    ///Bit 10 - Wakeup timer enable
1295    #[inline(always)]
1296    pub fn wute(&mut self) -> WUTE_W<CRrs> {
1297        WUTE_W::new(self, 10)
1298    }
1299    ///Bit 11 - Time stamp enable
1300    #[inline(always)]
1301    pub fn tse(&mut self) -> TSE_W<CRrs> {
1302        TSE_W::new(self, 11)
1303    }
1304    ///Alarm (A,B) interrupt enable
1305    ///
1306    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAIE` field.</div>
1307    #[inline(always)]
1308    pub fn alrie(&mut self, n: u8) -> ALRIE_W<CRrs> {
1309        #[allow(clippy::no_effect)]
1310        [(); 2][n as usize];
1311        ALRIE_W::new(self, n + 12)
1312    }
1313    ///Bit 12 - Alarm A interrupt enable
1314    #[inline(always)]
1315    pub fn alraie(&mut self) -> ALRIE_W<CRrs> {
1316        ALRIE_W::new(self, 12)
1317    }
1318    ///Bit 13 - Alarm B interrupt enable
1319    #[inline(always)]
1320    pub fn alrbie(&mut self) -> ALRIE_W<CRrs> {
1321        ALRIE_W::new(self, 13)
1322    }
1323    ///Bit 14 - Wakeup timer interrupt enable
1324    #[inline(always)]
1325    pub fn wutie(&mut self) -> WUTIE_W<CRrs> {
1326        WUTIE_W::new(self, 14)
1327    }
1328    ///Bit 15 - Time-stamp interrupt enable
1329    #[inline(always)]
1330    pub fn tsie(&mut self) -> TSIE_W<CRrs> {
1331        TSIE_W::new(self, 15)
1332    }
1333    ///Bit 16 - Add 1 hour (summer time change)
1334    #[inline(always)]
1335    pub fn add1h(&mut self) -> ADD1H_W<CRrs> {
1336        ADD1H_W::new(self, 16)
1337    }
1338    ///Bit 17 - Subtract 1 hour (winter time change)
1339    #[inline(always)]
1340    pub fn sub1h(&mut self) -> SUB1H_W<CRrs> {
1341        SUB1H_W::new(self, 17)
1342    }
1343    ///Bit 18 - Backup
1344    #[inline(always)]
1345    pub fn bkp(&mut self) -> BKP_W<CRrs> {
1346        BKP_W::new(self, 18)
1347    }
1348    ///Bit 19 - Calibration output selection
1349    #[inline(always)]
1350    pub fn cosel(&mut self) -> COSEL_W<CRrs> {
1351        COSEL_W::new(self, 19)
1352    }
1353    ///Bit 20 - Output polarity
1354    #[inline(always)]
1355    pub fn pol(&mut self) -> POL_W<CRrs> {
1356        POL_W::new(self, 20)
1357    }
1358    ///Bits 21:22 - Output selection
1359    #[inline(always)]
1360    pub fn osel(&mut self) -> OSEL_W<CRrs> {
1361        OSEL_W::new(self, 21)
1362    }
1363    ///Bit 23 - Calibration output enable
1364    #[inline(always)]
1365    pub fn coe(&mut self) -> COE_W<CRrs> {
1366        COE_W::new(self, 23)
1367    }
1368    ///Bit 24 - timestamp on internal event enable
1369    #[inline(always)]
1370    pub fn itse(&mut self) -> ITSE_W<CRrs> {
1371        ITSE_W::new(self, 24)
1372    }
1373}
1374/**control register
1375
1376You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1377
1378See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#RTC:CR)*/
1379pub struct CRrs;
1380impl crate::RegisterSpec for CRrs {
1381    type Ux = u32;
1382}
1383///`read()` method returns [`cr::R`](R) reader structure
1384impl crate::Readable for CRrs {}
1385///`write(|w| ..)` method takes [`cr::W`](W) writer structure
1386impl crate::Writable for CRrs {
1387    type Safety = crate::Unsafe;
1388}
1389///`reset()` method sets CR to value 0
1390impl crate::Resettable for CRrs {}
stm32f7_staging/stm32f779/rtc/cr.rs

stm32f7_staging/stm32f779/rtc/
cr.rs
