stm32f7_staging/stm32f779/rng/
sr.rs

1///Register `SR` reader
2pub type R = crate::R<SRrs>;
3///Register `SR` writer
4pub type W = crate::W<SRrs>;
5/**Data ready
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DRDY {
11    ///0: The RNG_DR register is not yet valid, no random data is available
12    Invalid = 0,
13    ///1: The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated.
14    Valid = 1,
15}
16impl From<DRDY> for bool {
17    #[inline(always)]
18    fn from(variant: DRDY) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DRDY` reader - Data ready
23pub type DRDY_R = crate::BitReader<DRDY>;
24impl DRDY_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DRDY {
28        match self.bits {
29            false => DRDY::Invalid,
30            true => DRDY::Valid,
31        }
32    }
33    ///The RNG_DR register is not yet valid, no random data is available
34    #[inline(always)]
35    pub fn is_invalid(&self) -> bool {
36        *self == DRDY::Invalid
37    }
38    ///The RNG_DR register contains valid random data. Once the RNG_DR register has been read, this bit returns to 0 until a new random value is generated.
39    #[inline(always)]
40    pub fn is_valid(&self) -> bool {
41        *self == DRDY::Valid
42    }
43}
44/**Clock error current status
45
46Value on reset: 0*/
47#[cfg_attr(feature = "defmt", derive(defmt::Format))]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum CECS {
50    ///0: The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.
51    Correct = 0,
52    ///1: The RNG clock is too slow
53    Slow = 1,
54}
55impl From<CECS> for bool {
56    #[inline(always)]
57    fn from(variant: CECS) -> Self {
58        variant as u8 != 0
59    }
60}
61///Field `CECS` reader - Clock error current status
62pub type CECS_R = crate::BitReader<CECS>;
63impl CECS_R {
64    ///Get enumerated values variant
65    #[inline(always)]
66    pub const fn variant(&self) -> CECS {
67        match self.bits {
68            false => CECS::Correct,
69            true => CECS::Slow,
70        }
71    }
72    ///The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.
73    #[inline(always)]
74    pub fn is_correct(&self) -> bool {
75        *self == CECS::Correct
76    }
77    ///The RNG clock is too slow
78    #[inline(always)]
79    pub fn is_slow(&self) -> bool {
80        *self == CECS::Slow
81    }
82}
83/**Seed error current status
84
85Value on reset: 0*/
86#[cfg_attr(feature = "defmt", derive(defmt::Format))]
87#[derive(Clone, Copy, Debug, PartialEq, Eq)]
88pub enum SECS {
89    ///0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.
90    NoFault = 0,
91    ///1: At least one faulty sequence has been detected - see ref manual for details
92    Fault = 1,
93}
94impl From<SECS> for bool {
95    #[inline(always)]
96    fn from(variant: SECS) -> Self {
97        variant as u8 != 0
98    }
99}
100///Field `SECS` reader - Seed error current status
101pub type SECS_R = crate::BitReader<SECS>;
102impl SECS_R {
103    ///Get enumerated values variant
104    #[inline(always)]
105    pub const fn variant(&self) -> SECS {
106        match self.bits {
107            false => SECS::NoFault,
108            true => SECS::Fault,
109        }
110    }
111    ///No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.
112    #[inline(always)]
113    pub fn is_no_fault(&self) -> bool {
114        *self == SECS::NoFault
115    }
116    ///At least one faulty sequence has been detected - see ref manual for details
117    #[inline(always)]
118    pub fn is_fault(&self) -> bool {
119        *self == SECS::Fault
120    }
121}
122/**Clock error interrupt status
123
124Value on reset: 0*/
125#[cfg_attr(feature = "defmt", derive(defmt::Format))]
126#[derive(Clone, Copy, Debug, PartialEq, Eq)]
127pub enum CEISR {
128    ///0: The RNG clock is correct
129    Correct = 0,
130    ///1: The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register
131    Slow = 1,
132}
133impl From<CEISR> for bool {
134    #[inline(always)]
135    fn from(variant: CEISR) -> Self {
136        variant as u8 != 0
137    }
138}
139///Field `CEIS` reader - Clock error interrupt status
140pub type CEIS_R = crate::BitReader<CEISR>;
141impl CEIS_R {
142    ///Get enumerated values variant
143    #[inline(always)]
144    pub const fn variant(&self) -> CEISR {
145        match self.bits {
146            false => CEISR::Correct,
147            true => CEISR::Slow,
148        }
149    }
150    ///The RNG clock is correct
151    #[inline(always)]
152    pub fn is_correct(&self) -> bool {
153        *self == CEISR::Correct
154    }
155    ///The RNG has been detected too slow An interrupt is pending if IE = 1 in the RNG_CR register
156    #[inline(always)]
157    pub fn is_slow(&self) -> bool {
158        *self == CEISR::Slow
159    }
160}
161/**Clock error interrupt status
162
163Value on reset: 0*/
164#[cfg_attr(feature = "defmt", derive(defmt::Format))]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum CEISW {
167    ///0: Clear flag
168    Clear = 0,
169}
170impl From<CEISW> for bool {
171    #[inline(always)]
172    fn from(variant: CEISW) -> Self {
173        variant as u8 != 0
174    }
175}
176///Field `CEIS` writer - Clock error interrupt status
177pub type CEIS_W<'a, REG> = crate::BitWriter0C<'a, REG, CEISW>;
178impl<'a, REG> CEIS_W<'a, REG>
179where
180    REG: crate::Writable + crate::RegisterSpec,
181{
182    ///Clear flag
183    #[inline(always)]
184    pub fn clear(self) -> &'a mut crate::W<REG> {
185        self.variant(CEISW::Clear)
186    }
187}
188/**Seed error interrupt status
189
190Value on reset: 0*/
191#[cfg_attr(feature = "defmt", derive(defmt::Format))]
192#[derive(Clone, Copy, Debug, PartialEq, Eq)]
193pub enum SEISR {
194    ///0: No faulty sequence detected
195    NoFault = 0,
196    ///1: At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register.
197    Fault = 1,
198}
199impl From<SEISR> for bool {
200    #[inline(always)]
201    fn from(variant: SEISR) -> Self {
202        variant as u8 != 0
203    }
204}
205///Field `SEIS` reader - Seed error interrupt status
206pub type SEIS_R = crate::BitReader<SEISR>;
207impl SEIS_R {
208    ///Get enumerated values variant
209    #[inline(always)]
210    pub const fn variant(&self) -> SEISR {
211        match self.bits {
212            false => SEISR::NoFault,
213            true => SEISR::Fault,
214        }
215    }
216    ///No faulty sequence detected
217    #[inline(always)]
218    pub fn is_no_fault(&self) -> bool {
219        *self == SEISR::NoFault
220    }
221    ///At least one faulty sequence has been detected. See **SECS** bit description for details. An interrupt is pending if IE = 1 in the RNG_CR register.
222    #[inline(always)]
223    pub fn is_fault(&self) -> bool {
224        *self == SEISR::Fault
225    }
226}
227///Field `SEIS` writer - Seed error interrupt status
228pub use CEIS_W as SEIS_W;
229impl R {
230    ///Bit 0 - Data ready
231    #[inline(always)]
232    pub fn drdy(&self) -> DRDY_R {
233        DRDY_R::new((self.bits & 1) != 0)
234    }
235    ///Bit 1 - Clock error current status
236    #[inline(always)]
237    pub fn cecs(&self) -> CECS_R {
238        CECS_R::new(((self.bits >> 1) & 1) != 0)
239    }
240    ///Bit 2 - Seed error current status
241    #[inline(always)]
242    pub fn secs(&self) -> SECS_R {
243        SECS_R::new(((self.bits >> 2) & 1) != 0)
244    }
245    ///Bit 5 - Clock error interrupt status
246    #[inline(always)]
247    pub fn ceis(&self) -> CEIS_R {
248        CEIS_R::new(((self.bits >> 5) & 1) != 0)
249    }
250    ///Bit 6 - Seed error interrupt status
251    #[inline(always)]
252    pub fn seis(&self) -> SEIS_R {
253        SEIS_R::new(((self.bits >> 6) & 1) != 0)
254    }
255}
256impl core::fmt::Debug for R {
257    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
258        f.debug_struct("SR")
259            .field("ceis", &self.ceis())
260            .field("seis", &self.seis())
261            .field("secs", &self.secs())
262            .field("cecs", &self.cecs())
263            .field("drdy", &self.drdy())
264            .finish()
265    }
266}
267impl W {
268    ///Bit 5 - Clock error interrupt status
269    #[inline(always)]
270    pub fn ceis(&mut self) -> CEIS_W<SRrs> {
271        CEIS_W::new(self, 5)
272    }
273    ///Bit 6 - Seed error interrupt status
274    #[inline(always)]
275    pub fn seis(&mut self) -> SEIS_W<SRrs> {
276        SEIS_W::new(self, 6)
277    }
278}
279/**status register
280
281You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
282
283See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#RNG:SR)*/
284pub struct SRrs;
285impl crate::RegisterSpec for SRrs {
286    type Ux = u32;
287}
288///`read()` method returns [`sr::R`](R) reader structure
289impl crate::Readable for SRrs {}
290///`write(|w| ..)` method takes [`sr::W`](W) writer structure
291impl crate::Writable for SRrs {
292    type Safety = crate::Unsafe;
293    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x60;
294}
295///`reset()` method sets SR to value 0
296impl crate::Resettable for SRrs {}
stm32f7_staging/stm32f779/rng/sr.rs

stm32f7_staging/stm32f779/rng/
sr.rs
