stm32f7_staging/stm32f779/lptim1/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**LPTIM Enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ENABLE {
11    ///0: LPTIM is disabled
12    Disabled = 0,
13    ///1: LPTIM is enabled
14    Enabled = 1,
15}
16impl From<ENABLE> for bool {
17    #[inline(always)]
18    fn from(variant: ENABLE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ENABLE` reader - LPTIM Enable
23pub type ENABLE_R = crate::BitReader<ENABLE>;
24impl ENABLE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> ENABLE {
28        match self.bits {
29            false => ENABLE::Disabled,
30            true => ENABLE::Enabled,
31        }
32    }
33    ///LPTIM is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == ENABLE::Disabled
37    }
38    ///LPTIM is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == ENABLE::Enabled
42    }
43}
44///Field `ENABLE` writer - LPTIM Enable
45pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, ENABLE>;
46impl<'a, REG> ENABLE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///LPTIM is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(ENABLE::Disabled)
54    }
55    ///LPTIM is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(ENABLE::Enabled)
59    }
60}
61/**LPTIM start in single mode
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum SNGSTRTW {
67    ///1: LPTIM start in Single mode
68    Start = 1,
69}
70impl From<SNGSTRTW> for bool {
71    #[inline(always)]
72    fn from(variant: SNGSTRTW) -> Self {
73        variant as u8 != 0
74    }
75}
76///Field `SNGSTRT` reader - LPTIM start in single mode
77pub type SNGSTRT_R = crate::BitReader<SNGSTRTW>;
78impl SNGSTRT_R {
79    ///Get enumerated values variant
80    #[inline(always)]
81    pub const fn variant(&self) -> Option<SNGSTRTW> {
82        match self.bits {
83            true => Some(SNGSTRTW::Start),
84            _ => None,
85        }
86    }
87    ///LPTIM start in Single mode
88    #[inline(always)]
89    pub fn is_start(&self) -> bool {
90        *self == SNGSTRTW::Start
91    }
92}
93///Field `SNGSTRT` writer - LPTIM start in single mode
94pub type SNGSTRT_W<'a, REG> = crate::BitWriter<'a, REG, SNGSTRTW>;
95impl<'a, REG> SNGSTRT_W<'a, REG>
96where
97    REG: crate::Writable + crate::RegisterSpec,
98{
99    ///LPTIM start in Single mode
100    #[inline(always)]
101    pub fn start(self) -> &'a mut crate::W<REG> {
102        self.variant(SNGSTRTW::Start)
103    }
104}
105/**Timer start in continuous mode
106
107Value on reset: 0*/
108#[cfg_attr(feature = "defmt", derive(defmt::Format))]
109#[derive(Clone, Copy, Debug, PartialEq, Eq)]
110pub enum CNTSTRTW {
111    ///1: Timer start in Continuous mode
112    Start = 1,
113}
114impl From<CNTSTRTW> for bool {
115    #[inline(always)]
116    fn from(variant: CNTSTRTW) -> Self {
117        variant as u8 != 0
118    }
119}
120///Field `CNTSTRT` reader - Timer start in continuous mode
121pub type CNTSTRT_R = crate::BitReader<CNTSTRTW>;
122impl CNTSTRT_R {
123    ///Get enumerated values variant
124    #[inline(always)]
125    pub const fn variant(&self) -> Option<CNTSTRTW> {
126        match self.bits {
127            true => Some(CNTSTRTW::Start),
128            _ => None,
129        }
130    }
131    ///Timer start in Continuous mode
132    #[inline(always)]
133    pub fn is_start(&self) -> bool {
134        *self == CNTSTRTW::Start
135    }
136}
137///Field `CNTSTRT` writer - Timer start in continuous mode
138pub type CNTSTRT_W<'a, REG> = crate::BitWriter<'a, REG, CNTSTRTW>;
139impl<'a, REG> CNTSTRT_W<'a, REG>
140where
141    REG: crate::Writable + crate::RegisterSpec,
142{
143    ///Timer start in Continuous mode
144    #[inline(always)]
145    pub fn start(self) -> &'a mut crate::W<REG> {
146        self.variant(CNTSTRTW::Start)
147    }
148}
149impl R {
150    ///Bit 0 - LPTIM Enable
151    #[inline(always)]
152    pub fn enable(&self) -> ENABLE_R {
153        ENABLE_R::new((self.bits & 1) != 0)
154    }
155    ///Bit 1 - LPTIM start in single mode
156    #[inline(always)]
157    pub fn sngstrt(&self) -> SNGSTRT_R {
158        SNGSTRT_R::new(((self.bits >> 1) & 1) != 0)
159    }
160    ///Bit 2 - Timer start in continuous mode
161    #[inline(always)]
162    pub fn cntstrt(&self) -> CNTSTRT_R {
163        CNTSTRT_R::new(((self.bits >> 2) & 1) != 0)
164    }
165}
166impl core::fmt::Debug for R {
167    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
168        f.debug_struct("CR")
169            .field("cntstrt", &self.cntstrt())
170            .field("sngstrt", &self.sngstrt())
171            .field("enable", &self.enable())
172            .finish()
173    }
174}
175impl W {
176    ///Bit 0 - LPTIM Enable
177    #[inline(always)]
178    pub fn enable(&mut self) -> ENABLE_W<CRrs> {
179        ENABLE_W::new(self, 0)
180    }
181    ///Bit 1 - LPTIM start in single mode
182    #[inline(always)]
183    pub fn sngstrt(&mut self) -> SNGSTRT_W<CRrs> {
184        SNGSTRT_W::new(self, 1)
185    }
186    ///Bit 2 - Timer start in continuous mode
187    #[inline(always)]
188    pub fn cntstrt(&mut self) -> CNTSTRT_W<CRrs> {
189        CNTSTRT_W::new(self, 2)
190    }
191}
192/**Control Register
193
194You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
195
196See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#LPTIM1:CR)*/
197pub struct CRrs;
198impl crate::RegisterSpec for CRrs {
199    type Ux = u32;
200}
201///`read()` method returns [`cr::R`](R) reader structure
202impl crate::Readable for CRrs {}
203///`write(|w| ..)` method takes [`cr::W`](W) writer structure
204impl crate::Writable for CRrs {
205    type Safety = crate::Unsafe;
206}
207///`reset()` method sets CR to value 0
208impl crate::Resettable for CRrs {}
stm32f7_staging/stm32f779/lptim1/cr.rs

stm32f7_staging/stm32f779/lptim1/
cr.rs
