stm32f7_staging/stm32f779/gpioa/
bsrr.rs

1///Register `BSRR` writer
2pub type W = crate::W<BSRRrs>;
3/**Port x set pin %s
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum BIT_SET {
9    ///1: Sets the corresponding ODRx bit
10    Set = 1,
11}
12impl From<BIT_SET> for bool {
13    #[inline(always)]
14    fn from(variant: BIT_SET) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `BS(0-15)` writer - Port x set pin %s
19pub type BS_W<'a, REG> = crate::BitWriter<'a, REG, BIT_SET>;
20impl<'a, REG> BS_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Sets the corresponding ODRx bit
25    #[inline(always)]
26    pub fn set_(self) -> &'a mut crate::W<REG> {
27        self.variant(BIT_SET::Set)
28    }
29}
30/**Port x reset pin %s
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum BIT_RESET {
36    ///1: Resets the corresponding ODRx bit
37    Reset = 1,
38}
39impl From<BIT_RESET> for bool {
40    #[inline(always)]
41    fn from(variant: BIT_RESET) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `BR(0-15)` writer - Port x reset pin %s
46pub type BR_W<'a, REG> = crate::BitWriter<'a, REG, BIT_RESET>;
47impl<'a, REG> BR_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///Resets the corresponding ODRx bit
52    #[inline(always)]
53    pub fn reset(self) -> &'a mut crate::W<REG> {
54        self.variant(BIT_RESET::Reset)
55    }
56}
57impl core::fmt::Debug for crate::generic::Reg<BSRRrs> {
58    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
59        write!(f, "(not readable)")
60    }
61}
62impl W {
63    ///Port x set pin (0-15)
64    ///
65    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BS0` field.</div>
66    #[inline(always)]
67    pub fn bs(&mut self, n: u8) -> BS_W<BSRRrs> {
68        #[allow(clippy::no_effect)]
69        [(); 16][n as usize];
70        BS_W::new(self, n)
71    }
72    ///Bit 0 - Port x set pin 0
73    #[inline(always)]
74    pub fn bs0(&mut self) -> BS_W<BSRRrs> {
75        BS_W::new(self, 0)
76    }
77    ///Bit 1 - Port x set pin 1
78    #[inline(always)]
79    pub fn bs1(&mut self) -> BS_W<BSRRrs> {
80        BS_W::new(self, 1)
81    }
82    ///Bit 2 - Port x set pin 2
83    #[inline(always)]
84    pub fn bs2(&mut self) -> BS_W<BSRRrs> {
85        BS_W::new(self, 2)
86    }
87    ///Bit 3 - Port x set pin 3
88    #[inline(always)]
89    pub fn bs3(&mut self) -> BS_W<BSRRrs> {
90        BS_W::new(self, 3)
91    }
92    ///Bit 4 - Port x set pin 4
93    #[inline(always)]
94    pub fn bs4(&mut self) -> BS_W<BSRRrs> {
95        BS_W::new(self, 4)
96    }
97    ///Bit 5 - Port x set pin 5
98    #[inline(always)]
99    pub fn bs5(&mut self) -> BS_W<BSRRrs> {
100        BS_W::new(self, 5)
101    }
102    ///Bit 6 - Port x set pin 6
103    #[inline(always)]
104    pub fn bs6(&mut self) -> BS_W<BSRRrs> {
105        BS_W::new(self, 6)
106    }
107    ///Bit 7 - Port x set pin 7
108    #[inline(always)]
109    pub fn bs7(&mut self) -> BS_W<BSRRrs> {
110        BS_W::new(self, 7)
111    }
112    ///Bit 8 - Port x set pin 8
113    #[inline(always)]
114    pub fn bs8(&mut self) -> BS_W<BSRRrs> {
115        BS_W::new(self, 8)
116    }
117    ///Bit 9 - Port x set pin 9
118    #[inline(always)]
119    pub fn bs9(&mut self) -> BS_W<BSRRrs> {
120        BS_W::new(self, 9)
121    }
122    ///Bit 10 - Port x set pin 10
123    #[inline(always)]
124    pub fn bs10(&mut self) -> BS_W<BSRRrs> {
125        BS_W::new(self, 10)
126    }
127    ///Bit 11 - Port x set pin 11
128    #[inline(always)]
129    pub fn bs11(&mut self) -> BS_W<BSRRrs> {
130        BS_W::new(self, 11)
131    }
132    ///Bit 12 - Port x set pin 12
133    #[inline(always)]
134    pub fn bs12(&mut self) -> BS_W<BSRRrs> {
135        BS_W::new(self, 12)
136    }
137    ///Bit 13 - Port x set pin 13
138    #[inline(always)]
139    pub fn bs13(&mut self) -> BS_W<BSRRrs> {
140        BS_W::new(self, 13)
141    }
142    ///Bit 14 - Port x set pin 14
143    #[inline(always)]
144    pub fn bs14(&mut self) -> BS_W<BSRRrs> {
145        BS_W::new(self, 14)
146    }
147    ///Bit 15 - Port x set pin 15
148    #[inline(always)]
149    pub fn bs15(&mut self) -> BS_W<BSRRrs> {
150        BS_W::new(self, 15)
151    }
152    ///Port x reset pin (0-15)
153    ///
154    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BR0` field.</div>
155    #[inline(always)]
156    pub fn br(&mut self, n: u8) -> BR_W<BSRRrs> {
157        #[allow(clippy::no_effect)]
158        [(); 16][n as usize];
159        BR_W::new(self, n + 16)
160    }
161    ///Bit 16 - Port x reset pin 0
162    #[inline(always)]
163    pub fn br0(&mut self) -> BR_W<BSRRrs> {
164        BR_W::new(self, 16)
165    }
166    ///Bit 17 - Port x reset pin 1
167    #[inline(always)]
168    pub fn br1(&mut self) -> BR_W<BSRRrs> {
169        BR_W::new(self, 17)
170    }
171    ///Bit 18 - Port x reset pin 2
172    #[inline(always)]
173    pub fn br2(&mut self) -> BR_W<BSRRrs> {
174        BR_W::new(self, 18)
175    }
176    ///Bit 19 - Port x reset pin 3
177    #[inline(always)]
178    pub fn br3(&mut self) -> BR_W<BSRRrs> {
179        BR_W::new(self, 19)
180    }
181    ///Bit 20 - Port x reset pin 4
182    #[inline(always)]
183    pub fn br4(&mut self) -> BR_W<BSRRrs> {
184        BR_W::new(self, 20)
185    }
186    ///Bit 21 - Port x reset pin 5
187    #[inline(always)]
188    pub fn br5(&mut self) -> BR_W<BSRRrs> {
189        BR_W::new(self, 21)
190    }
191    ///Bit 22 - Port x reset pin 6
192    #[inline(always)]
193    pub fn br6(&mut self) -> BR_W<BSRRrs> {
194        BR_W::new(self, 22)
195    }
196    ///Bit 23 - Port x reset pin 7
197    #[inline(always)]
198    pub fn br7(&mut self) -> BR_W<BSRRrs> {
199        BR_W::new(self, 23)
200    }
201    ///Bit 24 - Port x reset pin 8
202    #[inline(always)]
203    pub fn br8(&mut self) -> BR_W<BSRRrs> {
204        BR_W::new(self, 24)
205    }
206    ///Bit 25 - Port x reset pin 9
207    #[inline(always)]
208    pub fn br9(&mut self) -> BR_W<BSRRrs> {
209        BR_W::new(self, 25)
210    }
211    ///Bit 26 - Port x reset pin 10
212    #[inline(always)]
213    pub fn br10(&mut self) -> BR_W<BSRRrs> {
214        BR_W::new(self, 26)
215    }
216    ///Bit 27 - Port x reset pin 11
217    #[inline(always)]
218    pub fn br11(&mut self) -> BR_W<BSRRrs> {
219        BR_W::new(self, 27)
220    }
221    ///Bit 28 - Port x reset pin 12
222    #[inline(always)]
223    pub fn br12(&mut self) -> BR_W<BSRRrs> {
224        BR_W::new(self, 28)
225    }
226    ///Bit 29 - Port x reset pin 13
227    #[inline(always)]
228    pub fn br13(&mut self) -> BR_W<BSRRrs> {
229        BR_W::new(self, 29)
230    }
231    ///Bit 30 - Port x reset pin 14
232    #[inline(always)]
233    pub fn br14(&mut self) -> BR_W<BSRRrs> {
234        BR_W::new(self, 30)
235    }
236    ///Bit 31 - Port x reset pin 15
237    #[inline(always)]
238    pub fn br15(&mut self) -> BR_W<BSRRrs> {
239        BR_W::new(self, 31)
240    }
241}
242/**GPIO port bit set/reset register
243
244You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bsrr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
245
246See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#GPIOA:BSRR)*/
247pub struct BSRRrs;
248impl crate::RegisterSpec for BSRRrs {
249    type Ux = u32;
250}
251///`write(|w| ..)` method takes [`bsrr::W`](W) writer structure
252impl crate::Writable for BSRRrs {
253    type Safety = crate::Unsafe;
254}
255///`reset()` method sets BSRR to value 0
256impl crate::Resettable for BSRRrs {}
stm32f7_staging/stm32f779/gpioa/bsrr.rs

stm32f7_staging/stm32f779/gpioa/
bsrr.rs
