stm32f7_staging/stm32f779/dsi/
wpcr0.rs

1///Register `WPCR0` reader
2pub type R = crate::R<WPCR0rs>;
3///Register `WPCR0` writer
4pub type W = crate::W<WPCR0rs>;
5///Field `UIX4` reader - Unit Interval multiplied by 4
6pub type UIX4_R = crate::FieldReader;
7///Field `UIX4` writer - Unit Interval multiplied by 4
8pub type UIX4_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9///Field `SWCL` reader - Swap Clock Lane pins
10pub type SWCL_R = crate::BitReader;
11///Field `SWCL` writer - Swap Clock Lane pins
12pub type SWCL_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `SWDL0` reader - Swap Data Lane 0 pins
14pub type SWDL0_R = crate::BitReader;
15///Field `SWDL0` writer - Swap Data Lane 0 pins
16pub type SWDL0_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `SWDL1` reader - Swap Data Lane 1 pins
18pub type SWDL1_R = crate::BitReader;
19///Field `SWDL1` writer - Swap Data Lane 1 pins
20pub type SWDL1_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `HSICL` reader - Invert Hight-Speed data signal on Clock Lane
22pub type HSICL_R = crate::BitReader;
23///Field `HSICL` writer - Invert Hight-Speed data signal on Clock Lane
24pub type HSICL_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `HSIDL0` reader - Invert the Hight-Speed data signal on Data Lane 0
26pub type HSIDL0_R = crate::BitReader;
27///Field `HSIDL0` writer - Invert the Hight-Speed data signal on Data Lane 0
28pub type HSIDL0_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `HSIDL1` reader - Invert the High-Speed data signal on Data Lane 1
30pub type HSIDL1_R = crate::BitReader;
31///Field `HSIDL1` writer - Invert the High-Speed data signal on Data Lane 1
32pub type HSIDL1_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `FTXSMCL` reader - Force in TX Stop Mode the Clock Lane
34pub type FTXSMCL_R = crate::BitReader;
35///Field `FTXSMCL` writer - Force in TX Stop Mode the Clock Lane
36pub type FTXSMCL_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `FTXSMDL` reader - Force in TX Stop Mode the Data Lanes
38pub type FTXSMDL_R = crate::BitReader;
39///Field `FTXSMDL` writer - Force in TX Stop Mode the Data Lanes
40pub type FTXSMDL_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `CDOFFDL` reader - Contention Detection OFF on Data Lanes
42pub type CDOFFDL_R = crate::BitReader;
43///Field `CDOFFDL` writer - Contention Detection OFF on Data Lanes
44pub type CDOFFDL_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `TDDL` reader - Turn Disable Data Lanes
46pub type TDDL_R = crate::BitReader;
47///Field `TDDL` writer - Turn Disable Data Lanes
48pub type TDDL_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `PDEN` reader - Pull-Down Enable
50pub type PDEN_R = crate::BitReader;
51///Field `PDEN` writer - Pull-Down Enable
52pub type PDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `TCLKPREPEN` reader - custom time for tCLK-PREPARE Enable
54pub type TCLKPREPEN_R = crate::BitReader;
55///Field `TCLKPREPEN` writer - custom time for tCLK-PREPARE Enable
56pub type TCLKPREPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `TCLKZEROEN` reader - custom time for tCLK-ZERO Enable
58pub type TCLKZEROEN_R = crate::BitReader;
59///Field `TCLKZEROEN` writer - custom time for tCLK-ZERO Enable
60pub type TCLKZEROEN_W<'a, REG> = crate::BitWriter<'a, REG>;
61///Field `THSPREPEN` reader - custom time for tHS-PREPARE Enable
62pub type THSPREPEN_R = crate::BitReader;
63///Field `THSPREPEN` writer - custom time for tHS-PREPARE Enable
64pub type THSPREPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
65///Field `THSTRAILEN` reader - custom time for tHS-TRAIL Enable
66pub type THSTRAILEN_R = crate::BitReader;
67///Field `THSTRAILEN` writer - custom time for tHS-TRAIL Enable
68pub type THSTRAILEN_W<'a, REG> = crate::BitWriter<'a, REG>;
69///Field `THSZEROEN` reader - custom time for tHS-ZERO Enable
70pub type THSZEROEN_R = crate::BitReader;
71///Field `THSZEROEN` writer - custom time for tHS-ZERO Enable
72pub type THSZEROEN_W<'a, REG> = crate::BitWriter<'a, REG>;
73///Field `TLPXDEN` reader - custom time for tLPX for Data lanes Enable
74pub type TLPXDEN_R = crate::BitReader;
75///Field `TLPXDEN` writer - custom time for tLPX for Data lanes Enable
76pub type TLPXDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
77///Field `THSEXITEN` reader - custom time for tHS-EXIT Enable
78pub type THSEXITEN_R = crate::BitReader;
79///Field `THSEXITEN` writer - custom time for tHS-EXIT Enable
80pub type THSEXITEN_W<'a, REG> = crate::BitWriter<'a, REG>;
81///Field `TLPXCEN` reader - custom time for tLPX for Clock lane Enable
82pub type TLPXCEN_R = crate::BitReader;
83///Field `TLPXCEN` writer - custom time for tLPX for Clock lane Enable
84pub type TLPXCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
85///Field `TCLKPOSTEN` reader - custom time for tCLK-POST Enable
86pub type TCLKPOSTEN_R = crate::BitReader;
87///Field `TCLKPOSTEN` writer - custom time for tCLK-POST Enable
88pub type TCLKPOSTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
89impl R {
90    ///Bits 0:5 - Unit Interval multiplied by 4
91    #[inline(always)]
92    pub fn uix4(&self) -> UIX4_R {
93        UIX4_R::new((self.bits & 0x3f) as u8)
94    }
95    ///Bit 6 - Swap Clock Lane pins
96    #[inline(always)]
97    pub fn swcl(&self) -> SWCL_R {
98        SWCL_R::new(((self.bits >> 6) & 1) != 0)
99    }
100    ///Bit 7 - Swap Data Lane 0 pins
101    #[inline(always)]
102    pub fn swdl0(&self) -> SWDL0_R {
103        SWDL0_R::new(((self.bits >> 7) & 1) != 0)
104    }
105    ///Bit 8 - Swap Data Lane 1 pins
106    #[inline(always)]
107    pub fn swdl1(&self) -> SWDL1_R {
108        SWDL1_R::new(((self.bits >> 8) & 1) != 0)
109    }
110    ///Bit 9 - Invert Hight-Speed data signal on Clock Lane
111    #[inline(always)]
112    pub fn hsicl(&self) -> HSICL_R {
113        HSICL_R::new(((self.bits >> 9) & 1) != 0)
114    }
115    ///Bit 10 - Invert the Hight-Speed data signal on Data Lane 0
116    #[inline(always)]
117    pub fn hsidl0(&self) -> HSIDL0_R {
118        HSIDL0_R::new(((self.bits >> 10) & 1) != 0)
119    }
120    ///Bit 11 - Invert the High-Speed data signal on Data Lane 1
121    #[inline(always)]
122    pub fn hsidl1(&self) -> HSIDL1_R {
123        HSIDL1_R::new(((self.bits >> 11) & 1) != 0)
124    }
125    ///Bit 12 - Force in TX Stop Mode the Clock Lane
126    #[inline(always)]
127    pub fn ftxsmcl(&self) -> FTXSMCL_R {
128        FTXSMCL_R::new(((self.bits >> 12) & 1) != 0)
129    }
130    ///Bit 13 - Force in TX Stop Mode the Data Lanes
131    #[inline(always)]
132    pub fn ftxsmdl(&self) -> FTXSMDL_R {
133        FTXSMDL_R::new(((self.bits >> 13) & 1) != 0)
134    }
135    ///Bit 14 - Contention Detection OFF on Data Lanes
136    #[inline(always)]
137    pub fn cdoffdl(&self) -> CDOFFDL_R {
138        CDOFFDL_R::new(((self.bits >> 14) & 1) != 0)
139    }
140    ///Bit 16 - Turn Disable Data Lanes
141    #[inline(always)]
142    pub fn tddl(&self) -> TDDL_R {
143        TDDL_R::new(((self.bits >> 16) & 1) != 0)
144    }
145    ///Bit 18 - Pull-Down Enable
146    #[inline(always)]
147    pub fn pden(&self) -> PDEN_R {
148        PDEN_R::new(((self.bits >> 18) & 1) != 0)
149    }
150    ///Bit 19 - custom time for tCLK-PREPARE Enable
151    #[inline(always)]
152    pub fn tclkprepen(&self) -> TCLKPREPEN_R {
153        TCLKPREPEN_R::new(((self.bits >> 19) & 1) != 0)
154    }
155    ///Bit 20 - custom time for tCLK-ZERO Enable
156    #[inline(always)]
157    pub fn tclkzeroen(&self) -> TCLKZEROEN_R {
158        TCLKZEROEN_R::new(((self.bits >> 20) & 1) != 0)
159    }
160    ///Bit 21 - custom time for tHS-PREPARE Enable
161    #[inline(always)]
162    pub fn thsprepen(&self) -> THSPREPEN_R {
163        THSPREPEN_R::new(((self.bits >> 21) & 1) != 0)
164    }
165    ///Bit 22 - custom time for tHS-TRAIL Enable
166    #[inline(always)]
167    pub fn thstrailen(&self) -> THSTRAILEN_R {
168        THSTRAILEN_R::new(((self.bits >> 22) & 1) != 0)
169    }
170    ///Bit 23 - custom time for tHS-ZERO Enable
171    #[inline(always)]
172    pub fn thszeroen(&self) -> THSZEROEN_R {
173        THSZEROEN_R::new(((self.bits >> 23) & 1) != 0)
174    }
175    ///Bit 24 - custom time for tLPX for Data lanes Enable
176    #[inline(always)]
177    pub fn tlpxden(&self) -> TLPXDEN_R {
178        TLPXDEN_R::new(((self.bits >> 24) & 1) != 0)
179    }
180    ///Bit 25 - custom time for tHS-EXIT Enable
181    #[inline(always)]
182    pub fn thsexiten(&self) -> THSEXITEN_R {
183        THSEXITEN_R::new(((self.bits >> 25) & 1) != 0)
184    }
185    ///Bit 26 - custom time for tLPX for Clock lane Enable
186    #[inline(always)]
187    pub fn tlpxcen(&self) -> TLPXCEN_R {
188        TLPXCEN_R::new(((self.bits >> 26) & 1) != 0)
189    }
190    ///Bit 27 - custom time for tCLK-POST Enable
191    #[inline(always)]
192    pub fn tclkposten(&self) -> TCLKPOSTEN_R {
193        TCLKPOSTEN_R::new(((self.bits >> 27) & 1) != 0)
194    }
195}
196impl core::fmt::Debug for R {
197    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
198        f.debug_struct("WPCR0")
199            .field("tclkposten", &self.tclkposten())
200            .field("tlpxcen", &self.tlpxcen())
201            .field("thsexiten", &self.thsexiten())
202            .field("tlpxden", &self.tlpxden())
203            .field("thszeroen", &self.thszeroen())
204            .field("thstrailen", &self.thstrailen())
205            .field("thsprepen", &self.thsprepen())
206            .field("tclkzeroen", &self.tclkzeroen())
207            .field("tclkprepen", &self.tclkprepen())
208            .field("pden", &self.pden())
209            .field("tddl", &self.tddl())
210            .field("cdoffdl", &self.cdoffdl())
211            .field("ftxsmdl", &self.ftxsmdl())
212            .field("ftxsmcl", &self.ftxsmcl())
213            .field("hsidl1", &self.hsidl1())
214            .field("hsidl0", &self.hsidl0())
215            .field("hsicl", &self.hsicl())
216            .field("swdl1", &self.swdl1())
217            .field("swdl0", &self.swdl0())
218            .field("swcl", &self.swcl())
219            .field("uix4", &self.uix4())
220            .finish()
221    }
222}
223impl W {
224    ///Bits 0:5 - Unit Interval multiplied by 4
225    #[inline(always)]
226    pub fn uix4(&mut self) -> UIX4_W<WPCR0rs> {
227        UIX4_W::new(self, 0)
228    }
229    ///Bit 6 - Swap Clock Lane pins
230    #[inline(always)]
231    pub fn swcl(&mut self) -> SWCL_W<WPCR0rs> {
232        SWCL_W::new(self, 6)
233    }
234    ///Bit 7 - Swap Data Lane 0 pins
235    #[inline(always)]
236    pub fn swdl0(&mut self) -> SWDL0_W<WPCR0rs> {
237        SWDL0_W::new(self, 7)
238    }
239    ///Bit 8 - Swap Data Lane 1 pins
240    #[inline(always)]
241    pub fn swdl1(&mut self) -> SWDL1_W<WPCR0rs> {
242        SWDL1_W::new(self, 8)
243    }
244    ///Bit 9 - Invert Hight-Speed data signal on Clock Lane
245    #[inline(always)]
246    pub fn hsicl(&mut self) -> HSICL_W<WPCR0rs> {
247        HSICL_W::new(self, 9)
248    }
249    ///Bit 10 - Invert the Hight-Speed data signal on Data Lane 0
250    #[inline(always)]
251    pub fn hsidl0(&mut self) -> HSIDL0_W<WPCR0rs> {
252        HSIDL0_W::new(self, 10)
253    }
254    ///Bit 11 - Invert the High-Speed data signal on Data Lane 1
255    #[inline(always)]
256    pub fn hsidl1(&mut self) -> HSIDL1_W<WPCR0rs> {
257        HSIDL1_W::new(self, 11)
258    }
259    ///Bit 12 - Force in TX Stop Mode the Clock Lane
260    #[inline(always)]
261    pub fn ftxsmcl(&mut self) -> FTXSMCL_W<WPCR0rs> {
262        FTXSMCL_W::new(self, 12)
263    }
264    ///Bit 13 - Force in TX Stop Mode the Data Lanes
265    #[inline(always)]
266    pub fn ftxsmdl(&mut self) -> FTXSMDL_W<WPCR0rs> {
267        FTXSMDL_W::new(self, 13)
268    }
269    ///Bit 14 - Contention Detection OFF on Data Lanes
270    #[inline(always)]
271    pub fn cdoffdl(&mut self) -> CDOFFDL_W<WPCR0rs> {
272        CDOFFDL_W::new(self, 14)
273    }
274    ///Bit 16 - Turn Disable Data Lanes
275    #[inline(always)]
276    pub fn tddl(&mut self) -> TDDL_W<WPCR0rs> {
277        TDDL_W::new(self, 16)
278    }
279    ///Bit 18 - Pull-Down Enable
280    #[inline(always)]
281    pub fn pden(&mut self) -> PDEN_W<WPCR0rs> {
282        PDEN_W::new(self, 18)
283    }
284    ///Bit 19 - custom time for tCLK-PREPARE Enable
285    #[inline(always)]
286    pub fn tclkprepen(&mut self) -> TCLKPREPEN_W<WPCR0rs> {
287        TCLKPREPEN_W::new(self, 19)
288    }
289    ///Bit 20 - custom time for tCLK-ZERO Enable
290    #[inline(always)]
291    pub fn tclkzeroen(&mut self) -> TCLKZEROEN_W<WPCR0rs> {
292        TCLKZEROEN_W::new(self, 20)
293    }
294    ///Bit 21 - custom time for tHS-PREPARE Enable
295    #[inline(always)]
296    pub fn thsprepen(&mut self) -> THSPREPEN_W<WPCR0rs> {
297        THSPREPEN_W::new(self, 21)
298    }
299    ///Bit 22 - custom time for tHS-TRAIL Enable
300    #[inline(always)]
301    pub fn thstrailen(&mut self) -> THSTRAILEN_W<WPCR0rs> {
302        THSTRAILEN_W::new(self, 22)
303    }
304    ///Bit 23 - custom time for tHS-ZERO Enable
305    #[inline(always)]
306    pub fn thszeroen(&mut self) -> THSZEROEN_W<WPCR0rs> {
307        THSZEROEN_W::new(self, 23)
308    }
309    ///Bit 24 - custom time for tLPX for Data lanes Enable
310    #[inline(always)]
311    pub fn tlpxden(&mut self) -> TLPXDEN_W<WPCR0rs> {
312        TLPXDEN_W::new(self, 24)
313    }
314    ///Bit 25 - custom time for tHS-EXIT Enable
315    #[inline(always)]
316    pub fn thsexiten(&mut self) -> THSEXITEN_W<WPCR0rs> {
317        THSEXITEN_W::new(self, 25)
318    }
319    ///Bit 26 - custom time for tLPX for Clock lane Enable
320    #[inline(always)]
321    pub fn tlpxcen(&mut self) -> TLPXCEN_W<WPCR0rs> {
322        TLPXCEN_W::new(self, 26)
323    }
324    ///Bit 27 - custom time for tCLK-POST Enable
325    #[inline(always)]
326    pub fn tclkposten(&mut self) -> TCLKPOSTEN_W<WPCR0rs> {
327        TCLKPOSTEN_W::new(self, 27)
328    }
329}
330/**DSI Wrapper PHY Configuration Register 1
331
332You can [`read`](crate::Reg::read) this register and get [`wpcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
333
334See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:WPCR0)*/
335pub struct WPCR0rs;
336impl crate::RegisterSpec for WPCR0rs {
337    type Ux = u32;
338}
339///`read()` method returns [`wpcr0::R`](R) reader structure
340impl crate::Readable for WPCR0rs {}
341///`write(|w| ..)` method takes [`wpcr0::W`](W) writer structure
342impl crate::Writable for WPCR0rs {
343    type Safety = crate::Unsafe;
344}
345///`reset()` method sets WPCR0 to value 0
346impl crate::Resettable for WPCR0rs {}
stm32f7_staging/stm32f779/dsi/wpcr0.rs

stm32f7_staging/stm32f779/dsi/
wpcr0.rs
