stm32f7_staging/stm32f779/dsi/
psr.rs

1///Register `PSR` reader
2pub type R = crate::R<PSRrs>;
3///Field `PD` reader - PHY Direction
4pub type PD_R = crate::BitReader;
5///Field `PSSC` reader - PHY Stop State Clock lane
6pub type PSSC_R = crate::BitReader;
7///Field `UANC` reader - ULPS Active Not Clock lane
8pub type UANC_R = crate::BitReader;
9///Field `PSS0` reader - PHY Stop State lane 0
10pub type PSS0_R = crate::BitReader;
11///Field `UAN0` reader - ULPS Active Not lane 1
12pub type UAN0_R = crate::BitReader;
13///Field `RUE0` reader - RX ULPS Escape lane 0
14pub type RUE0_R = crate::BitReader;
15///Field `PSS1` reader - PHY Stop State lane 1
16pub type PSS1_R = crate::BitReader;
17///Field `UAN1` reader - ULPS Active Not lane 1
18pub type UAN1_R = crate::BitReader;
19impl R {
20    ///Bit 1 - PHY Direction
21    #[inline(always)]
22    pub fn pd(&self) -> PD_R {
23        PD_R::new(((self.bits >> 1) & 1) != 0)
24    }
25    ///Bit 2 - PHY Stop State Clock lane
26    #[inline(always)]
27    pub fn pssc(&self) -> PSSC_R {
28        PSSC_R::new(((self.bits >> 2) & 1) != 0)
29    }
30    ///Bit 3 - ULPS Active Not Clock lane
31    #[inline(always)]
32    pub fn uanc(&self) -> UANC_R {
33        UANC_R::new(((self.bits >> 3) & 1) != 0)
34    }
35    ///Bit 4 - PHY Stop State lane 0
36    #[inline(always)]
37    pub fn pss0(&self) -> PSS0_R {
38        PSS0_R::new(((self.bits >> 4) & 1) != 0)
39    }
40    ///Bit 5 - ULPS Active Not lane 1
41    #[inline(always)]
42    pub fn uan0(&self) -> UAN0_R {
43        UAN0_R::new(((self.bits >> 5) & 1) != 0)
44    }
45    ///Bit 6 - RX ULPS Escape lane 0
46    #[inline(always)]
47    pub fn rue0(&self) -> RUE0_R {
48        RUE0_R::new(((self.bits >> 6) & 1) != 0)
49    }
50    ///Bit 7 - PHY Stop State lane 1
51    #[inline(always)]
52    pub fn pss1(&self) -> PSS1_R {
53        PSS1_R::new(((self.bits >> 7) & 1) != 0)
54    }
55    ///Bit 8 - ULPS Active Not lane 1
56    #[inline(always)]
57    pub fn uan1(&self) -> UAN1_R {
58        UAN1_R::new(((self.bits >> 8) & 1) != 0)
59    }
60}
61impl core::fmt::Debug for R {
62    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
63        f.debug_struct("PSR")
64            .field("pd", &self.pd())
65            .field("pssc", &self.pssc())
66            .field("uanc", &self.uanc())
67            .field("pss0", &self.pss0())
68            .field("uan0", &self.uan0())
69            .field("rue0", &self.rue0())
70            .field("pss1", &self.pss1())
71            .field("uan1", &self.uan1())
72            .finish()
73    }
74}
75/**DSI Host PHY Status Register
76
77You can [`read`](crate::Reg::read) this register and get [`psr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:PSR)*/
80pub struct PSRrs;
81impl crate::RegisterSpec for PSRrs {
82    type Ux = u32;
83}
84///`read()` method returns [`psr::R`](R) reader structure
85impl crate::Readable for PSRrs {}
86///`reset()` method sets PSR to value 0
87impl crate::Resettable for PSRrs {}
stm32f7_staging/stm32f779/dsi/psr.rs

stm32f7_staging/stm32f779/dsi/
psr.rs
