stm32f7_staging/stm32f779/dsi/
lpcr.rs

1///Register `LPCR` reader
2pub type R = crate::R<LPCRrs>;
3///Register `LPCR` writer
4pub type W = crate::W<LPCRrs>;
5///Field `DEP` reader - Data Enable Polarity
6pub type DEP_R = crate::BitReader;
7///Field `DEP` writer - Data Enable Polarity
8pub type DEP_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `VSP` reader - VSYNC Polarity
10pub type VSP_R = crate::BitReader;
11///Field `VSP` writer - VSYNC Polarity
12pub type VSP_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `HSP` reader - HSYNC Polarity
14pub type HSP_R = crate::BitReader;
15///Field `HSP` writer - HSYNC Polarity
16pub type HSP_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    ///Bit 0 - Data Enable Polarity
19    #[inline(always)]
20    pub fn dep(&self) -> DEP_R {
21        DEP_R::new((self.bits & 1) != 0)
22    }
23    ///Bit 1 - VSYNC Polarity
24    #[inline(always)]
25    pub fn vsp(&self) -> VSP_R {
26        VSP_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    ///Bit 2 - HSYNC Polarity
29    #[inline(always)]
30    pub fn hsp(&self) -> HSP_R {
31        HSP_R::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("LPCR")
37            .field("dep", &self.dep())
38            .field("vsp", &self.vsp())
39            .field("hsp", &self.hsp())
40            .finish()
41    }
42}
43impl W {
44    ///Bit 0 - Data Enable Polarity
45    #[inline(always)]
46    pub fn dep(&mut self) -> DEP_W<LPCRrs> {
47        DEP_W::new(self, 0)
48    }
49    ///Bit 1 - VSYNC Polarity
50    #[inline(always)]
51    pub fn vsp(&mut self) -> VSP_W<LPCRrs> {
52        VSP_W::new(self, 1)
53    }
54    ///Bit 2 - HSYNC Polarity
55    #[inline(always)]
56    pub fn hsp(&mut self) -> HSP_W<LPCRrs> {
57        HSP_W::new(self, 2)
58    }
59}
60/**DSI Host LTDC Polarity Configuration Register
61
62You can [`read`](crate::Reg::read) this register and get [`lpcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:LPCR)*/
65pub struct LPCRrs;
66impl crate::RegisterSpec for LPCRrs {
67    type Ux = u32;
68}
69///`read()` method returns [`lpcr::R`](R) reader structure
70impl crate::Readable for LPCRrs {}
71///`write(|w| ..)` method takes [`lpcr::W`](W) writer structure
72impl crate::Writable for LPCRrs {
73    type Safety = crate::Unsafe;
74}
75///`reset()` method sets LPCR to value 0
76impl crate::Resettable for LPCRrs {}
stm32f7_staging/stm32f779/dsi/lpcr.rs

stm32f7_staging/stm32f779/dsi/
lpcr.rs
