stm32f7_staging/stm32f779/dsi/
ghcr.rs

1///Register `GHCR` reader
2pub type R = crate::R<GHCRrs>;
3///Register `GHCR` writer
4pub type W = crate::W<GHCRrs>;
5///Field `DT` reader - Type
6pub type DT_R = crate::FieldReader;
7///Field `DT` writer - Type
8pub type DT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9///Field `VCID` reader - Channel
10pub type VCID_R = crate::FieldReader;
11///Field `VCID` writer - Channel
12pub type VCID_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13///Field `WCLSB` reader - WordCount LSB
14pub type WCLSB_R = crate::FieldReader;
15///Field `WCLSB` writer - WordCount LSB
16pub type WCLSB_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17///Field `WCMSB` reader - WordCount MSB
18pub type WCMSB_R = crate::FieldReader;
19///Field `WCMSB` writer - WordCount MSB
20pub type WCMSB_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21impl R {
22    ///Bits 0:5 - Type
23    #[inline(always)]
24    pub fn dt(&self) -> DT_R {
25        DT_R::new((self.bits & 0x3f) as u8)
26    }
27    ///Bits 6:7 - Channel
28    #[inline(always)]
29    pub fn vcid(&self) -> VCID_R {
30        VCID_R::new(((self.bits >> 6) & 3) as u8)
31    }
32    ///Bits 8:15 - WordCount LSB
33    #[inline(always)]
34    pub fn wclsb(&self) -> WCLSB_R {
35        WCLSB_R::new(((self.bits >> 8) & 0xff) as u8)
36    }
37    ///Bits 16:23 - WordCount MSB
38    #[inline(always)]
39    pub fn wcmsb(&self) -> WCMSB_R {
40        WCMSB_R::new(((self.bits >> 16) & 0xff) as u8)
41    }
42}
43impl core::fmt::Debug for R {
44    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45        f.debug_struct("GHCR")
46            .field("dt", &self.dt())
47            .field("vcid", &self.vcid())
48            .field("wclsb", &self.wclsb())
49            .field("wcmsb", &self.wcmsb())
50            .finish()
51    }
52}
53impl W {
54    ///Bits 0:5 - Type
55    #[inline(always)]
56    pub fn dt(&mut self) -> DT_W<GHCRrs> {
57        DT_W::new(self, 0)
58    }
59    ///Bits 6:7 - Channel
60    #[inline(always)]
61    pub fn vcid(&mut self) -> VCID_W<GHCRrs> {
62        VCID_W::new(self, 6)
63    }
64    ///Bits 8:15 - WordCount LSB
65    #[inline(always)]
66    pub fn wclsb(&mut self) -> WCLSB_W<GHCRrs> {
67        WCLSB_W::new(self, 8)
68    }
69    ///Bits 16:23 - WordCount MSB
70    #[inline(always)]
71    pub fn wcmsb(&mut self) -> WCMSB_W<GHCRrs> {
72        WCMSB_W::new(self, 16)
73    }
74}
75/**DSI Host Generic Header Configuration Register
76
77You can [`read`](crate::Reg::read) this register and get [`ghcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ghcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:GHCR)*/
80pub struct GHCRrs;
81impl crate::RegisterSpec for GHCRrs {
82    type Ux = u32;
83}
84///`read()` method returns [`ghcr::R`](R) reader structure
85impl crate::Readable for GHCRrs {}
86///`write(|w| ..)` method takes [`ghcr::W`](W) writer structure
87impl crate::Writable for GHCRrs {
88    type Safety = crate::Unsafe;
89}
90///`reset()` method sets GHCR to value 0
91impl crate::Resettable for GHCRrs {}
stm32f7_staging/stm32f779/dsi/ghcr.rs

stm32f7_staging/stm32f779/dsi/
ghcr.rs
