stm32f7_staging/stm32f779/dsi/
cmcr.rs

1///Register `CMCR` reader
2pub type R = crate::R<CMCRrs>;
3///Register `CMCR` writer
4pub type W = crate::W<CMCRrs>;
5///Field `TEARE` reader - Tearing Effect Acknowledge Request Enable
6pub type TEARE_R = crate::BitReader;
7///Field `TEARE` writer - Tearing Effect Acknowledge Request Enable
8pub type TEARE_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `ARE` reader - Acknowledge Request Enable
10pub type ARE_R = crate::BitReader;
11///Field `ARE` writer - Acknowledge Request Enable
12pub type ARE_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `GSW0TX` reader - Generic Short Write Zero parameters Transmission
14pub type GSW0TX_R = crate::BitReader;
15///Field `GSW0TX` writer - Generic Short Write Zero parameters Transmission
16pub type GSW0TX_W<'a, REG> = crate::BitWriter<'a, REG>;
17///Field `GSW1TX` reader - Generic Short Write One parameters Transmission
18pub type GSW1TX_R = crate::BitReader;
19///Field `GSW1TX` writer - Generic Short Write One parameters Transmission
20pub type GSW1TX_W<'a, REG> = crate::BitWriter<'a, REG>;
21///Field `GSW2TX` reader - Generic Short Write Two parameters Transmission
22pub type GSW2TX_R = crate::BitReader;
23///Field `GSW2TX` writer - Generic Short Write Two parameters Transmission
24pub type GSW2TX_W<'a, REG> = crate::BitWriter<'a, REG>;
25///Field `GSR0TX` reader - Generic Short Read Zero parameters Transmission
26pub type GSR0TX_R = crate::BitReader;
27///Field `GSR0TX` writer - Generic Short Read Zero parameters Transmission
28pub type GSR0TX_W<'a, REG> = crate::BitWriter<'a, REG>;
29///Field `GSR1TX` reader - Generic Short Read One parameters Transmission
30pub type GSR1TX_R = crate::BitReader;
31///Field `GSR1TX` writer - Generic Short Read One parameters Transmission
32pub type GSR1TX_W<'a, REG> = crate::BitWriter<'a, REG>;
33///Field `GSR2TX` reader - Generic Short Read Two parameters Transmission
34pub type GSR2TX_R = crate::BitReader;
35///Field `GSR2TX` writer - Generic Short Read Two parameters Transmission
36pub type GSR2TX_W<'a, REG> = crate::BitWriter<'a, REG>;
37///Field `GLWTX` reader - Generic Long Write Transmission
38pub type GLWTX_R = crate::BitReader;
39///Field `GLWTX` writer - Generic Long Write Transmission
40pub type GLWTX_W<'a, REG> = crate::BitWriter<'a, REG>;
41///Field `DSW0TX` reader - DCS Short Write Zero parameter Transmission
42pub type DSW0TX_R = crate::BitReader;
43///Field `DSW0TX` writer - DCS Short Write Zero parameter Transmission
44pub type DSW0TX_W<'a, REG> = crate::BitWriter<'a, REG>;
45///Field `DSW1TX` reader - DCS Short Read One parameter Transmission
46pub type DSW1TX_R = crate::BitReader;
47///Field `DSW1TX` writer - DCS Short Read One parameter Transmission
48pub type DSW1TX_W<'a, REG> = crate::BitWriter<'a, REG>;
49///Field `DSR0TX` reader - DCS Short Read Zero parameter Transmission
50pub type DSR0TX_R = crate::BitReader;
51///Field `DSR0TX` writer - DCS Short Read Zero parameter Transmission
52pub type DSR0TX_W<'a, REG> = crate::BitWriter<'a, REG>;
53///Field `DLWTX` reader - DCS Long Write Transmission
54pub type DLWTX_R = crate::BitReader;
55///Field `DLWTX` writer - DCS Long Write Transmission
56pub type DLWTX_W<'a, REG> = crate::BitWriter<'a, REG>;
57///Field `MRDPS` reader - Maximum Read Packet Size
58pub type MRDPS_R = crate::BitReader;
59///Field `MRDPS` writer - Maximum Read Packet Size
60pub type MRDPS_W<'a, REG> = crate::BitWriter<'a, REG>;
61impl R {
62    ///Bit 0 - Tearing Effect Acknowledge Request Enable
63    #[inline(always)]
64    pub fn teare(&self) -> TEARE_R {
65        TEARE_R::new((self.bits & 1) != 0)
66    }
67    ///Bit 1 - Acknowledge Request Enable
68    #[inline(always)]
69    pub fn are(&self) -> ARE_R {
70        ARE_R::new(((self.bits >> 1) & 1) != 0)
71    }
72    ///Bit 8 - Generic Short Write Zero parameters Transmission
73    #[inline(always)]
74    pub fn gsw0tx(&self) -> GSW0TX_R {
75        GSW0TX_R::new(((self.bits >> 8) & 1) != 0)
76    }
77    ///Bit 9 - Generic Short Write One parameters Transmission
78    #[inline(always)]
79    pub fn gsw1tx(&self) -> GSW1TX_R {
80        GSW1TX_R::new(((self.bits >> 9) & 1) != 0)
81    }
82    ///Bit 10 - Generic Short Write Two parameters Transmission
83    #[inline(always)]
84    pub fn gsw2tx(&self) -> GSW2TX_R {
85        GSW2TX_R::new(((self.bits >> 10) & 1) != 0)
86    }
87    ///Bit 11 - Generic Short Read Zero parameters Transmission
88    #[inline(always)]
89    pub fn gsr0tx(&self) -> GSR0TX_R {
90        GSR0TX_R::new(((self.bits >> 11) & 1) != 0)
91    }
92    ///Bit 12 - Generic Short Read One parameters Transmission
93    #[inline(always)]
94    pub fn gsr1tx(&self) -> GSR1TX_R {
95        GSR1TX_R::new(((self.bits >> 12) & 1) != 0)
96    }
97    ///Bit 13 - Generic Short Read Two parameters Transmission
98    #[inline(always)]
99    pub fn gsr2tx(&self) -> GSR2TX_R {
100        GSR2TX_R::new(((self.bits >> 13) & 1) != 0)
101    }
102    ///Bit 14 - Generic Long Write Transmission
103    #[inline(always)]
104    pub fn glwtx(&self) -> GLWTX_R {
105        GLWTX_R::new(((self.bits >> 14) & 1) != 0)
106    }
107    ///Bit 16 - DCS Short Write Zero parameter Transmission
108    #[inline(always)]
109    pub fn dsw0tx(&self) -> DSW0TX_R {
110        DSW0TX_R::new(((self.bits >> 16) & 1) != 0)
111    }
112    ///Bit 17 - DCS Short Read One parameter Transmission
113    #[inline(always)]
114    pub fn dsw1tx(&self) -> DSW1TX_R {
115        DSW1TX_R::new(((self.bits >> 17) & 1) != 0)
116    }
117    ///Bit 18 - DCS Short Read Zero parameter Transmission
118    #[inline(always)]
119    pub fn dsr0tx(&self) -> DSR0TX_R {
120        DSR0TX_R::new(((self.bits >> 18) & 1) != 0)
121    }
122    ///Bit 19 - DCS Long Write Transmission
123    #[inline(always)]
124    pub fn dlwtx(&self) -> DLWTX_R {
125        DLWTX_R::new(((self.bits >> 19) & 1) != 0)
126    }
127    ///Bit 24 - Maximum Read Packet Size
128    #[inline(always)]
129    pub fn mrdps(&self) -> MRDPS_R {
130        MRDPS_R::new(((self.bits >> 24) & 1) != 0)
131    }
132}
133impl core::fmt::Debug for R {
134    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
135        f.debug_struct("CMCR")
136            .field("teare", &self.teare())
137            .field("are", &self.are())
138            .field("gsw0tx", &self.gsw0tx())
139            .field("gsw1tx", &self.gsw1tx())
140            .field("gsw2tx", &self.gsw2tx())
141            .field("gsr0tx", &self.gsr0tx())
142            .field("gsr1tx", &self.gsr1tx())
143            .field("gsr2tx", &self.gsr2tx())
144            .field("glwtx", &self.glwtx())
145            .field("dsw0tx", &self.dsw0tx())
146            .field("dsw1tx", &self.dsw1tx())
147            .field("dsr0tx", &self.dsr0tx())
148            .field("dlwtx", &self.dlwtx())
149            .field("mrdps", &self.mrdps())
150            .finish()
151    }
152}
153impl W {
154    ///Bit 0 - Tearing Effect Acknowledge Request Enable
155    #[inline(always)]
156    pub fn teare(&mut self) -> TEARE_W<CMCRrs> {
157        TEARE_W::new(self, 0)
158    }
159    ///Bit 1 - Acknowledge Request Enable
160    #[inline(always)]
161    pub fn are(&mut self) -> ARE_W<CMCRrs> {
162        ARE_W::new(self, 1)
163    }
164    ///Bit 8 - Generic Short Write Zero parameters Transmission
165    #[inline(always)]
166    pub fn gsw0tx(&mut self) -> GSW0TX_W<CMCRrs> {
167        GSW0TX_W::new(self, 8)
168    }
169    ///Bit 9 - Generic Short Write One parameters Transmission
170    #[inline(always)]
171    pub fn gsw1tx(&mut self) -> GSW1TX_W<CMCRrs> {
172        GSW1TX_W::new(self, 9)
173    }
174    ///Bit 10 - Generic Short Write Two parameters Transmission
175    #[inline(always)]
176    pub fn gsw2tx(&mut self) -> GSW2TX_W<CMCRrs> {
177        GSW2TX_W::new(self, 10)
178    }
179    ///Bit 11 - Generic Short Read Zero parameters Transmission
180    #[inline(always)]
181    pub fn gsr0tx(&mut self) -> GSR0TX_W<CMCRrs> {
182        GSR0TX_W::new(self, 11)
183    }
184    ///Bit 12 - Generic Short Read One parameters Transmission
185    #[inline(always)]
186    pub fn gsr1tx(&mut self) -> GSR1TX_W<CMCRrs> {
187        GSR1TX_W::new(self, 12)
188    }
189    ///Bit 13 - Generic Short Read Two parameters Transmission
190    #[inline(always)]
191    pub fn gsr2tx(&mut self) -> GSR2TX_W<CMCRrs> {
192        GSR2TX_W::new(self, 13)
193    }
194    ///Bit 14 - Generic Long Write Transmission
195    #[inline(always)]
196    pub fn glwtx(&mut self) -> GLWTX_W<CMCRrs> {
197        GLWTX_W::new(self, 14)
198    }
199    ///Bit 16 - DCS Short Write Zero parameter Transmission
200    #[inline(always)]
201    pub fn dsw0tx(&mut self) -> DSW0TX_W<CMCRrs> {
202        DSW0TX_W::new(self, 16)
203    }
204    ///Bit 17 - DCS Short Read One parameter Transmission
205    #[inline(always)]
206    pub fn dsw1tx(&mut self) -> DSW1TX_W<CMCRrs> {
207        DSW1TX_W::new(self, 17)
208    }
209    ///Bit 18 - DCS Short Read Zero parameter Transmission
210    #[inline(always)]
211    pub fn dsr0tx(&mut self) -> DSR0TX_W<CMCRrs> {
212        DSR0TX_W::new(self, 18)
213    }
214    ///Bit 19 - DCS Long Write Transmission
215    #[inline(always)]
216    pub fn dlwtx(&mut self) -> DLWTX_W<CMCRrs> {
217        DLWTX_W::new(self, 19)
218    }
219    ///Bit 24 - Maximum Read Packet Size
220    #[inline(always)]
221    pub fn mrdps(&mut self) -> MRDPS_W<CMCRrs> {
222        MRDPS_W::new(self, 24)
223    }
224}
225/**DSI Host Command mode Configuration Register
226
227You can [`read`](crate::Reg::read) this register and get [`cmcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
228
229See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DSI:CMCR)*/
230pub struct CMCRrs;
231impl crate::RegisterSpec for CMCRrs {
232    type Ux = u32;
233}
234///`read()` method returns [`cmcr::R`](R) reader structure
235impl crate::Readable for CMCRrs {}
236///`write(|w| ..)` method takes [`cmcr::W`](W) writer structure
237impl crate::Writable for CMCRrs {
238    type Safety = crate::Unsafe;
239}
240///`reset()` method sets CMCR to value 0
241impl crate::Resettable for CMCRrs {}
stm32f7_staging/stm32f779/dsi/cmcr.rs

stm32f7_staging/stm32f779/dsi/
cmcr.rs
