stm32f7_staging/stm32f779/dcmi/
ris.rs

1///Register `RIS` reader
2pub type R = crate::R<RISrs>;
3/**Capture complete raw interrupt status
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum FRAME_RIS {
9    ///0: No new capture
10    NoNewCapture = 0,
11    ///1: A frame has been captured
12    FrameCaptured = 1,
13}
14impl From<FRAME_RIS> for bool {
15    #[inline(always)]
16    fn from(variant: FRAME_RIS) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `FRAME_RIS` reader - Capture complete raw interrupt status
21pub type FRAME_RIS_R = crate::BitReader<FRAME_RIS>;
22impl FRAME_RIS_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> FRAME_RIS {
26        match self.bits {
27            false => FRAME_RIS::NoNewCapture,
28            true => FRAME_RIS::FrameCaptured,
29        }
30    }
31    ///No new capture
32    #[inline(always)]
33    pub fn is_no_new_capture(&self) -> bool {
34        *self == FRAME_RIS::NoNewCapture
35    }
36    ///A frame has been captured
37    #[inline(always)]
38    pub fn is_frame_captured(&self) -> bool {
39        *self == FRAME_RIS::FrameCaptured
40    }
41}
42/**Overrun raw interrupt status
43
44Value on reset: 0*/
45#[cfg_attr(feature = "defmt", derive(defmt::Format))]
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum OVR_RIS {
48    ///0: No data buffer overrun occurred
49    NoOverrun = 0,
50    ///1: A data buffer overrun occurred and the data FIFO is corrupted. The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register
51    OverrunOccured = 1,
52}
53impl From<OVR_RIS> for bool {
54    #[inline(always)]
55    fn from(variant: OVR_RIS) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `OVR_RIS` reader - Overrun raw interrupt status
60pub type OVR_RIS_R = crate::BitReader<OVR_RIS>;
61impl OVR_RIS_R {
62    ///Get enumerated values variant
63    #[inline(always)]
64    pub const fn variant(&self) -> OVR_RIS {
65        match self.bits {
66            false => OVR_RIS::NoOverrun,
67            true => OVR_RIS::OverrunOccured,
68        }
69    }
70    ///No data buffer overrun occurred
71    #[inline(always)]
72    pub fn is_no_overrun(&self) -> bool {
73        *self == OVR_RIS::NoOverrun
74    }
75    ///A data buffer overrun occurred and the data FIFO is corrupted. The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register
76    #[inline(always)]
77    pub fn is_overrun_occured(&self) -> bool {
78        *self == OVR_RIS::OverrunOccured
79    }
80}
81/**Synchronization error raw interrupt status
82
83Value on reset: 0*/
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum ERR_RIS {
87    ///0: No synchronization error detected
88    NoError = 0,
89    ///1: Embedded synchronization characters are not received in the correct order
90    SynchronizationError = 1,
91}
92impl From<ERR_RIS> for bool {
93    #[inline(always)]
94    fn from(variant: ERR_RIS) -> Self {
95        variant as u8 != 0
96    }
97}
98///Field `ERR_RIS` reader - Synchronization error raw interrupt status
99pub type ERR_RIS_R = crate::BitReader<ERR_RIS>;
100impl ERR_RIS_R {
101    ///Get enumerated values variant
102    #[inline(always)]
103    pub const fn variant(&self) -> ERR_RIS {
104        match self.bits {
105            false => ERR_RIS::NoError,
106            true => ERR_RIS::SynchronizationError,
107        }
108    }
109    ///No synchronization error detected
110    #[inline(always)]
111    pub fn is_no_error(&self) -> bool {
112        *self == ERR_RIS::NoError
113    }
114    ///Embedded synchronization characters are not received in the correct order
115    #[inline(always)]
116    pub fn is_synchronization_error(&self) -> bool {
117        *self == ERR_RIS::SynchronizationError
118    }
119}
120/**VSYNC raw interrupt status
121
122Value on reset: 0*/
123#[cfg_attr(feature = "defmt", derive(defmt::Format))]
124#[derive(Clone, Copy, Debug, PartialEq, Eq)]
125pub enum VSYNC_RIS {
126    ///0: Interrupt cleared
127    Cleared = 0,
128    ///1: Interrupt set
129    Set = 1,
130}
131impl From<VSYNC_RIS> for bool {
132    #[inline(always)]
133    fn from(variant: VSYNC_RIS) -> Self {
134        variant as u8 != 0
135    }
136}
137///Field `VSYNC_RIS` reader - VSYNC raw interrupt status
138pub type VSYNC_RIS_R = crate::BitReader<VSYNC_RIS>;
139impl VSYNC_RIS_R {
140    ///Get enumerated values variant
141    #[inline(always)]
142    pub const fn variant(&self) -> VSYNC_RIS {
143        match self.bits {
144            false => VSYNC_RIS::Cleared,
145            true => VSYNC_RIS::Set,
146        }
147    }
148    ///Interrupt cleared
149    #[inline(always)]
150    pub fn is_cleared(&self) -> bool {
151        *self == VSYNC_RIS::Cleared
152    }
153    ///Interrupt set
154    #[inline(always)]
155    pub fn is_set(&self) -> bool {
156        *self == VSYNC_RIS::Set
157    }
158}
159/**Line raw interrupt status
160
161Value on reset: 0*/
162#[cfg_attr(feature = "defmt", derive(defmt::Format))]
163#[derive(Clone, Copy, Debug, PartialEq, Eq)]
164pub enum LINE_RIS {
165    ///0: Interrupt cleared
166    Cleared = 0,
167    ///1: Interrupt set
168    Set = 1,
169}
170impl From<LINE_RIS> for bool {
171    #[inline(always)]
172    fn from(variant: LINE_RIS) -> Self {
173        variant as u8 != 0
174    }
175}
176///Field `LINE_RIS` reader - Line raw interrupt status
177pub type LINE_RIS_R = crate::BitReader<LINE_RIS>;
178impl LINE_RIS_R {
179    ///Get enumerated values variant
180    #[inline(always)]
181    pub const fn variant(&self) -> LINE_RIS {
182        match self.bits {
183            false => LINE_RIS::Cleared,
184            true => LINE_RIS::Set,
185        }
186    }
187    ///Interrupt cleared
188    #[inline(always)]
189    pub fn is_cleared(&self) -> bool {
190        *self == LINE_RIS::Cleared
191    }
192    ///Interrupt set
193    #[inline(always)]
194    pub fn is_set(&self) -> bool {
195        *self == LINE_RIS::Set
196    }
197}
198impl R {
199    ///Bit 0 - Capture complete raw interrupt status
200    #[inline(always)]
201    pub fn frame_ris(&self) -> FRAME_RIS_R {
202        FRAME_RIS_R::new((self.bits & 1) != 0)
203    }
204    ///Bit 1 - Overrun raw interrupt status
205    #[inline(always)]
206    pub fn ovr_ris(&self) -> OVR_RIS_R {
207        OVR_RIS_R::new(((self.bits >> 1) & 1) != 0)
208    }
209    ///Bit 2 - Synchronization error raw interrupt status
210    #[inline(always)]
211    pub fn err_ris(&self) -> ERR_RIS_R {
212        ERR_RIS_R::new(((self.bits >> 2) & 1) != 0)
213    }
214    ///Bit 3 - VSYNC raw interrupt status
215    #[inline(always)]
216    pub fn vsync_ris(&self) -> VSYNC_RIS_R {
217        VSYNC_RIS_R::new(((self.bits >> 3) & 1) != 0)
218    }
219    ///Bit 4 - Line raw interrupt status
220    #[inline(always)]
221    pub fn line_ris(&self) -> LINE_RIS_R {
222        LINE_RIS_R::new(((self.bits >> 4) & 1) != 0)
223    }
224}
225impl core::fmt::Debug for R {
226    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
227        f.debug_struct("RIS")
228            .field("line_ris", &self.line_ris())
229            .field("vsync_ris", &self.vsync_ris())
230            .field("err_ris", &self.err_ris())
231            .field("ovr_ris", &self.ovr_ris())
232            .field("frame_ris", &self.frame_ris())
233            .finish()
234    }
235}
236/**raw interrupt status register
237
238You can [`read`](crate::Reg::read) this register and get [`ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
239
240See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DCMI:RIS)*/
241pub struct RISrs;
242impl crate::RegisterSpec for RISrs {
243    type Ux = u32;
244}
245///`read()` method returns [`ris::R`](R) reader structure
246impl crate::Readable for RISrs {}
247///`reset()` method sets RIS to value 0
248impl crate::Resettable for RISrs {}
stm32f7_staging/stm32f779/dcmi/ris.rs

stm32f7_staging/stm32f779/dcmi/
ris.rs
