stm32f7_staging/stm32f779/dcmi/
dr.rs

1///Register `DR` reader
2pub type R = crate::R<DRrs>;
3///Field `BYTE(0-3)` reader - Data byte %s
4pub type BYTE_R = crate::FieldReader;
5impl R {
6    ///Data byte (0-3)
7    ///
8    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BYTE0` field.</div>
9    #[inline(always)]
10    pub fn byte(&self, n: u8) -> BYTE_R {
11        #[allow(clippy::no_effect)]
12        [(); 4][n as usize];
13        BYTE_R::new(((self.bits >> (n * 8)) & 0xff) as u8)
14    }
15    ///Iterator for array of:
16    ///Data byte (0-3)
17    #[inline(always)]
18    pub fn byte_iter(&self) -> impl Iterator<Item = BYTE_R> + '_ {
19        (0..4).map(move |n| BYTE_R::new(((self.bits >> (n * 8)) & 0xff) as u8))
20    }
21    ///Bits 0:7 - Data byte 0
22    #[inline(always)]
23    pub fn byte0(&self) -> BYTE_R {
24        BYTE_R::new((self.bits & 0xff) as u8)
25    }
26    ///Bits 8:15 - Data byte 1
27    #[inline(always)]
28    pub fn byte1(&self) -> BYTE_R {
29        BYTE_R::new(((self.bits >> 8) & 0xff) as u8)
30    }
31    ///Bits 16:23 - Data byte 2
32    #[inline(always)]
33    pub fn byte2(&self) -> BYTE_R {
34        BYTE_R::new(((self.bits >> 16) & 0xff) as u8)
35    }
36    ///Bits 24:31 - Data byte 3
37    #[inline(always)]
38    pub fn byte3(&self) -> BYTE_R {
39        BYTE_R::new(((self.bits >> 24) & 0xff) as u8)
40    }
41}
42impl core::fmt::Debug for R {
43    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
44        f.debug_struct("DR")
45            .field("byte0", &self.byte0())
46            .field("byte1", &self.byte1())
47            .field("byte2", &self.byte2())
48            .field("byte3", &self.byte3())
49            .finish()
50    }
51}
52/**data register
53
54You can [`read`](crate::Reg::read) this register and get [`dr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
55
56See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#DCMI:DR)*/
57pub struct DRrs;
58impl crate::RegisterSpec for DRrs {
59    type Ux = u32;
60}
61///`read()` method returns [`dr::R`](R) reader structure
62impl crate::Readable for DRrs {}
63///`reset()` method sets DR to value 0
64impl crate::Resettable for DRrs {}
stm32f7_staging/stm32f779/dcmi/dr.rs

stm32f7_staging/stm32f779/dcmi/
dr.rs
