stm32f7_staging/stm32f733/wwdg/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `T` reader - 7-bit counter (MSB to LSB)
6pub type T_R = crate::FieldReader;
7///Field `T` writer - 7-bit counter (MSB to LSB)
8pub type T_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
9/**Activation bit
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum WDGA {
15    ///0: Watchdog disabled
16    Disabled = 0,
17    ///1: Watchdog enabled
18    Enabled = 1,
19}
20impl From<WDGA> for bool {
21    #[inline(always)]
22    fn from(variant: WDGA) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `WDGA` reader - Activation bit
27pub type WDGA_R = crate::BitReader<WDGA>;
28impl WDGA_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> WDGA {
32        match self.bits {
33            false => WDGA::Disabled,
34            true => WDGA::Enabled,
35        }
36    }
37    ///Watchdog disabled
38    #[inline(always)]
39    pub fn is_disabled(&self) -> bool {
40        *self == WDGA::Disabled
41    }
42    ///Watchdog enabled
43    #[inline(always)]
44    pub fn is_enabled(&self) -> bool {
45        *self == WDGA::Enabled
46    }
47}
48///Field `WDGA` writer - Activation bit
49pub type WDGA_W<'a, REG> = crate::BitWriter<'a, REG, WDGA>;
50impl<'a, REG> WDGA_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///Watchdog disabled
55    #[inline(always)]
56    pub fn disabled(self) -> &'a mut crate::W<REG> {
57        self.variant(WDGA::Disabled)
58    }
59    ///Watchdog enabled
60    #[inline(always)]
61    pub fn enabled(self) -> &'a mut crate::W<REG> {
62        self.variant(WDGA::Enabled)
63    }
64}
65impl R {
66    ///Bits 0:6 - 7-bit counter (MSB to LSB)
67    #[inline(always)]
68    pub fn t(&self) -> T_R {
69        T_R::new((self.bits & 0x7f) as u8)
70    }
71    ///Bit 7 - Activation bit
72    #[inline(always)]
73    pub fn wdga(&self) -> WDGA_R {
74        WDGA_R::new(((self.bits >> 7) & 1) != 0)
75    }
76}
77impl core::fmt::Debug for R {
78    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
79        f.debug_struct("CR")
80            .field("wdga", &self.wdga())
81            .field("t", &self.t())
82            .finish()
83    }
84}
85impl W {
86    ///Bits 0:6 - 7-bit counter (MSB to LSB)
87    #[inline(always)]
88    pub fn t(&mut self) -> T_W<CRrs> {
89        T_W::new(self, 0)
90    }
91    ///Bit 7 - Activation bit
92    #[inline(always)]
93    pub fn wdga(&mut self) -> WDGA_W<CRrs> {
94        WDGA_W::new(self, 7)
95    }
96}
97/**Control register
98
99You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
100
101See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#WWDG:CR)*/
102pub struct CRrs;
103impl crate::RegisterSpec for CRrs {
104    type Ux = u16;
105}
106///`read()` method returns [`cr::R`](R) reader structure
107impl crate::Readable for CRrs {}
108///`write(|w| ..)` method takes [`cr::W`](W) writer structure
109impl crate::Writable for CRrs {
110    type Safety = crate::Unsafe;
111}
112///`reset()` method sets CR to value 0x7f
113impl crate::Resettable for CRrs {
114    const RESET_VALUE: u16 = 0x7f;
115}
stm32f7_staging/stm32f733/wwdg/cr.rs

stm32f7_staging/stm32f733/wwdg/
cr.rs
