stm32f7_staging/stm32f733/
tim9.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    _reserved1: [u8; 0x04],
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_5_ccmr1: [u8; 0x04],
12    _reserved6: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    _reserved10: [u8; 0x04],
18    ccr: [CCR; 2],
19}
20impl RegisterBlock {
21    ///0x00 - control register 1
22    #[inline(always)]
23    pub const fn cr1(&self) -> &CR1 {
24        &self.cr1
25    }
26    ///0x08 - slave mode control register
27    #[inline(always)]
28    pub const fn smcr(&self) -> &SMCR {
29        &self.smcr
30    }
31    ///0x0c - DMA/Interrupt enable register
32    #[inline(always)]
33    pub const fn dier(&self) -> &DIER {
34        &self.dier
35    }
36    ///0x10 - status register
37    #[inline(always)]
38    pub const fn sr(&self) -> &SR {
39        &self.sr
40    }
41    ///0x14 - event generation register
42    #[inline(always)]
43    pub const fn egr(&self) -> &EGR {
44        &self.egr
45    }
46    ///0x18 - capture/compare mode register 1 (input mode)
47    #[inline(always)]
48    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
49        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
50    }
51    ///0x18 - capture/compare mode register 1 (output mode)
52    #[inline(always)]
53    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
54        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
55    }
56    ///0x20 - capture/compare enable register
57    #[inline(always)]
58    pub const fn ccer(&self) -> &CCER {
59        &self.ccer
60    }
61    ///0x24 - counter
62    #[inline(always)]
63    pub const fn cnt(&self) -> &CNT {
64        &self.cnt
65    }
66    ///0x28 - prescaler
67    #[inline(always)]
68    pub const fn psc(&self) -> &PSC {
69        &self.psc
70    }
71    ///0x2c - auto-reload register
72    #[inline(always)]
73    pub const fn arr(&self) -> &ARR {
74        &self.arr
75    }
76    ///0x34..0x3c - capture/compare register
77    ///
78    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
79    #[inline(always)]
80    pub const fn ccr(&self, n: usize) -> &CCR {
81        &self.ccr[n]
82    }
83    ///Iterator for array of:
84    ///0x34..0x3c - capture/compare register
85    #[inline(always)]
86    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
87        self.ccr.iter()
88    }
89    ///0x34 - capture/compare register
90    #[inline(always)]
91    pub const fn ccr1(&self) -> &CCR {
92        self.ccr(0)
93    }
94    ///0x38 - capture/compare register
95    #[inline(always)]
96    pub const fn ccr2(&self) -> &CCR {
97        self.ccr(1)
98    }
99}
100/**CR1 (rw) register accessor: control register 1
101
102You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
103
104See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:CR1)
105
106For information about available fields see [`mod@cr1`] module*/
107pub type CR1 = crate::Reg<cr1::CR1rs>;
108///control register 1
109pub mod cr1;
110/**SMCR (rw) register accessor: slave mode control register
111
112You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
113
114See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:SMCR)
115
116For information about available fields see [`mod@smcr`] module*/
117pub type SMCR = crate::Reg<smcr::SMCRrs>;
118///slave mode control register
119pub mod smcr;
120/**DIER (rw) register accessor: DMA/Interrupt enable register
121
122You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:DIER)
125
126For information about available fields see [`mod@dier`] module*/
127pub type DIER = crate::Reg<dier::DIERrs>;
128///DMA/Interrupt enable register
129pub mod dier;
130/**SR (rw) register accessor: status register
131
132You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:SR)
135
136For information about available fields see [`mod@sr`] module*/
137pub type SR = crate::Reg<sr::SRrs>;
138///status register
139pub mod sr;
140/**EGR (w) register accessor: event generation register
141
142You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:EGR)
145
146For information about available fields see [`mod@egr`] module*/
147pub type EGR = crate::Reg<egr::EGRrs>;
148///event generation register
149pub mod egr;
150/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
151
152You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:CCMR1_Output)
155
156For information about available fields see [`mod@ccmr1_output`] module*/
157#[doc(alias = "CCMR1_Output")]
158pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
159///capture/compare mode register 1 (output mode)
160pub mod ccmr1_output;
161/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
162
163You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
164
165See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:CCMR1_Input)
166
167For information about available fields see [`mod@ccmr1_input`] module*/
168#[doc(alias = "CCMR1_Input")]
169pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
170///capture/compare mode register 1 (input mode)
171pub mod ccmr1_input;
172/**CCER (rw) register accessor: capture/compare enable register
173
174You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
175
176See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:CCER)
177
178For information about available fields see [`mod@ccer`] module*/
179pub type CCER = crate::Reg<ccer::CCERrs>;
180///capture/compare enable register
181pub mod ccer;
182/**CNT (rw) register accessor: counter
183
184You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
185
186See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:CNT)
187
188For information about available fields see [`mod@cnt`] module*/
189pub type CNT = crate::Reg<cnt::CNTrs>;
190///counter
191pub mod cnt;
192/**PSC (rw) register accessor: prescaler
193
194You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
195
196See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:PSC)
197
198For information about available fields see [`mod@psc`] module*/
199pub type PSC = crate::Reg<psc::PSCrs>;
200///prescaler
201pub mod psc;
202/**ARR (rw) register accessor: auto-reload register
203
204You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
205
206See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:ARR)
207
208For information about available fields see [`mod@arr`] module*/
209pub type ARR = crate::Reg<arr::ARRrs>;
210///auto-reload register
211pub mod arr;
212/**CCR (rw) register accessor: capture/compare register
213
214You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
215
216See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9:CCR[1])
217
218For information about available fields see [`mod@ccr`] module*/
219pub type CCR = crate::Reg<ccr::CCRrs>;
220///capture/compare register
221pub mod ccr;
stm32f7_staging/stm32f733/tim9.rs

stm32f7_staging/stm32f733/
tim9.rs
