stm32f7_staging/stm32f733/tim5/
smcr.rs

1///Register `SMCR` reader
2pub type R = crate::R<SMCRrs>;
3///Register `SMCR` writer
4pub type W = crate::W<SMCRrs>;
5///Slave mode selection
6pub use crate::stm32f733::tim2::smcr::SMS;
7///Field `SMS` reader - Slave mode selection
8pub use crate::stm32f733::tim2::smcr::SMS_R;
9///Field `SMS` writer - Slave mode selection
10pub use crate::stm32f733::tim2::smcr::SMS_W;
11/**Trigger selection
12
13Value on reset: 0*/
14#[cfg_attr(feature = "defmt", derive(defmt::Format))]
15#[derive(Clone, Copy, Debug, PartialEq, Eq)]
16#[repr(u8)]
17pub enum TS {
18    ///0: Internal Trigger 0 (ITR0)
19    Itr0 = 0,
20    ///1: Internal Trigger 1 (ITR1)
21    Itr1 = 1,
22    ///2: Internal Trigger 2 (ITR2)
23    Itr2 = 2,
24    ///4: TI1 Edge Detector (TI1F_ED)
25    Ti1fEd = 4,
26    ///5: Filtered Timer Input 1 (TI1FP1)
27    Ti1fp1 = 5,
28    ///6: Filtered Timer Input 2 (TI2FP2)
29    Ti2fp2 = 6,
30    ///7: External Trigger input (ETRF)
31    Etrf = 7,
32}
33impl From<TS> for u8 {
34    #[inline(always)]
35    fn from(variant: TS) -> Self {
36        variant as _
37    }
38}
39impl crate::FieldSpec for TS {
40    type Ux = u8;
41}
42impl crate::IsEnum for TS {}
43///Field `TS` reader - Trigger selection
44pub type TS_R = crate::FieldReader<TS>;
45impl TS_R {
46    ///Get enumerated values variant
47    #[inline(always)]
48    pub const fn variant(&self) -> Option<TS> {
49        match self.bits {
50            0 => Some(TS::Itr0),
51            1 => Some(TS::Itr1),
52            2 => Some(TS::Itr2),
53            4 => Some(TS::Ti1fEd),
54            5 => Some(TS::Ti1fp1),
55            6 => Some(TS::Ti2fp2),
56            7 => Some(TS::Etrf),
57            _ => None,
58        }
59    }
60    ///Internal Trigger 0 (ITR0)
61    #[inline(always)]
62    pub fn is_itr0(&self) -> bool {
63        *self == TS::Itr0
64    }
65    ///Internal Trigger 1 (ITR1)
66    #[inline(always)]
67    pub fn is_itr1(&self) -> bool {
68        *self == TS::Itr1
69    }
70    ///Internal Trigger 2 (ITR2)
71    #[inline(always)]
72    pub fn is_itr2(&self) -> bool {
73        *self == TS::Itr2
74    }
75    ///TI1 Edge Detector (TI1F_ED)
76    #[inline(always)]
77    pub fn is_ti1f_ed(&self) -> bool {
78        *self == TS::Ti1fEd
79    }
80    ///Filtered Timer Input 1 (TI1FP1)
81    #[inline(always)]
82    pub fn is_ti1fp1(&self) -> bool {
83        *self == TS::Ti1fp1
84    }
85    ///Filtered Timer Input 2 (TI2FP2)
86    #[inline(always)]
87    pub fn is_ti2fp2(&self) -> bool {
88        *self == TS::Ti2fp2
89    }
90    ///External Trigger input (ETRF)
91    #[inline(always)]
92    pub fn is_etrf(&self) -> bool {
93        *self == TS::Etrf
94    }
95}
96///Field `TS` writer - Trigger selection
97pub type TS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, TS>;
98impl<'a, REG> TS_W<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101    REG::Ux: From<u8>,
102{
103    ///Internal Trigger 0 (ITR0)
104    #[inline(always)]
105    pub fn itr0(self) -> &'a mut crate::W<REG> {
106        self.variant(TS::Itr0)
107    }
108    ///Internal Trigger 1 (ITR1)
109    #[inline(always)]
110    pub fn itr1(self) -> &'a mut crate::W<REG> {
111        self.variant(TS::Itr1)
112    }
113    ///Internal Trigger 2 (ITR2)
114    #[inline(always)]
115    pub fn itr2(self) -> &'a mut crate::W<REG> {
116        self.variant(TS::Itr2)
117    }
118    ///TI1 Edge Detector (TI1F_ED)
119    #[inline(always)]
120    pub fn ti1f_ed(self) -> &'a mut crate::W<REG> {
121        self.variant(TS::Ti1fEd)
122    }
123    ///Filtered Timer Input 1 (TI1FP1)
124    #[inline(always)]
125    pub fn ti1fp1(self) -> &'a mut crate::W<REG> {
126        self.variant(TS::Ti1fp1)
127    }
128    ///Filtered Timer Input 2 (TI2FP2)
129    #[inline(always)]
130    pub fn ti2fp2(self) -> &'a mut crate::W<REG> {
131        self.variant(TS::Ti2fp2)
132    }
133    ///External Trigger input (ETRF)
134    #[inline(always)]
135    pub fn etrf(self) -> &'a mut crate::W<REG> {
136        self.variant(TS::Etrf)
137    }
138}
139///External clock enable
140pub use crate::stm32f733::tim2::smcr::ECE;
141///Field `ECE` reader - External clock enable
142pub use crate::stm32f733::tim2::smcr::ECE_R;
143///Field `ECE` writer - External clock enable
144pub use crate::stm32f733::tim2::smcr::ECE_W;
145///External trigger filter
146pub use crate::stm32f733::tim2::smcr::ETF;
147///Field `ETF` reader - External trigger filter
148pub use crate::stm32f733::tim2::smcr::ETF_R;
149///Field `ETF` writer - External trigger filter
150pub use crate::stm32f733::tim2::smcr::ETF_W;
151///External trigger polarity
152pub use crate::stm32f733::tim2::smcr::ETP;
153///External trigger prescaler
154pub use crate::stm32f733::tim2::smcr::ETPS;
155///Field `ETPS` reader - External trigger prescaler
156pub use crate::stm32f733::tim2::smcr::ETPS_R;
157///Field `ETPS` writer - External trigger prescaler
158pub use crate::stm32f733::tim2::smcr::ETPS_W;
159///Field `ETP` reader - External trigger polarity
160pub use crate::stm32f733::tim2::smcr::ETP_R;
161///Field `ETP` writer - External trigger polarity
162pub use crate::stm32f733::tim2::smcr::ETP_W;
163///Master/Slave mode
164pub use crate::stm32f733::tim2::smcr::MSM;
165///Field `MSM` reader - Master/Slave mode
166pub use crate::stm32f733::tim2::smcr::MSM_R;
167///Field `MSM` writer - Master/Slave mode
168pub use crate::stm32f733::tim2::smcr::MSM_W;
169///Field `SMS_3` reader - Slave model selection - bit\[3\]
170pub type SMS_3_R = crate::BitReader;
171///Field `SMS_3` writer - Slave model selection - bit\[3\]
172pub type SMS_3_W<'a, REG> = crate::BitWriter<'a, REG>;
173impl R {
174    ///Bits 0:2 - Slave mode selection
175    #[inline(always)]
176    pub fn sms(&self) -> SMS_R {
177        SMS_R::new((self.bits & 7) as u8)
178    }
179    ///Bits 4:6 - Trigger selection
180    #[inline(always)]
181    pub fn ts(&self) -> TS_R {
182        TS_R::new(((self.bits >> 4) & 7) as u8)
183    }
184    ///Bit 7 - Master/Slave mode
185    #[inline(always)]
186    pub fn msm(&self) -> MSM_R {
187        MSM_R::new(((self.bits >> 7) & 1) != 0)
188    }
189    ///Bits 8:11 - External trigger filter
190    #[inline(always)]
191    pub fn etf(&self) -> ETF_R {
192        ETF_R::new(((self.bits >> 8) & 0x0f) as u8)
193    }
194    ///Bits 12:13 - External trigger prescaler
195    #[inline(always)]
196    pub fn etps(&self) -> ETPS_R {
197        ETPS_R::new(((self.bits >> 12) & 3) as u8)
198    }
199    ///Bit 14 - External clock enable
200    #[inline(always)]
201    pub fn ece(&self) -> ECE_R {
202        ECE_R::new(((self.bits >> 14) & 1) != 0)
203    }
204    ///Bit 15 - External trigger polarity
205    #[inline(always)]
206    pub fn etp(&self) -> ETP_R {
207        ETP_R::new(((self.bits >> 15) & 1) != 0)
208    }
209    ///Bit 16 - Slave model selection - bit\[3\]
210    #[inline(always)]
211    pub fn sms_3(&self) -> SMS_3_R {
212        SMS_3_R::new(((self.bits >> 16) & 1) != 0)
213    }
214}
215impl core::fmt::Debug for R {
216    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
217        f.debug_struct("SMCR")
218            .field("sms", &self.sms())
219            .field("ts", &self.ts())
220            .field("msm", &self.msm())
221            .field("etf", &self.etf())
222            .field("etps", &self.etps())
223            .field("ece", &self.ece())
224            .field("etp", &self.etp())
225            .field("sms_3", &self.sms_3())
226            .finish()
227    }
228}
229impl W {
230    ///Bits 0:2 - Slave mode selection
231    #[inline(always)]
232    pub fn sms(&mut self) -> SMS_W<SMCRrs> {
233        SMS_W::new(self, 0)
234    }
235    ///Bits 4:6 - Trigger selection
236    #[inline(always)]
237    pub fn ts(&mut self) -> TS_W<SMCRrs> {
238        TS_W::new(self, 4)
239    }
240    ///Bit 7 - Master/Slave mode
241    #[inline(always)]
242    pub fn msm(&mut self) -> MSM_W<SMCRrs> {
243        MSM_W::new(self, 7)
244    }
245    ///Bits 8:11 - External trigger filter
246    #[inline(always)]
247    pub fn etf(&mut self) -> ETF_W<SMCRrs> {
248        ETF_W::new(self, 8)
249    }
250    ///Bits 12:13 - External trigger prescaler
251    #[inline(always)]
252    pub fn etps(&mut self) -> ETPS_W<SMCRrs> {
253        ETPS_W::new(self, 12)
254    }
255    ///Bit 14 - External clock enable
256    #[inline(always)]
257    pub fn ece(&mut self) -> ECE_W<SMCRrs> {
258        ECE_W::new(self, 14)
259    }
260    ///Bit 15 - External trigger polarity
261    #[inline(always)]
262    pub fn etp(&mut self) -> ETP_W<SMCRrs> {
263        ETP_W::new(self, 15)
264    }
265    ///Bit 16 - Slave model selection - bit\[3\]
266    #[inline(always)]
267    pub fn sms_3(&mut self) -> SMS_3_W<SMCRrs> {
268        SMS_3_W::new(self, 16)
269    }
270}
271/**slave mode control register
272
273You can [`read`](crate::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
274
275See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM5:SMCR)*/
276pub struct SMCRrs;
277impl crate::RegisterSpec for SMCRrs {
278    type Ux = u32;
279}
280///`read()` method returns [`smcr::R`](R) reader structure
281impl crate::Readable for SMCRrs {}
282///`write(|w| ..)` method takes [`smcr::W`](W) writer structure
283impl crate::Writable for SMCRrs {
284    type Safety = crate::Unsafe;
285}
286///`reset()` method sets SMCR to value 0
287impl crate::Resettable for SMCRrs {}
stm32f7_staging/stm32f733/tim5/smcr.rs

stm32f7_staging/stm32f733/tim5/
smcr.rs
