stm32f7_staging/stm32f733/tim3/
egr.rs

1///Register `EGR` writer
2pub type W = crate::W<EGRrs>;
3/**Update generation
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum UG {
9    ///1: Re-initializes the timer counter and generates an update of the registers.
10    Update = 1,
11}
12impl From<UG> for bool {
13    #[inline(always)]
14    fn from(variant: UG) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `UG` writer - Update generation
19pub type UG_W<'a, REG> = crate::BitWriter<'a, REG, UG>;
20impl<'a, REG> UG_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Re-initializes the timer counter and generates an update of the registers.
25    #[inline(always)]
26    pub fn update(self) -> &'a mut crate::W<REG> {
27        self.variant(UG::Update)
28    }
29}
30/**Capture/compare %s generation
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum CC1GW {
36    ///1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
37    Trigger = 1,
38}
39impl From<CC1GW> for bool {
40    #[inline(always)]
41    fn from(variant: CC1GW) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `CCG(1-4)` writer - Capture/compare %s generation
46pub type CCG_W<'a, REG> = crate::BitWriter<'a, REG, CC1GW>;
47impl<'a, REG> CCG_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
52    #[inline(always)]
53    pub fn trigger(self) -> &'a mut crate::W<REG> {
54        self.variant(CC1GW::Trigger)
55    }
56}
57/**Trigger generation
58
59Value on reset: 0*/
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TGW {
63    ///1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
64    Trigger = 1,
65}
66impl From<TGW> for bool {
67    #[inline(always)]
68    fn from(variant: TGW) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `TG` writer - Trigger generation
73pub type TG_W<'a, REG> = crate::BitWriter<'a, REG, TGW>;
74impl<'a, REG> TG_W<'a, REG>
75where
76    REG: crate::Writable + crate::RegisterSpec,
77{
78    ///The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
79    #[inline(always)]
80    pub fn trigger(self) -> &'a mut crate::W<REG> {
81        self.variant(TGW::Trigger)
82    }
83}
84impl core::fmt::Debug for crate::generic::Reg<EGRrs> {
85    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
86        write!(f, "(not readable)")
87    }
88}
89impl W {
90    ///Bit 0 - Update generation
91    #[inline(always)]
92    pub fn ug(&mut self) -> UG_W<EGRrs> {
93        UG_W::new(self, 0)
94    }
95    ///Capture/compare (1-4) generation
96    ///
97    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1G` field.</div>
98    #[inline(always)]
99    pub fn ccg(&mut self, n: u8) -> CCG_W<EGRrs> {
100        #[allow(clippy::no_effect)]
101        [(); 4][n as usize];
102        CCG_W::new(self, n + 1)
103    }
104    ///Bit 1 - Capture/compare 1 generation
105    #[inline(always)]
106    pub fn cc1g(&mut self) -> CCG_W<EGRrs> {
107        CCG_W::new(self, 1)
108    }
109    ///Bit 2 - Capture/compare 2 generation
110    #[inline(always)]
111    pub fn cc2g(&mut self) -> CCG_W<EGRrs> {
112        CCG_W::new(self, 2)
113    }
114    ///Bit 3 - Capture/compare 3 generation
115    #[inline(always)]
116    pub fn cc3g(&mut self) -> CCG_W<EGRrs> {
117        CCG_W::new(self, 3)
118    }
119    ///Bit 4 - Capture/compare 4 generation
120    #[inline(always)]
121    pub fn cc4g(&mut self) -> CCG_W<EGRrs> {
122        CCG_W::new(self, 4)
123    }
124    ///Bit 6 - Trigger generation
125    #[inline(always)]
126    pub fn tg(&mut self) -> TG_W<EGRrs> {
127        TG_W::new(self, 6)
128    }
129}
130/**event generation register
131
132You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM3:EGR)*/
135pub struct EGRrs;
136impl crate::RegisterSpec for EGRrs {
137    type Ux = u32;
138}
139///`write(|w| ..)` method takes [`egr::W`](W) writer structure
140impl crate::Writable for EGRrs {
141    type Safety = crate::Unsafe;
142}
143///`reset()` method sets EGR to value 0
144impl crate::Resettable for EGRrs {}
stm32f7_staging/stm32f733/tim3/egr.rs

stm32f7_staging/stm32f733/tim3/
egr.rs
