stm32f7_staging/stm32f733/tim2/
cr1.rs

1///Register `CR1` reader
2pub type R = crate::R<CR1rs>;
3///Register `CR1` writer
4pub type W = crate::W<CR1rs>;
5/**Counter enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CEN {
11    ///0: Counter disabled
12    Disabled = 0,
13    ///1: Counter enabled
14    Enabled = 1,
15}
16impl From<CEN> for bool {
17    #[inline(always)]
18    fn from(variant: CEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CEN` reader - Counter enable
23pub type CEN_R = crate::BitReader<CEN>;
24impl CEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CEN {
28        match self.bits {
29            false => CEN::Disabled,
30            true => CEN::Enabled,
31        }
32    }
33    ///Counter disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CEN::Disabled
37    }
38    ///Counter enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CEN::Enabled
42    }
43}
44///Field `CEN` writer - Counter enable
45pub type CEN_W<'a, REG> = crate::BitWriter<'a, REG, CEN>;
46impl<'a, REG> CEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Counter disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CEN::Disabled)
54    }
55    ///Counter enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CEN::Enabled)
59    }
60}
61/**Update disable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum UDIS {
67    ///0: Update event enabled
68    Enabled = 0,
69    ///1: Update event disabled
70    Disabled = 1,
71}
72impl From<UDIS> for bool {
73    #[inline(always)]
74    fn from(variant: UDIS) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `UDIS` reader - Update disable
79pub type UDIS_R = crate::BitReader<UDIS>;
80impl UDIS_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> UDIS {
84        match self.bits {
85            false => UDIS::Enabled,
86            true => UDIS::Disabled,
87        }
88    }
89    ///Update event enabled
90    #[inline(always)]
91    pub fn is_enabled(&self) -> bool {
92        *self == UDIS::Enabled
93    }
94    ///Update event disabled
95    #[inline(always)]
96    pub fn is_disabled(&self) -> bool {
97        *self == UDIS::Disabled
98    }
99}
100///Field `UDIS` writer - Update disable
101pub type UDIS_W<'a, REG> = crate::BitWriter<'a, REG, UDIS>;
102impl<'a, REG> UDIS_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Update event enabled
107    #[inline(always)]
108    pub fn enabled(self) -> &'a mut crate::W<REG> {
109        self.variant(UDIS::Enabled)
110    }
111    ///Update event disabled
112    #[inline(always)]
113    pub fn disabled(self) -> &'a mut crate::W<REG> {
114        self.variant(UDIS::Disabled)
115    }
116}
117/**Update request source
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum URS {
123    ///0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
124    AnyEvent = 0,
125    ///1: Only counter overflow/underflow generates an update interrupt or DMA request
126    CounterOnly = 1,
127}
128impl From<URS> for bool {
129    #[inline(always)]
130    fn from(variant: URS) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `URS` reader - Update request source
135pub type URS_R = crate::BitReader<URS>;
136impl URS_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> URS {
140        match self.bits {
141            false => URS::AnyEvent,
142            true => URS::CounterOnly,
143        }
144    }
145    ///Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
146    #[inline(always)]
147    pub fn is_any_event(&self) -> bool {
148        *self == URS::AnyEvent
149    }
150    ///Only counter overflow/underflow generates an update interrupt or DMA request
151    #[inline(always)]
152    pub fn is_counter_only(&self) -> bool {
153        *self == URS::CounterOnly
154    }
155}
156///Field `URS` writer - Update request source
157pub type URS_W<'a, REG> = crate::BitWriter<'a, REG, URS>;
158impl<'a, REG> URS_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
163    #[inline(always)]
164    pub fn any_event(self) -> &'a mut crate::W<REG> {
165        self.variant(URS::AnyEvent)
166    }
167    ///Only counter overflow/underflow generates an update interrupt or DMA request
168    #[inline(always)]
169    pub fn counter_only(self) -> &'a mut crate::W<REG> {
170        self.variant(URS::CounterOnly)
171    }
172}
173/**One-pulse mode
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum OPM {
179    ///0: Counter is not stopped at update event
180    Disabled = 0,
181    ///1: Counter stops counting at the next update event (clearing the CEN bit)
182    Enabled = 1,
183}
184impl From<OPM> for bool {
185    #[inline(always)]
186    fn from(variant: OPM) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `OPM` reader - One-pulse mode
191pub type OPM_R = crate::BitReader<OPM>;
192impl OPM_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> OPM {
196        match self.bits {
197            false => OPM::Disabled,
198            true => OPM::Enabled,
199        }
200    }
201    ///Counter is not stopped at update event
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == OPM::Disabled
205    }
206    ///Counter stops counting at the next update event (clearing the CEN bit)
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == OPM::Enabled
210    }
211}
212///Field `OPM` writer - One-pulse mode
213pub type OPM_W<'a, REG> = crate::BitWriter<'a, REG, OPM>;
214impl<'a, REG> OPM_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Counter is not stopped at update event
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(OPM::Disabled)
222    }
223    ///Counter stops counting at the next update event (clearing the CEN bit)
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(OPM::Enabled)
227    }
228}
229/**Direction
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum DIR {
235    ///0: Counter used as upcounter
236    Up = 0,
237    ///1: Counter used as downcounter
238    Down = 1,
239}
240impl From<DIR> for bool {
241    #[inline(always)]
242    fn from(variant: DIR) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `DIR` reader - Direction
247pub type DIR_R = crate::BitReader<DIR>;
248impl DIR_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> DIR {
252        match self.bits {
253            false => DIR::Up,
254            true => DIR::Down,
255        }
256    }
257    ///Counter used as upcounter
258    #[inline(always)]
259    pub fn is_up(&self) -> bool {
260        *self == DIR::Up
261    }
262    ///Counter used as downcounter
263    #[inline(always)]
264    pub fn is_down(&self) -> bool {
265        *self == DIR::Down
266    }
267}
268///Field `DIR` writer - Direction
269pub type DIR_W<'a, REG> = crate::BitWriter<'a, REG, DIR>;
270impl<'a, REG> DIR_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///Counter used as upcounter
275    #[inline(always)]
276    pub fn up(self) -> &'a mut crate::W<REG> {
277        self.variant(DIR::Up)
278    }
279    ///Counter used as downcounter
280    #[inline(always)]
281    pub fn down(self) -> &'a mut crate::W<REG> {
282        self.variant(DIR::Down)
283    }
284}
285/**Center-aligned mode selection
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290#[repr(u8)]
291pub enum CMS {
292    ///0: The counter counts up or down depending on the direction bit
293    EdgeAligned = 0,
294    ///1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
295    CenterAligned1 = 1,
296    ///2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
297    CenterAligned2 = 2,
298    ///3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
299    CenterAligned3 = 3,
300}
301impl From<CMS> for u8 {
302    #[inline(always)]
303    fn from(variant: CMS) -> Self {
304        variant as _
305    }
306}
307impl crate::FieldSpec for CMS {
308    type Ux = u8;
309}
310impl crate::IsEnum for CMS {}
311///Field `CMS` reader - Center-aligned mode selection
312pub type CMS_R = crate::FieldReader<CMS>;
313impl CMS_R {
314    ///Get enumerated values variant
315    #[inline(always)]
316    pub const fn variant(&self) -> CMS {
317        match self.bits {
318            0 => CMS::EdgeAligned,
319            1 => CMS::CenterAligned1,
320            2 => CMS::CenterAligned2,
321            3 => CMS::CenterAligned3,
322            _ => unreachable!(),
323        }
324    }
325    ///The counter counts up or down depending on the direction bit
326    #[inline(always)]
327    pub fn is_edge_aligned(&self) -> bool {
328        *self == CMS::EdgeAligned
329    }
330    ///The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
331    #[inline(always)]
332    pub fn is_center_aligned1(&self) -> bool {
333        *self == CMS::CenterAligned1
334    }
335    ///The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
336    #[inline(always)]
337    pub fn is_center_aligned2(&self) -> bool {
338        *self == CMS::CenterAligned2
339    }
340    ///The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
341    #[inline(always)]
342    pub fn is_center_aligned3(&self) -> bool {
343        *self == CMS::CenterAligned3
344    }
345}
346///Field `CMS` writer - Center-aligned mode selection
347pub type CMS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CMS, crate::Safe>;
348impl<'a, REG> CMS_W<'a, REG>
349where
350    REG: crate::Writable + crate::RegisterSpec,
351    REG::Ux: From<u8>,
352{
353    ///The counter counts up or down depending on the direction bit
354    #[inline(always)]
355    pub fn edge_aligned(self) -> &'a mut crate::W<REG> {
356        self.variant(CMS::EdgeAligned)
357    }
358    ///The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
359    #[inline(always)]
360    pub fn center_aligned1(self) -> &'a mut crate::W<REG> {
361        self.variant(CMS::CenterAligned1)
362    }
363    ///The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
364    #[inline(always)]
365    pub fn center_aligned2(self) -> &'a mut crate::W<REG> {
366        self.variant(CMS::CenterAligned2)
367    }
368    ///The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
369    #[inline(always)]
370    pub fn center_aligned3(self) -> &'a mut crate::W<REG> {
371        self.variant(CMS::CenterAligned3)
372    }
373}
374/**Auto-reload preload enable
375
376Value on reset: 0*/
377#[cfg_attr(feature = "defmt", derive(defmt::Format))]
378#[derive(Clone, Copy, Debug, PartialEq, Eq)]
379pub enum ARPE {
380    ///0: TIMx_APRR register is not buffered
381    Disabled = 0,
382    ///1: TIMx_APRR register is buffered
383    Enabled = 1,
384}
385impl From<ARPE> for bool {
386    #[inline(always)]
387    fn from(variant: ARPE) -> Self {
388        variant as u8 != 0
389    }
390}
391///Field `ARPE` reader - Auto-reload preload enable
392pub type ARPE_R = crate::BitReader<ARPE>;
393impl ARPE_R {
394    ///Get enumerated values variant
395    #[inline(always)]
396    pub const fn variant(&self) -> ARPE {
397        match self.bits {
398            false => ARPE::Disabled,
399            true => ARPE::Enabled,
400        }
401    }
402    ///TIMx_APRR register is not buffered
403    #[inline(always)]
404    pub fn is_disabled(&self) -> bool {
405        *self == ARPE::Disabled
406    }
407    ///TIMx_APRR register is buffered
408    #[inline(always)]
409    pub fn is_enabled(&self) -> bool {
410        *self == ARPE::Enabled
411    }
412}
413///Field `ARPE` writer - Auto-reload preload enable
414pub type ARPE_W<'a, REG> = crate::BitWriter<'a, REG, ARPE>;
415impl<'a, REG> ARPE_W<'a, REG>
416where
417    REG: crate::Writable + crate::RegisterSpec,
418{
419    ///TIMx_APRR register is not buffered
420    #[inline(always)]
421    pub fn disabled(self) -> &'a mut crate::W<REG> {
422        self.variant(ARPE::Disabled)
423    }
424    ///TIMx_APRR register is buffered
425    #[inline(always)]
426    pub fn enabled(self) -> &'a mut crate::W<REG> {
427        self.variant(ARPE::Enabled)
428    }
429}
430/**Clock division
431
432Value on reset: 0*/
433#[cfg_attr(feature = "defmt", derive(defmt::Format))]
434#[derive(Clone, Copy, Debug, PartialEq, Eq)]
435#[repr(u8)]
436pub enum CKD {
437    ///0: t_DTS = t_CK_INT
438    Div1 = 0,
439    ///1: t_DTS = 2 × t_CK_INT
440    Div2 = 1,
441    ///2: t_DTS = 4 × t_CK_INT
442    Div4 = 2,
443}
444impl From<CKD> for u8 {
445    #[inline(always)]
446    fn from(variant: CKD) -> Self {
447        variant as _
448    }
449}
450impl crate::FieldSpec for CKD {
451    type Ux = u8;
452}
453impl crate::IsEnum for CKD {}
454///Field `CKD` reader - Clock division
455pub type CKD_R = crate::FieldReader<CKD>;
456impl CKD_R {
457    ///Get enumerated values variant
458    #[inline(always)]
459    pub const fn variant(&self) -> Option<CKD> {
460        match self.bits {
461            0 => Some(CKD::Div1),
462            1 => Some(CKD::Div2),
463            2 => Some(CKD::Div4),
464            _ => None,
465        }
466    }
467    ///t_DTS = t_CK_INT
468    #[inline(always)]
469    pub fn is_div1(&self) -> bool {
470        *self == CKD::Div1
471    }
472    ///t_DTS = 2 × t_CK_INT
473    #[inline(always)]
474    pub fn is_div2(&self) -> bool {
475        *self == CKD::Div2
476    }
477    ///t_DTS = 4 × t_CK_INT
478    #[inline(always)]
479    pub fn is_div4(&self) -> bool {
480        *self == CKD::Div4
481    }
482}
483///Field `CKD` writer - Clock division
484pub type CKD_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CKD>;
485impl<'a, REG> CKD_W<'a, REG>
486where
487    REG: crate::Writable + crate::RegisterSpec,
488    REG::Ux: From<u8>,
489{
490    ///t_DTS = t_CK_INT
491    #[inline(always)]
492    pub fn div1(self) -> &'a mut crate::W<REG> {
493        self.variant(CKD::Div1)
494    }
495    ///t_DTS = 2 × t_CK_INT
496    #[inline(always)]
497    pub fn div2(self) -> &'a mut crate::W<REG> {
498        self.variant(CKD::Div2)
499    }
500    ///t_DTS = 4 × t_CK_INT
501    #[inline(always)]
502    pub fn div4(self) -> &'a mut crate::W<REG> {
503        self.variant(CKD::Div4)
504    }
505}
506///Field `UIFREMAP` reader - UIF status bit remapping
507pub type UIFREMAP_R = crate::BitReader;
508///Field `UIFREMAP` writer - UIF status bit remapping
509pub type UIFREMAP_W<'a, REG> = crate::BitWriter<'a, REG>;
510impl R {
511    ///Bit 0 - Counter enable
512    #[inline(always)]
513    pub fn cen(&self) -> CEN_R {
514        CEN_R::new((self.bits & 1) != 0)
515    }
516    ///Bit 1 - Update disable
517    #[inline(always)]
518    pub fn udis(&self) -> UDIS_R {
519        UDIS_R::new(((self.bits >> 1) & 1) != 0)
520    }
521    ///Bit 2 - Update request source
522    #[inline(always)]
523    pub fn urs(&self) -> URS_R {
524        URS_R::new(((self.bits >> 2) & 1) != 0)
525    }
526    ///Bit 3 - One-pulse mode
527    #[inline(always)]
528    pub fn opm(&self) -> OPM_R {
529        OPM_R::new(((self.bits >> 3) & 1) != 0)
530    }
531    ///Bit 4 - Direction
532    #[inline(always)]
533    pub fn dir(&self) -> DIR_R {
534        DIR_R::new(((self.bits >> 4) & 1) != 0)
535    }
536    ///Bits 5:6 - Center-aligned mode selection
537    #[inline(always)]
538    pub fn cms(&self) -> CMS_R {
539        CMS_R::new(((self.bits >> 5) & 3) as u8)
540    }
541    ///Bit 7 - Auto-reload preload enable
542    #[inline(always)]
543    pub fn arpe(&self) -> ARPE_R {
544        ARPE_R::new(((self.bits >> 7) & 1) != 0)
545    }
546    ///Bits 8:9 - Clock division
547    #[inline(always)]
548    pub fn ckd(&self) -> CKD_R {
549        CKD_R::new(((self.bits >> 8) & 3) as u8)
550    }
551    ///Bit 11 - UIF status bit remapping
552    #[inline(always)]
553    pub fn uifremap(&self) -> UIFREMAP_R {
554        UIFREMAP_R::new(((self.bits >> 11) & 1) != 0)
555    }
556}
557impl core::fmt::Debug for R {
558    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
559        f.debug_struct("CR1")
560            .field("ckd", &self.ckd())
561            .field("arpe", &self.arpe())
562            .field("cms", &self.cms())
563            .field("dir", &self.dir())
564            .field("opm", &self.opm())
565            .field("urs", &self.urs())
566            .field("udis", &self.udis())
567            .field("cen", &self.cen())
568            .field("uifremap", &self.uifremap())
569            .finish()
570    }
571}
572impl W {
573    ///Bit 0 - Counter enable
574    #[inline(always)]
575    pub fn cen(&mut self) -> CEN_W<CR1rs> {
576        CEN_W::new(self, 0)
577    }
578    ///Bit 1 - Update disable
579    #[inline(always)]
580    pub fn udis(&mut self) -> UDIS_W<CR1rs> {
581        UDIS_W::new(self, 1)
582    }
583    ///Bit 2 - Update request source
584    #[inline(always)]
585    pub fn urs(&mut self) -> URS_W<CR1rs> {
586        URS_W::new(self, 2)
587    }
588    ///Bit 3 - One-pulse mode
589    #[inline(always)]
590    pub fn opm(&mut self) -> OPM_W<CR1rs> {
591        OPM_W::new(self, 3)
592    }
593    ///Bit 4 - Direction
594    #[inline(always)]
595    pub fn dir(&mut self) -> DIR_W<CR1rs> {
596        DIR_W::new(self, 4)
597    }
598    ///Bits 5:6 - Center-aligned mode selection
599    #[inline(always)]
600    pub fn cms(&mut self) -> CMS_W<CR1rs> {
601        CMS_W::new(self, 5)
602    }
603    ///Bit 7 - Auto-reload preload enable
604    #[inline(always)]
605    pub fn arpe(&mut self) -> ARPE_W<CR1rs> {
606        ARPE_W::new(self, 7)
607    }
608    ///Bits 8:9 - Clock division
609    #[inline(always)]
610    pub fn ckd(&mut self) -> CKD_W<CR1rs> {
611        CKD_W::new(self, 8)
612    }
613    ///Bit 11 - UIF status bit remapping
614    #[inline(always)]
615    pub fn uifremap(&mut self) -> UIFREMAP_W<CR1rs> {
616        UIFREMAP_W::new(self, 11)
617    }
618}
619/**control register 1
620
621You can [`read`](crate::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
622
623See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2:CR1)*/
624pub struct CR1rs;
625impl crate::RegisterSpec for CR1rs {
626    type Ux = u32;
627}
628///`read()` method returns [`cr1::R`](R) reader structure
629impl crate::Readable for CR1rs {}
630///`write(|w| ..)` method takes [`cr1::W`](W) writer structure
631impl crate::Writable for CR1rs {
632    type Safety = crate::Unsafe;
633}
634///`reset()` method sets CR1 to value 0
635impl crate::Resettable for CR1rs {}
stm32f7_staging/stm32f733/tim2/cr1.rs

stm32f7_staging/stm32f733/tim2/
cr1.rs
