stm32f7_staging/stm32f733/spi1/
cr2.rs

1///Register `CR2` reader
2pub type R = crate::R<CR2rs>;
3///Register `CR2` writer
4pub type W = crate::W<CR2rs>;
5/**Rx buffer DMA enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum RXDMAEN {
11    ///0: Rx buffer DMA disabled
12    Disabled = 0,
13    ///1: Rx buffer DMA enabled
14    Enabled = 1,
15}
16impl From<RXDMAEN> for bool {
17    #[inline(always)]
18    fn from(variant: RXDMAEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `RXDMAEN` reader - Rx buffer DMA enable
23pub type RXDMAEN_R = crate::BitReader<RXDMAEN>;
24impl RXDMAEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> RXDMAEN {
28        match self.bits {
29            false => RXDMAEN::Disabled,
30            true => RXDMAEN::Enabled,
31        }
32    }
33    ///Rx buffer DMA disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == RXDMAEN::Disabled
37    }
38    ///Rx buffer DMA enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == RXDMAEN::Enabled
42    }
43}
44///Field `RXDMAEN` writer - Rx buffer DMA enable
45pub type RXDMAEN_W<'a, REG> = crate::BitWriter<'a, REG, RXDMAEN>;
46impl<'a, REG> RXDMAEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Rx buffer DMA disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(RXDMAEN::Disabled)
54    }
55    ///Rx buffer DMA enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(RXDMAEN::Enabled)
59    }
60}
61/**Tx buffer DMA enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum TXDMAEN {
67    ///0: Tx buffer DMA disabled
68    Disabled = 0,
69    ///1: Tx buffer DMA enabled
70    Enabled = 1,
71}
72impl From<TXDMAEN> for bool {
73    #[inline(always)]
74    fn from(variant: TXDMAEN) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `TXDMAEN` reader - Tx buffer DMA enable
79pub type TXDMAEN_R = crate::BitReader<TXDMAEN>;
80impl TXDMAEN_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> TXDMAEN {
84        match self.bits {
85            false => TXDMAEN::Disabled,
86            true => TXDMAEN::Enabled,
87        }
88    }
89    ///Tx buffer DMA disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == TXDMAEN::Disabled
93    }
94    ///Tx buffer DMA enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == TXDMAEN::Enabled
98    }
99}
100///Field `TXDMAEN` writer - Tx buffer DMA enable
101pub type TXDMAEN_W<'a, REG> = crate::BitWriter<'a, REG, TXDMAEN>;
102impl<'a, REG> TXDMAEN_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Tx buffer DMA disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(TXDMAEN::Disabled)
110    }
111    ///Tx buffer DMA enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(TXDMAEN::Enabled)
115    }
116}
117/**SS output enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum SSOE {
123    ///0: SS output is disabled in master mode
124    Disabled = 0,
125    ///1: SS output is enabled in master mode
126    Enabled = 1,
127}
128impl From<SSOE> for bool {
129    #[inline(always)]
130    fn from(variant: SSOE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `SSOE` reader - SS output enable
135pub type SSOE_R = crate::BitReader<SSOE>;
136impl SSOE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> SSOE {
140        match self.bits {
141            false => SSOE::Disabled,
142            true => SSOE::Enabled,
143        }
144    }
145    ///SS output is disabled in master mode
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == SSOE::Disabled
149    }
150    ///SS output is enabled in master mode
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == SSOE::Enabled
154    }
155}
156///Field `SSOE` writer - SS output enable
157pub type SSOE_W<'a, REG> = crate::BitWriter<'a, REG, SSOE>;
158impl<'a, REG> SSOE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///SS output is disabled in master mode
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(SSOE::Disabled)
166    }
167    ///SS output is enabled in master mode
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(SSOE::Enabled)
171    }
172}
173/**NSS pulse management
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum NSSP {
179    ///0: No NSS pulse
180    NoPulse = 0,
181    ///1: NSS pulse generated
182    PulseGenerated = 1,
183}
184impl From<NSSP> for bool {
185    #[inline(always)]
186    fn from(variant: NSSP) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `NSSP` reader - NSS pulse management
191pub type NSSP_R = crate::BitReader<NSSP>;
192impl NSSP_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> NSSP {
196        match self.bits {
197            false => NSSP::NoPulse,
198            true => NSSP::PulseGenerated,
199        }
200    }
201    ///No NSS pulse
202    #[inline(always)]
203    pub fn is_no_pulse(&self) -> bool {
204        *self == NSSP::NoPulse
205    }
206    ///NSS pulse generated
207    #[inline(always)]
208    pub fn is_pulse_generated(&self) -> bool {
209        *self == NSSP::PulseGenerated
210    }
211}
212///Field `NSSP` writer - NSS pulse management
213pub type NSSP_W<'a, REG> = crate::BitWriter<'a, REG, NSSP>;
214impl<'a, REG> NSSP_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///No NSS pulse
219    #[inline(always)]
220    pub fn no_pulse(self) -> &'a mut crate::W<REG> {
221        self.variant(NSSP::NoPulse)
222    }
223    ///NSS pulse generated
224    #[inline(always)]
225    pub fn pulse_generated(self) -> &'a mut crate::W<REG> {
226        self.variant(NSSP::PulseGenerated)
227    }
228}
229/**Frame format
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum FRF {
235    ///0: SPI Motorola mode
236    Motorola = 0,
237    ///1: SPI TI mode
238    Ti = 1,
239}
240impl From<FRF> for bool {
241    #[inline(always)]
242    fn from(variant: FRF) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `FRF` reader - Frame format
247pub type FRF_R = crate::BitReader<FRF>;
248impl FRF_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> FRF {
252        match self.bits {
253            false => FRF::Motorola,
254            true => FRF::Ti,
255        }
256    }
257    ///SPI Motorola mode
258    #[inline(always)]
259    pub fn is_motorola(&self) -> bool {
260        *self == FRF::Motorola
261    }
262    ///SPI TI mode
263    #[inline(always)]
264    pub fn is_ti(&self) -> bool {
265        *self == FRF::Ti
266    }
267}
268///Field `FRF` writer - Frame format
269pub type FRF_W<'a, REG> = crate::BitWriter<'a, REG, FRF>;
270impl<'a, REG> FRF_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///SPI Motorola mode
275    #[inline(always)]
276    pub fn motorola(self) -> &'a mut crate::W<REG> {
277        self.variant(FRF::Motorola)
278    }
279    ///SPI TI mode
280    #[inline(always)]
281    pub fn ti(self) -> &'a mut crate::W<REG> {
282        self.variant(FRF::Ti)
283    }
284}
285/**Error interrupt enable
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum ERRIE {
291    ///0: Error interrupt masked
292    Masked = 0,
293    ///1: Error interrupt not masked
294    NotMasked = 1,
295}
296impl From<ERRIE> for bool {
297    #[inline(always)]
298    fn from(variant: ERRIE) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `ERRIE` reader - Error interrupt enable
303pub type ERRIE_R = crate::BitReader<ERRIE>;
304impl ERRIE_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> ERRIE {
308        match self.bits {
309            false => ERRIE::Masked,
310            true => ERRIE::NotMasked,
311        }
312    }
313    ///Error interrupt masked
314    #[inline(always)]
315    pub fn is_masked(&self) -> bool {
316        *self == ERRIE::Masked
317    }
318    ///Error interrupt not masked
319    #[inline(always)]
320    pub fn is_not_masked(&self) -> bool {
321        *self == ERRIE::NotMasked
322    }
323}
324///Field `ERRIE` writer - Error interrupt enable
325pub type ERRIE_W<'a, REG> = crate::BitWriter<'a, REG, ERRIE>;
326impl<'a, REG> ERRIE_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///Error interrupt masked
331    #[inline(always)]
332    pub fn masked(self) -> &'a mut crate::W<REG> {
333        self.variant(ERRIE::Masked)
334    }
335    ///Error interrupt not masked
336    #[inline(always)]
337    pub fn not_masked(self) -> &'a mut crate::W<REG> {
338        self.variant(ERRIE::NotMasked)
339    }
340}
341/**RX buffer not empty interrupt enable
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum RXNEIE {
347    ///0: RXE interrupt masked
348    Masked = 0,
349    ///1: RXE interrupt not masked
350    NotMasked = 1,
351}
352impl From<RXNEIE> for bool {
353    #[inline(always)]
354    fn from(variant: RXNEIE) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `RXNEIE` reader - RX buffer not empty interrupt enable
359pub type RXNEIE_R = crate::BitReader<RXNEIE>;
360impl RXNEIE_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> RXNEIE {
364        match self.bits {
365            false => RXNEIE::Masked,
366            true => RXNEIE::NotMasked,
367        }
368    }
369    ///RXE interrupt masked
370    #[inline(always)]
371    pub fn is_masked(&self) -> bool {
372        *self == RXNEIE::Masked
373    }
374    ///RXE interrupt not masked
375    #[inline(always)]
376    pub fn is_not_masked(&self) -> bool {
377        *self == RXNEIE::NotMasked
378    }
379}
380///Field `RXNEIE` writer - RX buffer not empty interrupt enable
381pub type RXNEIE_W<'a, REG> = crate::BitWriter<'a, REG, RXNEIE>;
382impl<'a, REG> RXNEIE_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///RXE interrupt masked
387    #[inline(always)]
388    pub fn masked(self) -> &'a mut crate::W<REG> {
389        self.variant(RXNEIE::Masked)
390    }
391    ///RXE interrupt not masked
392    #[inline(always)]
393    pub fn not_masked(self) -> &'a mut crate::W<REG> {
394        self.variant(RXNEIE::NotMasked)
395    }
396}
397/**Tx buffer empty interrupt enable
398
399Value on reset: 0*/
400#[cfg_attr(feature = "defmt", derive(defmt::Format))]
401#[derive(Clone, Copy, Debug, PartialEq, Eq)]
402pub enum TXEIE {
403    ///0: TXE interrupt masked
404    Masked = 0,
405    ///1: TXE interrupt not masked
406    NotMasked = 1,
407}
408impl From<TXEIE> for bool {
409    #[inline(always)]
410    fn from(variant: TXEIE) -> Self {
411        variant as u8 != 0
412    }
413}
414///Field `TXEIE` reader - Tx buffer empty interrupt enable
415pub type TXEIE_R = crate::BitReader<TXEIE>;
416impl TXEIE_R {
417    ///Get enumerated values variant
418    #[inline(always)]
419    pub const fn variant(&self) -> TXEIE {
420        match self.bits {
421            false => TXEIE::Masked,
422            true => TXEIE::NotMasked,
423        }
424    }
425    ///TXE interrupt masked
426    #[inline(always)]
427    pub fn is_masked(&self) -> bool {
428        *self == TXEIE::Masked
429    }
430    ///TXE interrupt not masked
431    #[inline(always)]
432    pub fn is_not_masked(&self) -> bool {
433        *self == TXEIE::NotMasked
434    }
435}
436///Field `TXEIE` writer - Tx buffer empty interrupt enable
437pub type TXEIE_W<'a, REG> = crate::BitWriter<'a, REG, TXEIE>;
438impl<'a, REG> TXEIE_W<'a, REG>
439where
440    REG: crate::Writable + crate::RegisterSpec,
441{
442    ///TXE interrupt masked
443    #[inline(always)]
444    pub fn masked(self) -> &'a mut crate::W<REG> {
445        self.variant(TXEIE::Masked)
446    }
447    ///TXE interrupt not masked
448    #[inline(always)]
449    pub fn not_masked(self) -> &'a mut crate::W<REG> {
450        self.variant(TXEIE::NotMasked)
451    }
452}
453/**Data size
454
455Value on reset: 7*/
456#[cfg_attr(feature = "defmt", derive(defmt::Format))]
457#[derive(Clone, Copy, Debug, PartialEq, Eq)]
458#[repr(u8)]
459pub enum DS {
460    ///3: 4-bit
461    FourBit = 3,
462    ///4: 5-bit
463    FiveBit = 4,
464    ///5: 6-bit
465    SixBit = 5,
466    ///6: 7-bit
467    SevenBit = 6,
468    ///7: 8-bit
469    EightBit = 7,
470    ///8: 9-bit
471    NineBit = 8,
472    ///9: 10-bit
473    TenBit = 9,
474    ///10: 11-bit
475    ElevenBit = 10,
476    ///11: 12-bit
477    TwelveBit = 11,
478    ///12: 13-bit
479    ThirteenBit = 12,
480    ///13: 14-bit
481    FourteenBit = 13,
482    ///14: 15-bit
483    FifteenBit = 14,
484    ///15: 16-bit
485    SixteenBit = 15,
486}
487impl From<DS> for u8 {
488    #[inline(always)]
489    fn from(variant: DS) -> Self {
490        variant as _
491    }
492}
493impl crate::FieldSpec for DS {
494    type Ux = u8;
495}
496impl crate::IsEnum for DS {}
497///Field `DS` reader - Data size
498pub type DS_R = crate::FieldReader<DS>;
499impl DS_R {
500    ///Get enumerated values variant
501    #[inline(always)]
502    pub const fn variant(&self) -> Option<DS> {
503        match self.bits {
504            3 => Some(DS::FourBit),
505            4 => Some(DS::FiveBit),
506            5 => Some(DS::SixBit),
507            6 => Some(DS::SevenBit),
508            7 => Some(DS::EightBit),
509            8 => Some(DS::NineBit),
510            9 => Some(DS::TenBit),
511            10 => Some(DS::ElevenBit),
512            11 => Some(DS::TwelveBit),
513            12 => Some(DS::ThirteenBit),
514            13 => Some(DS::FourteenBit),
515            14 => Some(DS::FifteenBit),
516            15 => Some(DS::SixteenBit),
517            _ => None,
518        }
519    }
520    ///4-bit
521    #[inline(always)]
522    pub fn is_four_bit(&self) -> bool {
523        *self == DS::FourBit
524    }
525    ///5-bit
526    #[inline(always)]
527    pub fn is_five_bit(&self) -> bool {
528        *self == DS::FiveBit
529    }
530    ///6-bit
531    #[inline(always)]
532    pub fn is_six_bit(&self) -> bool {
533        *self == DS::SixBit
534    }
535    ///7-bit
536    #[inline(always)]
537    pub fn is_seven_bit(&self) -> bool {
538        *self == DS::SevenBit
539    }
540    ///8-bit
541    #[inline(always)]
542    pub fn is_eight_bit(&self) -> bool {
543        *self == DS::EightBit
544    }
545    ///9-bit
546    #[inline(always)]
547    pub fn is_nine_bit(&self) -> bool {
548        *self == DS::NineBit
549    }
550    ///10-bit
551    #[inline(always)]
552    pub fn is_ten_bit(&self) -> bool {
553        *self == DS::TenBit
554    }
555    ///11-bit
556    #[inline(always)]
557    pub fn is_eleven_bit(&self) -> bool {
558        *self == DS::ElevenBit
559    }
560    ///12-bit
561    #[inline(always)]
562    pub fn is_twelve_bit(&self) -> bool {
563        *self == DS::TwelveBit
564    }
565    ///13-bit
566    #[inline(always)]
567    pub fn is_thirteen_bit(&self) -> bool {
568        *self == DS::ThirteenBit
569    }
570    ///14-bit
571    #[inline(always)]
572    pub fn is_fourteen_bit(&self) -> bool {
573        *self == DS::FourteenBit
574    }
575    ///15-bit
576    #[inline(always)]
577    pub fn is_fifteen_bit(&self) -> bool {
578        *self == DS::FifteenBit
579    }
580    ///16-bit
581    #[inline(always)]
582    pub fn is_sixteen_bit(&self) -> bool {
583        *self == DS::SixteenBit
584    }
585}
586///Field `DS` writer - Data size
587pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 4, DS>;
588impl<'a, REG> DS_W<'a, REG>
589where
590    REG: crate::Writable + crate::RegisterSpec,
591    REG::Ux: From<u8>,
592{
593    ///4-bit
594    #[inline(always)]
595    pub fn four_bit(self) -> &'a mut crate::W<REG> {
596        self.variant(DS::FourBit)
597    }
598    ///5-bit
599    #[inline(always)]
600    pub fn five_bit(self) -> &'a mut crate::W<REG> {
601        self.variant(DS::FiveBit)
602    }
603    ///6-bit
604    #[inline(always)]
605    pub fn six_bit(self) -> &'a mut crate::W<REG> {
606        self.variant(DS::SixBit)
607    }
608    ///7-bit
609    #[inline(always)]
610    pub fn seven_bit(self) -> &'a mut crate::W<REG> {
611        self.variant(DS::SevenBit)
612    }
613    ///8-bit
614    #[inline(always)]
615    pub fn eight_bit(self) -> &'a mut crate::W<REG> {
616        self.variant(DS::EightBit)
617    }
618    ///9-bit
619    #[inline(always)]
620    pub fn nine_bit(self) -> &'a mut crate::W<REG> {
621        self.variant(DS::NineBit)
622    }
623    ///10-bit
624    #[inline(always)]
625    pub fn ten_bit(self) -> &'a mut crate::W<REG> {
626        self.variant(DS::TenBit)
627    }
628    ///11-bit
629    #[inline(always)]
630    pub fn eleven_bit(self) -> &'a mut crate::W<REG> {
631        self.variant(DS::ElevenBit)
632    }
633    ///12-bit
634    #[inline(always)]
635    pub fn twelve_bit(self) -> &'a mut crate::W<REG> {
636        self.variant(DS::TwelveBit)
637    }
638    ///13-bit
639    #[inline(always)]
640    pub fn thirteen_bit(self) -> &'a mut crate::W<REG> {
641        self.variant(DS::ThirteenBit)
642    }
643    ///14-bit
644    #[inline(always)]
645    pub fn fourteen_bit(self) -> &'a mut crate::W<REG> {
646        self.variant(DS::FourteenBit)
647    }
648    ///15-bit
649    #[inline(always)]
650    pub fn fifteen_bit(self) -> &'a mut crate::W<REG> {
651        self.variant(DS::FifteenBit)
652    }
653    ///16-bit
654    #[inline(always)]
655    pub fn sixteen_bit(self) -> &'a mut crate::W<REG> {
656        self.variant(DS::SixteenBit)
657    }
658}
659/**FIFO reception threshold
660
661Value on reset: 0*/
662#[cfg_attr(feature = "defmt", derive(defmt::Format))]
663#[derive(Clone, Copy, Debug, PartialEq, Eq)]
664pub enum FRXTH {
665    ///0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
666    Half = 0,
667    ///1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
668    Quarter = 1,
669}
670impl From<FRXTH> for bool {
671    #[inline(always)]
672    fn from(variant: FRXTH) -> Self {
673        variant as u8 != 0
674    }
675}
676///Field `FRXTH` reader - FIFO reception threshold
677pub type FRXTH_R = crate::BitReader<FRXTH>;
678impl FRXTH_R {
679    ///Get enumerated values variant
680    #[inline(always)]
681    pub const fn variant(&self) -> FRXTH {
682        match self.bits {
683            false => FRXTH::Half,
684            true => FRXTH::Quarter,
685        }
686    }
687    ///RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
688    #[inline(always)]
689    pub fn is_half(&self) -> bool {
690        *self == FRXTH::Half
691    }
692    ///RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
693    #[inline(always)]
694    pub fn is_quarter(&self) -> bool {
695        *self == FRXTH::Quarter
696    }
697}
698///Field `FRXTH` writer - FIFO reception threshold
699pub type FRXTH_W<'a, REG> = crate::BitWriter<'a, REG, FRXTH>;
700impl<'a, REG> FRXTH_W<'a, REG>
701where
702    REG: crate::Writable + crate::RegisterSpec,
703{
704    ///RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
705    #[inline(always)]
706    pub fn half(self) -> &'a mut crate::W<REG> {
707        self.variant(FRXTH::Half)
708    }
709    ///RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
710    #[inline(always)]
711    pub fn quarter(self) -> &'a mut crate::W<REG> {
712        self.variant(FRXTH::Quarter)
713    }
714}
715/**Last DMA transfer for reception
716
717Value on reset: 0*/
718#[cfg_attr(feature = "defmt", derive(defmt::Format))]
719#[derive(Clone, Copy, Debug, PartialEq, Eq)]
720pub enum LDMA_RX {
721    ///0: Number of data to transfer for receive is even
722    Even = 0,
723    ///1: Number of data to transfer for receive is odd
724    Odd = 1,
725}
726impl From<LDMA_RX> for bool {
727    #[inline(always)]
728    fn from(variant: LDMA_RX) -> Self {
729        variant as u8 != 0
730    }
731}
732///Field `LDMA_RX` reader - Last DMA transfer for reception
733pub type LDMA_RX_R = crate::BitReader<LDMA_RX>;
734impl LDMA_RX_R {
735    ///Get enumerated values variant
736    #[inline(always)]
737    pub const fn variant(&self) -> LDMA_RX {
738        match self.bits {
739            false => LDMA_RX::Even,
740            true => LDMA_RX::Odd,
741        }
742    }
743    ///Number of data to transfer for receive is even
744    #[inline(always)]
745    pub fn is_even(&self) -> bool {
746        *self == LDMA_RX::Even
747    }
748    ///Number of data to transfer for receive is odd
749    #[inline(always)]
750    pub fn is_odd(&self) -> bool {
751        *self == LDMA_RX::Odd
752    }
753}
754///Field `LDMA_RX` writer - Last DMA transfer for reception
755pub type LDMA_RX_W<'a, REG> = crate::BitWriter<'a, REG, LDMA_RX>;
756impl<'a, REG> LDMA_RX_W<'a, REG>
757where
758    REG: crate::Writable + crate::RegisterSpec,
759{
760    ///Number of data to transfer for receive is even
761    #[inline(always)]
762    pub fn even(self) -> &'a mut crate::W<REG> {
763        self.variant(LDMA_RX::Even)
764    }
765    ///Number of data to transfer for receive is odd
766    #[inline(always)]
767    pub fn odd(self) -> &'a mut crate::W<REG> {
768        self.variant(LDMA_RX::Odd)
769    }
770}
771/**Last DMA transfer for transmission
772
773Value on reset: 0*/
774#[cfg_attr(feature = "defmt", derive(defmt::Format))]
775#[derive(Clone, Copy, Debug, PartialEq, Eq)]
776pub enum LDMA_TX {
777    ///0: Number of data to transfer for transmit is even
778    Even = 0,
779    ///1: Number of data to transfer for transmit is odd
780    Odd = 1,
781}
782impl From<LDMA_TX> for bool {
783    #[inline(always)]
784    fn from(variant: LDMA_TX) -> Self {
785        variant as u8 != 0
786    }
787}
788///Field `LDMA_TX` reader - Last DMA transfer for transmission
789pub type LDMA_TX_R = crate::BitReader<LDMA_TX>;
790impl LDMA_TX_R {
791    ///Get enumerated values variant
792    #[inline(always)]
793    pub const fn variant(&self) -> LDMA_TX {
794        match self.bits {
795            false => LDMA_TX::Even,
796            true => LDMA_TX::Odd,
797        }
798    }
799    ///Number of data to transfer for transmit is even
800    #[inline(always)]
801    pub fn is_even(&self) -> bool {
802        *self == LDMA_TX::Even
803    }
804    ///Number of data to transfer for transmit is odd
805    #[inline(always)]
806    pub fn is_odd(&self) -> bool {
807        *self == LDMA_TX::Odd
808    }
809}
810///Field `LDMA_TX` writer - Last DMA transfer for transmission
811pub type LDMA_TX_W<'a, REG> = crate::BitWriter<'a, REG, LDMA_TX>;
812impl<'a, REG> LDMA_TX_W<'a, REG>
813where
814    REG: crate::Writable + crate::RegisterSpec,
815{
816    ///Number of data to transfer for transmit is even
817    #[inline(always)]
818    pub fn even(self) -> &'a mut crate::W<REG> {
819        self.variant(LDMA_TX::Even)
820    }
821    ///Number of data to transfer for transmit is odd
822    #[inline(always)]
823    pub fn odd(self) -> &'a mut crate::W<REG> {
824        self.variant(LDMA_TX::Odd)
825    }
826}
827impl R {
828    ///Bit 0 - Rx buffer DMA enable
829    #[inline(always)]
830    pub fn rxdmaen(&self) -> RXDMAEN_R {
831        RXDMAEN_R::new((self.bits & 1) != 0)
832    }
833    ///Bit 1 - Tx buffer DMA enable
834    #[inline(always)]
835    pub fn txdmaen(&self) -> TXDMAEN_R {
836        TXDMAEN_R::new(((self.bits >> 1) & 1) != 0)
837    }
838    ///Bit 2 - SS output enable
839    #[inline(always)]
840    pub fn ssoe(&self) -> SSOE_R {
841        SSOE_R::new(((self.bits >> 2) & 1) != 0)
842    }
843    ///Bit 3 - NSS pulse management
844    #[inline(always)]
845    pub fn nssp(&self) -> NSSP_R {
846        NSSP_R::new(((self.bits >> 3) & 1) != 0)
847    }
848    ///Bit 4 - Frame format
849    #[inline(always)]
850    pub fn frf(&self) -> FRF_R {
851        FRF_R::new(((self.bits >> 4) & 1) != 0)
852    }
853    ///Bit 5 - Error interrupt enable
854    #[inline(always)]
855    pub fn errie(&self) -> ERRIE_R {
856        ERRIE_R::new(((self.bits >> 5) & 1) != 0)
857    }
858    ///Bit 6 - RX buffer not empty interrupt enable
859    #[inline(always)]
860    pub fn rxneie(&self) -> RXNEIE_R {
861        RXNEIE_R::new(((self.bits >> 6) & 1) != 0)
862    }
863    ///Bit 7 - Tx buffer empty interrupt enable
864    #[inline(always)]
865    pub fn txeie(&self) -> TXEIE_R {
866        TXEIE_R::new(((self.bits >> 7) & 1) != 0)
867    }
868    ///Bits 8:11 - Data size
869    #[inline(always)]
870    pub fn ds(&self) -> DS_R {
871        DS_R::new(((self.bits >> 8) & 0x0f) as u8)
872    }
873    ///Bit 12 - FIFO reception threshold
874    #[inline(always)]
875    pub fn frxth(&self) -> FRXTH_R {
876        FRXTH_R::new(((self.bits >> 12) & 1) != 0)
877    }
878    ///Bit 13 - Last DMA transfer for reception
879    #[inline(always)]
880    pub fn ldma_rx(&self) -> LDMA_RX_R {
881        LDMA_RX_R::new(((self.bits >> 13) & 1) != 0)
882    }
883    ///Bit 14 - Last DMA transfer for transmission
884    #[inline(always)]
885    pub fn ldma_tx(&self) -> LDMA_TX_R {
886        LDMA_TX_R::new(((self.bits >> 14) & 1) != 0)
887    }
888}
889impl core::fmt::Debug for R {
890    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
891        f.debug_struct("CR2")
892            .field("rxdmaen", &self.rxdmaen())
893            .field("txdmaen", &self.txdmaen())
894            .field("ssoe", &self.ssoe())
895            .field("nssp", &self.nssp())
896            .field("frf", &self.frf())
897            .field("errie", &self.errie())
898            .field("rxneie", &self.rxneie())
899            .field("txeie", &self.txeie())
900            .field("ds", &self.ds())
901            .field("frxth", &self.frxth())
902            .field("ldma_rx", &self.ldma_rx())
903            .field("ldma_tx", &self.ldma_tx())
904            .finish()
905    }
906}
907impl W {
908    ///Bit 0 - Rx buffer DMA enable
909    #[inline(always)]
910    pub fn rxdmaen(&mut self) -> RXDMAEN_W<CR2rs> {
911        RXDMAEN_W::new(self, 0)
912    }
913    ///Bit 1 - Tx buffer DMA enable
914    #[inline(always)]
915    pub fn txdmaen(&mut self) -> TXDMAEN_W<CR2rs> {
916        TXDMAEN_W::new(self, 1)
917    }
918    ///Bit 2 - SS output enable
919    #[inline(always)]
920    pub fn ssoe(&mut self) -> SSOE_W<CR2rs> {
921        SSOE_W::new(self, 2)
922    }
923    ///Bit 3 - NSS pulse management
924    #[inline(always)]
925    pub fn nssp(&mut self) -> NSSP_W<CR2rs> {
926        NSSP_W::new(self, 3)
927    }
928    ///Bit 4 - Frame format
929    #[inline(always)]
930    pub fn frf(&mut self) -> FRF_W<CR2rs> {
931        FRF_W::new(self, 4)
932    }
933    ///Bit 5 - Error interrupt enable
934    #[inline(always)]
935    pub fn errie(&mut self) -> ERRIE_W<CR2rs> {
936        ERRIE_W::new(self, 5)
937    }
938    ///Bit 6 - RX buffer not empty interrupt enable
939    #[inline(always)]
940    pub fn rxneie(&mut self) -> RXNEIE_W<CR2rs> {
941        RXNEIE_W::new(self, 6)
942    }
943    ///Bit 7 - Tx buffer empty interrupt enable
944    #[inline(always)]
945    pub fn txeie(&mut self) -> TXEIE_W<CR2rs> {
946        TXEIE_W::new(self, 7)
947    }
948    ///Bits 8:11 - Data size
949    #[inline(always)]
950    pub fn ds(&mut self) -> DS_W<CR2rs> {
951        DS_W::new(self, 8)
952    }
953    ///Bit 12 - FIFO reception threshold
954    #[inline(always)]
955    pub fn frxth(&mut self) -> FRXTH_W<CR2rs> {
956        FRXTH_W::new(self, 12)
957    }
958    ///Bit 13 - Last DMA transfer for reception
959    #[inline(always)]
960    pub fn ldma_rx(&mut self) -> LDMA_RX_W<CR2rs> {
961        LDMA_RX_W::new(self, 13)
962    }
963    ///Bit 14 - Last DMA transfer for transmission
964    #[inline(always)]
965    pub fn ldma_tx(&mut self) -> LDMA_TX_W<CR2rs> {
966        LDMA_TX_W::new(self, 14)
967    }
968}
969/**control register 2
970
971You can [`read`](crate::Reg::read) this register and get [`cr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
972
973See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SPI1:CR2)*/
974pub struct CR2rs;
975impl crate::RegisterSpec for CR2rs {
976    type Ux = u16;
977}
978///`read()` method returns [`cr2::R`](R) reader structure
979impl crate::Readable for CR2rs {}
980///`write(|w| ..)` method takes [`cr2::W`](W) writer structure
981impl crate::Writable for CR2rs {
982    type Safety = crate::Unsafe;
983}
984///`reset()` method sets CR2 to value 0x0700
985impl crate::Resettable for CR2rs {
986    const RESET_VALUE: u16 = 0x0700;
987}
stm32f7_staging/stm32f733/spi1/cr2.rs

stm32f7_staging/stm32f733/spi1/
cr2.rs
