stm32f7_staging/stm32f733/rtc/
dr.rs1pub type R = crate::R<DRrs>;
3pub type W = crate::W<DRrs>;
5pub type DU_R = crate::FieldReader;
7pub type DU_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
9pub type DT_R = crate::FieldReader;
11pub type DT_W<'a, REG> = crate::FieldWriter<'a, REG, 2, u8, crate::Safe>;
13pub type MU_R = crate::FieldReader;
15pub type MU_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
17#[cfg_attr(feature = "defmt", derive(defmt::Format))]
21#[derive(Clone, Copy, Debug, PartialEq, Eq)]
22pub enum MT {
23 Zero = 0,
25 One = 1,
27}
28impl From<MT> for bool {
29 #[inline(always)]
30 fn from(variant: MT) -> Self {
31 variant as u8 != 0
32 }
33}
34pub type MT_R = crate::BitReader<MT>;
36impl MT_R {
37 #[inline(always)]
39 pub const fn variant(&self) -> MT {
40 match self.bits {
41 false => MT::Zero,
42 true => MT::One,
43 }
44 }
45 #[inline(always)]
47 pub fn is_zero(&self) -> bool {
48 *self == MT::Zero
49 }
50 #[inline(always)]
52 pub fn is_one(&self) -> bool {
53 *self == MT::One
54 }
55}
56pub type MT_W<'a, REG> = crate::BitWriter<'a, REG, MT>;
58impl<'a, REG> MT_W<'a, REG>
59where
60 REG: crate::Writable + crate::RegisterSpec,
61{
62 #[inline(always)]
64 pub fn zero(self) -> &'a mut crate::W<REG> {
65 self.variant(MT::Zero)
66 }
67 #[inline(always)]
69 pub fn one(self) -> &'a mut crate::W<REG> {
70 self.variant(MT::One)
71 }
72}
73pub type WDU_R = crate::FieldReader;
75pub type WDU_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
77pub type YU_R = crate::FieldReader;
79pub type YU_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
81pub type YT_R = crate::FieldReader;
83pub type YT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
85impl R {
86 #[inline(always)]
88 pub fn du(&self) -> DU_R {
89 DU_R::new((self.bits & 0x0f) as u8)
90 }
91 #[inline(always)]
93 pub fn dt(&self) -> DT_R {
94 DT_R::new(((self.bits >> 4) & 3) as u8)
95 }
96 #[inline(always)]
98 pub fn mu(&self) -> MU_R {
99 MU_R::new(((self.bits >> 8) & 0x0f) as u8)
100 }
101 #[inline(always)]
103 pub fn mt(&self) -> MT_R {
104 MT_R::new(((self.bits >> 12) & 1) != 0)
105 }
106 #[inline(always)]
108 pub fn wdu(&self) -> WDU_R {
109 WDU_R::new(((self.bits >> 13) & 7) as u8)
110 }
111 #[inline(always)]
113 pub fn yu(&self) -> YU_R {
114 YU_R::new(((self.bits >> 16) & 0x0f) as u8)
115 }
116 #[inline(always)]
118 pub fn yt(&self) -> YT_R {
119 YT_R::new(((self.bits >> 20) & 0x0f) as u8)
120 }
121}
122impl core::fmt::Debug for R {
123 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
124 f.debug_struct("DR")
125 .field("yt", &self.yt())
126 .field("yu", &self.yu())
127 .field("wdu", &self.wdu())
128 .field("mt", &self.mt())
129 .field("mu", &self.mu())
130 .field("dt", &self.dt())
131 .field("du", &self.du())
132 .finish()
133 }
134}
135impl W {
136 #[inline(always)]
138 pub fn du(&mut self) -> DU_W<DRrs> {
139 DU_W::new(self, 0)
140 }
141 #[inline(always)]
143 pub fn dt(&mut self) -> DT_W<DRrs> {
144 DT_W::new(self, 4)
145 }
146 #[inline(always)]
148 pub fn mu(&mut self) -> MU_W<DRrs> {
149 MU_W::new(self, 8)
150 }
151 #[inline(always)]
153 pub fn mt(&mut self) -> MT_W<DRrs> {
154 MT_W::new(self, 12)
155 }
156 #[inline(always)]
158 pub fn wdu(&mut self) -> WDU_W<DRrs> {
159 WDU_W::new(self, 13)
160 }
161 #[inline(always)]
163 pub fn yu(&mut self) -> YU_W<DRrs> {
164 YU_W::new(self, 16)
165 }
166 #[inline(always)]
168 pub fn yt(&mut self) -> YT_W<DRrs> {
169 YT_W::new(self, 20)
170 }
171}
172pub struct DRrs;
178impl crate::RegisterSpec for DRrs {
179 type Ux = u32;
180}
181impl crate::Readable for DRrs {}
183impl crate::Writable for DRrs {
185 type Safety = crate::Unsafe;
186}
187impl crate::Resettable for DRrs {
189 const RESET_VALUE: u32 = 0x2101;
190}