stm32f7_staging/stm32f733/
rtc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    tr: TR,
6    dr: DR,
7    cr: CR,
8    isr: ISR,
9    prer: PRER,
10    wutr: WUTR,
11    _reserved6: [u8; 0x04],
12    alrmr: [ALRMR; 2],
13    wpr: WPR,
14    ssr: SSR,
15    shiftr: SHIFTR,
16    tstr: TSTR,
17    tsdr: TSDR,
18    tsssr: TSSSR,
19    calr: CALR,
20    tampcr: TAMPCR,
21    alrmssr: [ALRMSSR; 2],
22    or: OR,
23    bkpr: [BKPR; 32],
24}
25impl RegisterBlock {
26    ///0x00 - time register
27    #[inline(always)]
28    pub const fn tr(&self) -> &TR {
29        &self.tr
30    }
31    ///0x04 - date register
32    #[inline(always)]
33    pub const fn dr(&self) -> &DR {
34        &self.dr
35    }
36    ///0x08 - control register
37    #[inline(always)]
38    pub const fn cr(&self) -> &CR {
39        &self.cr
40    }
41    ///0x0c - initialization and status register
42    #[inline(always)]
43    pub const fn isr(&self) -> &ISR {
44        &self.isr
45    }
46    ///0x10 - prescaler register
47    #[inline(always)]
48    pub const fn prer(&self) -> &PRER {
49        &self.prer
50    }
51    ///0x14 - wakeup timer register
52    #[inline(always)]
53    pub const fn wutr(&self) -> &WUTR {
54        &self.wutr
55    }
56    ///0x1c..0x24 - Alarm %s register
57    ///
58    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `ALRMAR` register.</div>
59    #[inline(always)]
60    pub const fn alrmr(&self, n: usize) -> &ALRMR {
61        &self.alrmr[n]
62    }
63    ///Iterator for array of:
64    ///0x1c..0x24 - Alarm %s register
65    #[inline(always)]
66    pub fn alrmr_iter(&self) -> impl Iterator<Item = &ALRMR> {
67        self.alrmr.iter()
68    }
69    ///0x1c - Alarm A register
70    #[inline(always)]
71    pub const fn alrmar(&self) -> &ALRMR {
72        self.alrmr(0)
73    }
74    ///0x20 - Alarm B register
75    #[inline(always)]
76    pub const fn alrmbr(&self) -> &ALRMR {
77        self.alrmr(1)
78    }
79    ///0x24 - write protection register
80    #[inline(always)]
81    pub const fn wpr(&self) -> &WPR {
82        &self.wpr
83    }
84    ///0x28 - sub second register
85    #[inline(always)]
86    pub const fn ssr(&self) -> &SSR {
87        &self.ssr
88    }
89    ///0x2c - shift control register
90    #[inline(always)]
91    pub const fn shiftr(&self) -> &SHIFTR {
92        &self.shiftr
93    }
94    ///0x30 - time stamp time register
95    #[inline(always)]
96    pub const fn tstr(&self) -> &TSTR {
97        &self.tstr
98    }
99    ///0x34 - time stamp date register
100    #[inline(always)]
101    pub const fn tsdr(&self) -> &TSDR {
102        &self.tsdr
103    }
104    ///0x38 - timestamp sub second register
105    #[inline(always)]
106    pub const fn tsssr(&self) -> &TSSSR {
107        &self.tsssr
108    }
109    ///0x3c - calibration register
110    #[inline(always)]
111    pub const fn calr(&self) -> &CALR {
112        &self.calr
113    }
114    ///0x40 - tamper configuration register
115    #[inline(always)]
116    pub const fn tampcr(&self) -> &TAMPCR {
117        &self.tampcr
118    }
119    ///0x44..0x4c - Alarm %s sub-second register
120    ///
121    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `ALRMASSR` register.</div>
122    #[inline(always)]
123    pub const fn alrmssr(&self, n: usize) -> &ALRMSSR {
124        &self.alrmssr[n]
125    }
126    ///Iterator for array of:
127    ///0x44..0x4c - Alarm %s sub-second register
128    #[inline(always)]
129    pub fn alrmssr_iter(&self) -> impl Iterator<Item = &ALRMSSR> {
130        self.alrmssr.iter()
131    }
132    ///0x44 - Alarm A sub-second register
133    #[inline(always)]
134    pub const fn alrmassr(&self) -> &ALRMSSR {
135        self.alrmssr(0)
136    }
137    ///0x48 - Alarm B sub-second register
138    #[inline(always)]
139    pub const fn alrmbssr(&self) -> &ALRMSSR {
140        self.alrmssr(1)
141    }
142    ///0x4c - option register
143    #[inline(always)]
144    pub const fn or(&self) -> &OR {
145        &self.or
146    }
147    ///0x50..0xd0 - backup register
148    #[inline(always)]
149    pub const fn bkpr(&self, n: usize) -> &BKPR {
150        &self.bkpr[n]
151    }
152    ///Iterator for array of:
153    ///0x50..0xd0 - backup register
154    #[inline(always)]
155    pub fn bkpr_iter(&self) -> impl Iterator<Item = &BKPR> {
156        self.bkpr.iter()
157    }
158    ///0x50 - backup register
159    #[inline(always)]
160    pub const fn bkp0r(&self) -> &BKPR {
161        self.bkpr(0)
162    }
163    ///0x54 - backup register
164    #[inline(always)]
165    pub const fn bkp1r(&self) -> &BKPR {
166        self.bkpr(1)
167    }
168    ///0x58 - backup register
169    #[inline(always)]
170    pub const fn bkp2r(&self) -> &BKPR {
171        self.bkpr(2)
172    }
173    ///0x5c - backup register
174    #[inline(always)]
175    pub const fn bkp3r(&self) -> &BKPR {
176        self.bkpr(3)
177    }
178    ///0x60 - backup register
179    #[inline(always)]
180    pub const fn bkp4r(&self) -> &BKPR {
181        self.bkpr(4)
182    }
183    ///0x64 - backup register
184    #[inline(always)]
185    pub const fn bkp5r(&self) -> &BKPR {
186        self.bkpr(5)
187    }
188    ///0x68 - backup register
189    #[inline(always)]
190    pub const fn bkp6r(&self) -> &BKPR {
191        self.bkpr(6)
192    }
193    ///0x6c - backup register
194    #[inline(always)]
195    pub const fn bkp7r(&self) -> &BKPR {
196        self.bkpr(7)
197    }
198    ///0x70 - backup register
199    #[inline(always)]
200    pub const fn bkp8r(&self) -> &BKPR {
201        self.bkpr(8)
202    }
203    ///0x74 - backup register
204    #[inline(always)]
205    pub const fn bkp9r(&self) -> &BKPR {
206        self.bkpr(9)
207    }
208    ///0x78 - backup register
209    #[inline(always)]
210    pub const fn bkp10r(&self) -> &BKPR {
211        self.bkpr(10)
212    }
213    ///0x7c - backup register
214    #[inline(always)]
215    pub const fn bkp11r(&self) -> &BKPR {
216        self.bkpr(11)
217    }
218    ///0x80 - backup register
219    #[inline(always)]
220    pub const fn bkp12r(&self) -> &BKPR {
221        self.bkpr(12)
222    }
223    ///0x84 - backup register
224    #[inline(always)]
225    pub const fn bkp13r(&self) -> &BKPR {
226        self.bkpr(13)
227    }
228    ///0x88 - backup register
229    #[inline(always)]
230    pub const fn bkp14r(&self) -> &BKPR {
231        self.bkpr(14)
232    }
233    ///0x8c - backup register
234    #[inline(always)]
235    pub const fn bkp15r(&self) -> &BKPR {
236        self.bkpr(15)
237    }
238    ///0x90 - backup register
239    #[inline(always)]
240    pub const fn bkp16r(&self) -> &BKPR {
241        self.bkpr(16)
242    }
243    ///0x94 - backup register
244    #[inline(always)]
245    pub const fn bkp17r(&self) -> &BKPR {
246        self.bkpr(17)
247    }
248    ///0x98 - backup register
249    #[inline(always)]
250    pub const fn bkp18r(&self) -> &BKPR {
251        self.bkpr(18)
252    }
253    ///0x9c - backup register
254    #[inline(always)]
255    pub const fn bkp19r(&self) -> &BKPR {
256        self.bkpr(19)
257    }
258    ///0xa0 - backup register
259    #[inline(always)]
260    pub const fn bkp20r(&self) -> &BKPR {
261        self.bkpr(20)
262    }
263    ///0xa4 - backup register
264    #[inline(always)]
265    pub const fn bkp21r(&self) -> &BKPR {
266        self.bkpr(21)
267    }
268    ///0xa8 - backup register
269    #[inline(always)]
270    pub const fn bkp22r(&self) -> &BKPR {
271        self.bkpr(22)
272    }
273    ///0xac - backup register
274    #[inline(always)]
275    pub const fn bkp23r(&self) -> &BKPR {
276        self.bkpr(23)
277    }
278    ///0xb0 - backup register
279    #[inline(always)]
280    pub const fn bkp24r(&self) -> &BKPR {
281        self.bkpr(24)
282    }
283    ///0xb4 - backup register
284    #[inline(always)]
285    pub const fn bkp25r(&self) -> &BKPR {
286        self.bkpr(25)
287    }
288    ///0xb8 - backup register
289    #[inline(always)]
290    pub const fn bkp26r(&self) -> &BKPR {
291        self.bkpr(26)
292    }
293    ///0xbc - backup register
294    #[inline(always)]
295    pub const fn bkp27r(&self) -> &BKPR {
296        self.bkpr(27)
297    }
298    ///0xc0 - backup register
299    #[inline(always)]
300    pub const fn bkp28r(&self) -> &BKPR {
301        self.bkpr(28)
302    }
303    ///0xc4 - backup register
304    #[inline(always)]
305    pub const fn bkp29r(&self) -> &BKPR {
306        self.bkpr(29)
307    }
308    ///0xc8 - backup register
309    #[inline(always)]
310    pub const fn bkp30r(&self) -> &BKPR {
311        self.bkpr(30)
312    }
313    ///0xcc - backup register
314    #[inline(always)]
315    pub const fn bkp31r(&self) -> &BKPR {
316        self.bkpr(31)
317    }
318}
319/**TR (rw) register accessor: time register
320
321You can [`read`](crate::Reg::read) this register and get [`tr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
322
323See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:TR)
324
325For information about available fields see [`mod@tr`] module*/
326pub type TR = crate::Reg<tr::TRrs>;
327///time register
328pub mod tr;
329/**DR (rw) register accessor: date register
330
331You can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
332
333See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:DR)
334
335For information about available fields see [`mod@dr`] module*/
336pub type DR = crate::Reg<dr::DRrs>;
337///date register
338pub mod dr;
339/**CR (rw) register accessor: control register
340
341You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
342
343See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:CR)
344
345For information about available fields see [`mod@cr`] module*/
346pub type CR = crate::Reg<cr::CRrs>;
347///control register
348pub mod cr;
349/**ISR (rw) register accessor: initialization and status register
350
351You can [`read`](crate::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
352
353See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:ISR)
354
355For information about available fields see [`mod@isr`] module*/
356pub type ISR = crate::Reg<isr::ISRrs>;
357///initialization and status register
358pub mod isr;
359/**PRER (rw) register accessor: prescaler register
360
361You can [`read`](crate::Reg::read) this register and get [`prer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
362
363See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:PRER)
364
365For information about available fields see [`mod@prer`] module*/
366pub type PRER = crate::Reg<prer::PRERrs>;
367///prescaler register
368pub mod prer;
369/**WUTR (rw) register accessor: wakeup timer register
370
371You can [`read`](crate::Reg::read) this register and get [`wutr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wutr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
372
373See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:WUTR)
374
375For information about available fields see [`mod@wutr`] module*/
376pub type WUTR = crate::Reg<wutr::WUTRrs>;
377///wakeup timer register
378pub mod wutr;
379/**ALRMR (rw) register accessor: Alarm %s register
380
381You can [`read`](crate::Reg::read) this register and get [`alrmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alrmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
382
383See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:ALRM[A]R)
384
385For information about available fields see [`mod@alrmr`] module*/
386pub type ALRMR = crate::Reg<alrmr::ALRMRrs>;
387///Alarm %s register
388pub mod alrmr;
389/**WPR (w) register accessor: write protection register
390
391You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
392
393See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:WPR)
394
395For information about available fields see [`mod@wpr`] module*/
396pub type WPR = crate::Reg<wpr::WPRrs>;
397///write protection register
398pub mod wpr;
399/**SSR (r) register accessor: sub second register
400
401You can [`read`](crate::Reg::read) this register and get [`ssr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
402
403See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:SSR)
404
405For information about available fields see [`mod@ssr`] module*/
406pub type SSR = crate::Reg<ssr::SSRrs>;
407///sub second register
408pub mod ssr;
409/**SHIFTR (w) register accessor: shift control register
410
411You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
412
413See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:SHIFTR)
414
415For information about available fields see [`mod@shiftr`] module*/
416pub type SHIFTR = crate::Reg<shiftr::SHIFTRrs>;
417///shift control register
418pub mod shiftr;
419pub use dr as tsdr;
420pub use ssr as tsssr;
421pub use tr as tstr;
422pub use DR as TSDR;
423pub use SSR as TSSSR;
424pub use TR as TSTR;
425/**CALR (rw) register accessor: calibration register
426
427You can [`read`](crate::Reg::read) this register and get [`calr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
428
429See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:CALR)
430
431For information about available fields see [`mod@calr`] module*/
432pub type CALR = crate::Reg<calr::CALRrs>;
433///calibration register
434pub mod calr;
435/**TAMPCR (rw) register accessor: tamper configuration register
436
437You can [`read`](crate::Reg::read) this register and get [`tampcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tampcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
438
439See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:TAMPCR)
440
441For information about available fields see [`mod@tampcr`] module*/
442pub type TAMPCR = crate::Reg<tampcr::TAMPCRrs>;
443///tamper configuration register
444pub mod tampcr;
445/**ALRMSSR (rw) register accessor: Alarm %s sub-second register
446
447You can [`read`](crate::Reg::read) this register and get [`alrmssr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alrmssr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
448
449See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:ALRM[A]SSR)
450
451For information about available fields see [`mod@alrmssr`] module*/
452pub type ALRMSSR = crate::Reg<alrmssr::ALRMSSRrs>;
453///Alarm %s sub-second register
454pub mod alrmssr;
455/**OR (rw) register accessor: option register
456
457You can [`read`](crate::Reg::read) this register and get [`or::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
458
459See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:OR)
460
461For information about available fields see [`mod@or`] module*/
462pub type OR = crate::Reg<or::ORrs>;
463///option register
464pub mod or;
465/**BKPR (rw) register accessor: backup register
466
467You can [`read`](crate::Reg::read) this register and get [`bkpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bkpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
468
469See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC:BKP[0]R)
470
471For information about available fields see [`mod@bkpr`] module*/
472pub type BKPR = crate::Reg<bkpr::BKPRrs>;
473///backup register
474pub mod bkpr;
stm32f7_staging/stm32f733/rtc.rs

stm32f7_staging/stm32f733/
rtc.rs
