stm32f7_staging/stm32f733/
mod.rs

1/*!Peripheral access API for STM32F733 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn WWDG();
21    fn PVD();
22    fn TAMP_STAMP();
23    fn RTC_WKUP();
24    fn FLASH();
25    fn RCC();
26    fn EXTI0();
27    fn EXTI1();
28    fn EXTI2();
29    fn EXTI3();
30    fn EXTI4();
31    fn DMA1_STREAM0();
32    fn DMA1_STREAM1();
33    fn DMA1_STREAM2();
34    fn DMA1_STREAM3();
35    fn DMA1_STREAM4();
36    fn DMA1_STREAM5();
37    fn DMA1_STREAM6();
38    fn ADC();
39    fn CAN1_TX();
40    fn CAN1_RX0();
41    fn CAN1_RX1();
42    fn CAN1_SCE();
43    fn EXTI9_5();
44    fn TIM1_BRK_TIM9();
45    fn TIM1_UP_TIM10();
46    fn TIM1_TRG_COM_TIM11();
47    fn TIM1_CC();
48    fn TIM2();
49    fn TIM3();
50    fn TIM4();
51    fn I2C1_EV();
52    fn I2C1_ER();
53    fn I2C2_EV();
54    fn I2C2_ER();
55    fn SPI1();
56    fn SPI2();
57    fn USART1();
58    fn USART2();
59    fn USART3();
60    fn EXTI15_10();
61    fn RTC_ALARM();
62    fn OTG_FS_WKUP();
63    fn TIM8_BRK_TIM12();
64    fn TIM8_UP_TIM13();
65    fn TIM8_TRG_COM_TIM14();
66    fn TIM8_CC();
67    fn DMA1_STREAM7();
68    fn FSMC();
69    fn SDMMC1();
70    fn TIM5();
71    fn SPI3();
72    fn UART4();
73    fn UART5();
74    fn TIM6_DAC();
75    fn TIM7();
76    fn DMA2_STREAM0();
77    fn DMA2_STREAM1();
78    fn DMA2_STREAM2();
79    fn DMA2_STREAM3();
80    fn DMA2_STREAM4();
81    fn OTG_FS();
82    fn DMA2_STREAM5();
83    fn DMA2_STREAM6();
84    fn DMA2_STREAM7();
85    fn USART6();
86    fn I2C3_EV();
87    fn I2C3_ER();
88    fn OTG_HS_EP1_OUT();
89    fn OTG_HS_EP1_IN();
90    fn OTG_HS_WKUP();
91    fn OTG_HS();
92    fn AES();
93    fn RNG();
94    fn FPU();
95    fn UART7();
96    fn UART8();
97    fn SPI4();
98    fn SPI5();
99    fn SAI1();
100    fn SAI2();
101    fn QUAD_SPI();
102    fn LP_TIMER1();
103    fn SDMMC2();
104}
105#[doc(hidden)]
106#[repr(C)]
107pub union Vector {
108    _handler: unsafe extern "C" fn(),
109    _reserved: u32,
110}
111#[cfg(feature = "rt")]
112#[doc(hidden)]
113#[link_section = ".vector_table.interrupts"]
114#[no_mangle]
115pub static __INTERRUPTS: [Vector; 104] = [
116    Vector { _handler: WWDG },
117    Vector { _handler: PVD },
118    Vector {
119        _handler: TAMP_STAMP,
120    },
121    Vector { _handler: RTC_WKUP },
122    Vector { _handler: FLASH },
123    Vector { _handler: RCC },
124    Vector { _handler: EXTI0 },
125    Vector { _handler: EXTI1 },
126    Vector { _handler: EXTI2 },
127    Vector { _handler: EXTI3 },
128    Vector { _handler: EXTI4 },
129    Vector {
130        _handler: DMA1_STREAM0,
131    },
132    Vector {
133        _handler: DMA1_STREAM1,
134    },
135    Vector {
136        _handler: DMA1_STREAM2,
137    },
138    Vector {
139        _handler: DMA1_STREAM3,
140    },
141    Vector {
142        _handler: DMA1_STREAM4,
143    },
144    Vector {
145        _handler: DMA1_STREAM5,
146    },
147    Vector {
148        _handler: DMA1_STREAM6,
149    },
150    Vector { _handler: ADC },
151    Vector { _handler: CAN1_TX },
152    Vector { _handler: CAN1_RX0 },
153    Vector { _handler: CAN1_RX1 },
154    Vector { _handler: CAN1_SCE },
155    Vector { _handler: EXTI9_5 },
156    Vector {
157        _handler: TIM1_BRK_TIM9,
158    },
159    Vector {
160        _handler: TIM1_UP_TIM10,
161    },
162    Vector {
163        _handler: TIM1_TRG_COM_TIM11,
164    },
165    Vector { _handler: TIM1_CC },
166    Vector { _handler: TIM2 },
167    Vector { _handler: TIM3 },
168    Vector { _handler: TIM4 },
169    Vector { _handler: I2C1_EV },
170    Vector { _handler: I2C1_ER },
171    Vector { _handler: I2C2_EV },
172    Vector { _handler: I2C2_ER },
173    Vector { _handler: SPI1 },
174    Vector { _handler: SPI2 },
175    Vector { _handler: USART1 },
176    Vector { _handler: USART2 },
177    Vector { _handler: USART3 },
178    Vector {
179        _handler: EXTI15_10,
180    },
181    Vector {
182        _handler: RTC_ALARM,
183    },
184    Vector {
185        _handler: OTG_FS_WKUP,
186    },
187    Vector {
188        _handler: TIM8_BRK_TIM12,
189    },
190    Vector {
191        _handler: TIM8_UP_TIM13,
192    },
193    Vector {
194        _handler: TIM8_TRG_COM_TIM14,
195    },
196    Vector { _handler: TIM8_CC },
197    Vector {
198        _handler: DMA1_STREAM7,
199    },
200    Vector { _handler: FSMC },
201    Vector { _handler: SDMMC1 },
202    Vector { _handler: TIM5 },
203    Vector { _handler: SPI3 },
204    Vector { _handler: UART4 },
205    Vector { _handler: UART5 },
206    Vector { _handler: TIM6_DAC },
207    Vector { _handler: TIM7 },
208    Vector {
209        _handler: DMA2_STREAM0,
210    },
211    Vector {
212        _handler: DMA2_STREAM1,
213    },
214    Vector {
215        _handler: DMA2_STREAM2,
216    },
217    Vector {
218        _handler: DMA2_STREAM3,
219    },
220    Vector {
221        _handler: DMA2_STREAM4,
222    },
223    Vector { _reserved: 0 },
224    Vector { _reserved: 0 },
225    Vector { _reserved: 0 },
226    Vector { _reserved: 0 },
227    Vector { _reserved: 0 },
228    Vector { _reserved: 0 },
229    Vector { _handler: OTG_FS },
230    Vector {
231        _handler: DMA2_STREAM5,
232    },
233    Vector {
234        _handler: DMA2_STREAM6,
235    },
236    Vector {
237        _handler: DMA2_STREAM7,
238    },
239    Vector { _handler: USART6 },
240    Vector { _handler: I2C3_EV },
241    Vector { _handler: I2C3_ER },
242    Vector {
243        _handler: OTG_HS_EP1_OUT,
244    },
245    Vector {
246        _handler: OTG_HS_EP1_IN,
247    },
248    Vector {
249        _handler: OTG_HS_WKUP,
250    },
251    Vector { _handler: OTG_HS },
252    Vector { _reserved: 0 },
253    Vector { _handler: AES },
254    Vector { _handler: RNG },
255    Vector { _handler: FPU },
256    Vector { _handler: UART7 },
257    Vector { _handler: UART8 },
258    Vector { _handler: SPI4 },
259    Vector { _handler: SPI5 },
260    Vector { _reserved: 0 },
261    Vector { _handler: SAI1 },
262    Vector { _reserved: 0 },
263    Vector { _reserved: 0 },
264    Vector { _reserved: 0 },
265    Vector { _handler: SAI2 },
266    Vector { _handler: QUAD_SPI },
267    Vector {
268        _handler: LP_TIMER1,
269    },
270    Vector { _reserved: 0 },
271    Vector { _reserved: 0 },
272    Vector { _reserved: 0 },
273    Vector { _reserved: 0 },
274    Vector { _reserved: 0 },
275    Vector { _reserved: 0 },
276    Vector { _reserved: 0 },
277    Vector { _reserved: 0 },
278    Vector { _reserved: 0 },
279    Vector { _handler: SDMMC2 },
280];
281///Enumeration of all the interrupts.
282#[cfg_attr(feature = "defmt", derive(defmt::Format))]
283#[derive(Copy, Clone, Debug, PartialEq, Eq)]
284#[repr(u16)]
285pub enum Interrupt {
286    ///0 - Window Watchdog interrupt
287    WWDG = 0,
288    ///1 - PVD through EXTI line detection interrupt
289    PVD = 1,
290    ///2 - Tamper and TimeStamp interrupts through the EXTI line
291    TAMP_STAMP = 2,
292    ///3 - RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts
293    RTC_WKUP = 3,
294    ///4 - Flash global interrupt
295    FLASH = 4,
296    ///5 - RCC global interrupt
297    RCC = 5,
298    ///6 - EXTI Line0 interrupt
299    EXTI0 = 6,
300    ///7 - EXTI Line1 interrupt
301    EXTI1 = 7,
302    ///8 - EXTI Line2 interrupt
303    EXTI2 = 8,
304    ///9 - EXTI Line3 interrupt
305    EXTI3 = 9,
306    ///10 - EXTI Line4 interrupt
307    EXTI4 = 10,
308    ///11 - DMA1 Stream0 global interrupt
309    DMA1_STREAM0 = 11,
310    ///12 - DMA1 Stream1 global interrupt
311    DMA1_STREAM1 = 12,
312    ///13 - DMA1 Stream2 global interrupt
313    DMA1_STREAM2 = 13,
314    ///14 - DMA1 Stream3 global interrupt
315    DMA1_STREAM3 = 14,
316    ///15 - DMA1 Stream4 global interrupt
317    DMA1_STREAM4 = 15,
318    ///16 - DMA1 Stream5 global interrupt
319    DMA1_STREAM5 = 16,
320    ///17 - DMA1 Stream6 global interrupt
321    DMA1_STREAM6 = 17,
322    ///18 - ADC1 global interrupt
323    ADC = 18,
324    ///19 - CAN1 TX interrupts
325    CAN1_TX = 19,
326    ///20 - CAN1 RX0 interrupts
327    CAN1_RX0 = 20,
328    ///21 - CAN1 RX1 interrupts
329    CAN1_RX1 = 21,
330    ///22 - CAN1 SCE interrupt
331    CAN1_SCE = 22,
332    ///23 - EXTI Line\[9:5\] interrupts
333    EXTI9_5 = 23,
334    ///24 - TIM1 Break interrupt and TIM9 global interrupt
335    TIM1_BRK_TIM9 = 24,
336    ///25 - TIM1 Update interrupt and TIM10
337    TIM1_UP_TIM10 = 25,
338    ///26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
339    TIM1_TRG_COM_TIM11 = 26,
340    ///27 - TIM1 Capture Compare interrupt
341    TIM1_CC = 27,
342    ///28 - TIM2 global interrupt
343    TIM2 = 28,
344    ///29 - TIM3 global interrupt
345    TIM3 = 29,
346    ///30 - TIM4 global interrupt
347    TIM4 = 30,
348    ///31 - I2C1 event interrupt
349    I2C1_EV = 31,
350    ///32 - I2C1 error interrupt
351    I2C1_ER = 32,
352    ///33 - I2C2 event interrupt
353    I2C2_EV = 33,
354    ///34 - I2C2 error interrupt
355    I2C2_ER = 34,
356    ///35 - SPI1 global interrupt
357    SPI1 = 35,
358    ///36 - SPI2 global interrupt
359    SPI2 = 36,
360    ///37 - USART1 global interrupt
361    USART1 = 37,
362    ///38 - USART2 global interrupt
363    USART2 = 38,
364    ///39 - USART3 global interrupt
365    USART3 = 39,
366    ///40 - EXTI Line\[15:10\] interrupts
367    EXTI15_10 = 40,
368    ///41 - RTC alarms through EXTI line 18 interrupts
369    RTC_ALARM = 41,
370    ///42 - USB On-The-Go FS Wakeup through EXTI line interrupt
371    OTG_FS_WKUP = 42,
372    ///43 - TIM8 Break interrupt and TIM12 global interrupt
373    TIM8_BRK_TIM12 = 43,
374    ///44 - TIM8 Update interrupt and TIM13 global interrupt
375    TIM8_UP_TIM13 = 44,
376    ///45 - TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
377    TIM8_TRG_COM_TIM14 = 45,
378    ///46 - TIM8 Capture Compare interrupt
379    TIM8_CC = 46,
380    ///47 - DMA1 Stream7 global interrupt
381    DMA1_STREAM7 = 47,
382    ///48 - FMC global interrupt
383    FSMC = 48,
384    ///49 - SDMMC1 global interrupt
385    SDMMC1 = 49,
386    ///50 - TIM5 global interrupt
387    TIM5 = 50,
388    ///51 - SPI3 global interrupt
389    SPI3 = 51,
390    ///52 - UART4 global interrupt
391    UART4 = 52,
392    ///53 - UART5 global interrupt
393    UART5 = 53,
394    ///54 - TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
395    TIM6_DAC = 54,
396    ///55 - TIM7 global interrupt
397    TIM7 = 55,
398    ///56 - DMA2 Stream0 global interrupt
399    DMA2_STREAM0 = 56,
400    ///57 - DMA2 Stream1 global interrupt
401    DMA2_STREAM1 = 57,
402    ///58 - DMA2 Stream2 global interrupt
403    DMA2_STREAM2 = 58,
404    ///59 - DMA2 Stream3 global interrupt
405    DMA2_STREAM3 = 59,
406    ///60 - DMA2 Stream4 global interrupt
407    DMA2_STREAM4 = 60,
408    ///67 - USB On The Go FS global interrupt
409    OTG_FS = 67,
410    ///68 - DMA2 Stream5 global interrupt
411    DMA2_STREAM5 = 68,
412    ///69 - DMA2 Stream6 global interrupt
413    DMA2_STREAM6 = 69,
414    ///70 - DMA2 Stream7 global interrupt
415    DMA2_STREAM7 = 70,
416    ///71 - USART6 global interrupt
417    USART6 = 71,
418    ///72 - I2C3 event interrupt
419    I2C3_EV = 72,
420    ///73 - I2C3 error interrupt
421    I2C3_ER = 73,
422    ///74 - USB On The Go HS End Point 1 Out
423    OTG_HS_EP1_OUT = 74,
424    ///75 - USB On The Go HS End Point 1 In
425    OTG_HS_EP1_IN = 75,
426    ///76 - USB On The Go HS Wakeup through
427    OTG_HS_WKUP = 76,
428    ///77 - USB On The Go HS global interrupt
429    OTG_HS = 77,
430    ///79 - AES global interrupt
431    AES = 79,
432    ///80 - Rng global interrupt
433    RNG = 80,
434    ///81 - Floating point unit interrupt
435    FPU = 81,
436    ///82 - UART7 global interrupt
437    UART7 = 82,
438    ///83 - UART 8 global interrupt
439    UART8 = 83,
440    ///84 - SPI 4 global interrupt
441    SPI4 = 84,
442    ///85 - SPI 5 global interrupt
443    SPI5 = 85,
444    ///87 - SAI1 global interrupt
445    SAI1 = 87,
446    ///91 - SAI2 global interrupt
447    SAI2 = 91,
448    ///92 - QuadSPI global interrupt
449    QUAD_SPI = 92,
450    ///93 - LP Timer1 global interrupt
451    LP_TIMER1 = 93,
452    ///103 - SDMMC2 global interrupt
453    SDMMC2 = 103,
454}
455unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
456    #[inline(always)]
457    fn number(self) -> u16 {
458        self as u16
459    }
460}
461///Advanced-timers
462///
463///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM1)
464pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_0000>;
465impl core::fmt::Debug for TIM1 {
466    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
467        f.debug_struct("TIM1").finish()
468    }
469}
470///Advanced-timers
471pub mod tim1;
472///Advanced-timers
473///
474///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM1)
475pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_0400>;
476impl core::fmt::Debug for TIM8 {
477    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
478        f.debug_struct("TIM8").finish()
479    }
480}
481///Advanced-timers
482pub use self::tim1 as tim8;
483///Analog-to-digital converter
484///
485///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#ADC2)
486pub type ADC2 = crate::Periph<adc2::RegisterBlock, 0x4001_2100>;
487impl core::fmt::Debug for ADC2 {
488    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
489        f.debug_struct("ADC2").finish()
490    }
491}
492///Analog-to-digital converter
493pub mod adc2;
494///Analog-to-digital converter
495///
496///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#ADC2)
497pub type ADC1 = crate::Periph<adc2::RegisterBlock, 0x4001_2000>;
498impl core::fmt::Debug for ADC1 {
499    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
500        f.debug_struct("ADC1").finish()
501    }
502}
503///Analog-to-digital converter
504pub use self::adc2 as adc1;
505///Analog-to-digital converter
506///
507///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#ADC2)
508pub type ADC3 = crate::Periph<adc2::RegisterBlock, 0x4001_2200>;
509impl core::fmt::Debug for ADC3 {
510    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
511        f.debug_struct("ADC3").finish()
512    }
513}
514///Analog-to-digital converter
515pub use self::adc2 as adc3;
516///Basic timers
517///
518///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM6)
519pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
520impl core::fmt::Debug for TIM6 {
521    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
522        f.debug_struct("TIM6").finish()
523    }
524}
525///Basic timers
526pub mod tim6;
527///Basic timers
528///
529///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM6)
530pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
531impl core::fmt::Debug for TIM7 {
532    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
533        f.debug_struct("TIM7").finish()
534    }
535}
536///Basic timers
537pub use self::tim6 as tim7;
538///Common ADC registers
539///
540///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#ADC_Common)
541pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4001_2300>;
542impl core::fmt::Debug for ADC_COMMON {
543    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
544        f.debug_struct("ADC_COMMON").finish()
545    }
546}
547///Common ADC registers
548pub mod adc_common;
549///Controller area network
550///
551///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#CAN1)
552pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
553impl core::fmt::Debug for CAN1 {
554    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
555        f.debug_struct("CAN1").finish()
556    }
557}
558///Controller area network
559pub mod can1;
560///Cryptographic processor
561///
562///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#CRC)
563pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
564impl core::fmt::Debug for CRC {
565    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
566        f.debug_struct("CRC").finish()
567    }
568}
569///Cryptographic processor
570pub mod crc;
571///Cryptographic processor
572///
573///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#CRYP)
574pub type CRYP = crate::Periph<cryp::RegisterBlock, 0x5006_0000>;
575impl core::fmt::Debug for CRYP {
576    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
577        f.debug_struct("CRYP").finish()
578    }
579}
580///Cryptographic processor
581pub mod cryp;
582///Debug support
583///
584///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#DBGMCU)
585pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
586impl core::fmt::Debug for DBGMCU {
587    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
588        f.debug_struct("DBGMCU").finish()
589    }
590}
591///Debug support
592pub mod dbgmcu;
593///Digital-to-analog converter
594///
595///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#DAC)
596pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
597impl core::fmt::Debug for DAC {
598    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
599        f.debug_struct("DAC").finish()
600    }
601}
602///Digital-to-analog converter
603pub mod dac;
604///DMA controller
605///
606///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#DMA2)
607pub type DMA2 = crate::Periph<dma2::RegisterBlock, 0x4002_6400>;
608impl core::fmt::Debug for DMA2 {
609    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
610        f.debug_struct("DMA2").finish()
611    }
612}
613///DMA controller
614pub mod dma2;
615///DMA controller
616///
617///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#DMA2)
618pub type DMA1 = crate::Periph<dma2::RegisterBlock, 0x4002_6000>;
619impl core::fmt::Debug for DMA1 {
620    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
621        f.debug_struct("DMA1").finish()
622    }
623}
624///DMA controller
625pub use self::dma2 as dma1;
626///External interrupt/event controller
627///
628///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#EXTI)
629pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_3c00>;
630impl core::fmt::Debug for EXTI {
631    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
632        f.debug_struct("EXTI").finish()
633    }
634}
635///External interrupt/event controller
636pub mod exti;
637///FLASH
638///
639///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#FLASH)
640pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_3c00>;
641impl core::fmt::Debug for FLASH {
642    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
643        f.debug_struct("FLASH").finish()
644    }
645}
646///FLASH
647pub mod flash;
648///Flexible memory controller
649///
650///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#FMC)
651pub type FMC = crate::Periph<fmc::RegisterBlock, 0xa000_0000>;
652impl core::fmt::Debug for FMC {
653    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
654        f.debug_struct("FMC").finish()
655    }
656}
657///Flexible memory controller
658pub mod fmc;
659///General purpose timers
660///
661///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9)
662pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4000>;
663impl core::fmt::Debug for TIM9 {
664    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
665        f.debug_struct("TIM9").finish()
666    }
667}
668///General purpose timers
669pub mod tim9;
670///General purpose timers
671///
672///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM9)
673pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
674impl core::fmt::Debug for TIM12 {
675    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
676        f.debug_struct("TIM12").finish()
677    }
678}
679///General purpose timers
680pub use self::tim9 as tim12;
681///General purpose timers
682///
683///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM2)
684pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
685impl core::fmt::Debug for TIM2 {
686    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
687        f.debug_struct("TIM2").finish()
688    }
689}
690///General purpose timers
691pub mod tim2;
692///General purpose timers
693///
694///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM3)
695pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
696impl core::fmt::Debug for TIM3 {
697    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
698        f.debug_struct("TIM3").finish()
699    }
700}
701///General purpose timers
702pub mod tim3;
703///General purpose timers
704///
705///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM3)
706pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
707impl core::fmt::Debug for TIM4 {
708    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
709        f.debug_struct("TIM4").finish()
710    }
711}
712///General purpose timers
713pub use self::tim3 as tim4;
714///General purpose timers
715///
716///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM5)
717pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_0c00>;
718impl core::fmt::Debug for TIM5 {
719    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
720        f.debug_struct("TIM5").finish()
721    }
722}
723///General purpose timers
724pub mod tim5;
725///General-purpose I/Os
726///
727///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOH)
728pub type GPIOH = crate::Periph<gpioh::RegisterBlock, 0x4002_1c00>;
729impl core::fmt::Debug for GPIOH {
730    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
731        f.debug_struct("GPIOH").finish()
732    }
733}
734///General-purpose I/Os
735pub mod gpioh;
736///General-purpose I/Os
737///
738///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOH)
739pub type GPIOF = crate::Periph<gpioh::RegisterBlock, 0x4002_1400>;
740impl core::fmt::Debug for GPIOF {
741    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
742        f.debug_struct("GPIOF").finish()
743    }
744}
745///General-purpose I/Os
746pub use self::gpioh as gpiof;
747///General-purpose I/Os
748///
749///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOH)
750pub type GPIOG = crate::Periph<gpioh::RegisterBlock, 0x4002_1800>;
751impl core::fmt::Debug for GPIOG {
752    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
753        f.debug_struct("GPIOG").finish()
754    }
755}
756///General-purpose I/Os
757pub use self::gpioh as gpiog;
758///General-purpose I/Os
759///
760///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOH)
761pub type GPIOI = crate::Periph<gpioh::RegisterBlock, 0x4002_2000>;
762impl core::fmt::Debug for GPIOI {
763    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
764        f.debug_struct("GPIOI").finish()
765    }
766}
767///General-purpose I/Os
768pub use self::gpioh as gpioi;
769///General-purpose I/Os
770///
771///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOH)
772pub type GPIOE = crate::Periph<gpioh::RegisterBlock, 0x4002_1000>;
773impl core::fmt::Debug for GPIOE {
774    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
775        f.debug_struct("GPIOE").finish()
776    }
777}
778///General-purpose I/Os
779pub use self::gpioh as gpioe;
780///General-purpose I/Os
781///
782///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOH)
783pub type GPIOD = crate::Periph<gpioh::RegisterBlock, 0x4002_0c00>;
784impl core::fmt::Debug for GPIOD {
785    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
786        f.debug_struct("GPIOD").finish()
787    }
788}
789///General-purpose I/Os
790pub use self::gpioh as gpiod;
791///General-purpose I/Os
792///
793///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOH)
794pub type GPIOC = crate::Periph<gpioh::RegisterBlock, 0x4002_0800>;
795impl core::fmt::Debug for GPIOC {
796    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
797        f.debug_struct("GPIOC").finish()
798    }
799}
800///General-purpose I/Os
801pub use self::gpioh as gpioc;
802///General-purpose I/Os
803///
804///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOB)
805pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4002_0400>;
806impl core::fmt::Debug for GPIOB {
807    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
808        f.debug_struct("GPIOB").finish()
809    }
810}
811///General-purpose I/Os
812pub mod gpiob;
813///General-purpose I/Os
814///
815///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOA)
816pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4002_0000>;
817impl core::fmt::Debug for GPIOA {
818    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
819        f.debug_struct("GPIOA").finish()
820    }
821}
822///General-purpose I/Os
823pub mod gpioa;
824///General-purpose-timers
825///
826///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM13)
827pub type TIM13 = crate::Periph<tim13::RegisterBlock, 0x4000_1c00>;
828impl core::fmt::Debug for TIM13 {
829    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
830        f.debug_struct("TIM13").finish()
831    }
832}
833///General-purpose-timers
834pub mod tim13;
835///General-purpose-timers
836///
837///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM13)
838pub type TIM14 = crate::Periph<tim13::RegisterBlock, 0x4000_2000>;
839impl core::fmt::Debug for TIM14 {
840    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
841        f.debug_struct("TIM14").finish()
842    }
843}
844///General-purpose-timers
845pub use self::tim13 as tim14;
846///General-purpose-timers
847///
848///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM13)
849pub type TIM10 = crate::Periph<tim13::RegisterBlock, 0x4001_4400>;
850impl core::fmt::Debug for TIM10 {
851    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
852        f.debug_struct("TIM10").finish()
853    }
854}
855///General-purpose-timers
856pub use self::tim13 as tim10;
857///General-purpose-timers
858///
859///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#TIM13)
860pub type TIM11 = crate::Periph<tim13::RegisterBlock, 0x4001_4800>;
861impl core::fmt::Debug for TIM11 {
862    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
863        f.debug_struct("TIM11").finish()
864    }
865}
866///General-purpose-timers
867pub use self::tim13 as tim11;
868///Independent watchdog
869///
870///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#IWDG)
871pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
872impl core::fmt::Debug for IWDG {
873    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
874        f.debug_struct("IWDG").finish()
875    }
876}
877///Independent watchdog
878pub mod iwdg;
879///Inter-integrated circuit
880///
881///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#I2C1)
882pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
883impl core::fmt::Debug for I2C1 {
884    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
885        f.debug_struct("I2C1").finish()
886    }
887}
888///Inter-integrated circuit
889pub mod i2c1;
890///Inter-integrated circuit
891///
892///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#I2C1)
893pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
894impl core::fmt::Debug for I2C2 {
895    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
896        f.debug_struct("I2C2").finish()
897    }
898}
899///Inter-integrated circuit
900pub use self::i2c1 as i2c2;
901///Inter-integrated circuit
902///
903///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#I2C1)
904pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
905impl core::fmt::Debug for I2C3 {
906    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
907        f.debug_struct("I2C3").finish()
908    }
909}
910///Inter-integrated circuit
911pub use self::i2c1 as i2c3;
912///Low power timer
913///
914///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#LPTIM1)
915pub type LPTIM1 = crate::Periph<lptim1::RegisterBlock, 0x4000_2400>;
916impl core::fmt::Debug for LPTIM1 {
917    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
918        f.debug_struct("LPTIM1").finish()
919    }
920}
921///Low power timer
922pub mod lptim1;
923///Power control
924///
925///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#PWR)
926pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
927impl core::fmt::Debug for PWR {
928    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
929        f.debug_struct("PWR").finish()
930    }
931}
932///Power control
933pub mod pwr;
934///QuadSPI interface
935///
936///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#QUADSPI)
937pub type QUADSPI = crate::Periph<quadspi::RegisterBlock, 0xa000_1000>;
938impl core::fmt::Debug for QUADSPI {
939    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
940        f.debug_struct("QUADSPI").finish()
941    }
942}
943///QuadSPI interface
944pub mod quadspi;
945///Random number generator
946///
947///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RNG)
948pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
949impl core::fmt::Debug for RNG {
950    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
951        f.debug_struct("RNG").finish()
952    }
953}
954///Random number generator
955pub mod rng;
956///Real-time clock
957///
958///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RTC)
959pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
960impl core::fmt::Debug for RTC {
961    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
962        f.debug_struct("RTC").finish()
963    }
964}
965///Real-time clock
966pub mod rtc;
967///Reset and clock control
968///
969///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#RCC)
970pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_3800>;
971impl core::fmt::Debug for RCC {
972    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
973        f.debug_struct("RCC").finish()
974    }
975}
976///Reset and clock control
977pub mod rcc;
978///Secure digital input/output interface
979///
980///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SDMMC1)
981pub type SDMMC1 = crate::Periph<sdmmc1::RegisterBlock, 0x4001_2c00>;
982impl core::fmt::Debug for SDMMC1 {
983    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
984        f.debug_struct("SDMMC1").finish()
985    }
986}
987///Secure digital input/output interface
988pub mod sdmmc1;
989///Secure digital input/output interface
990///
991///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SDMMC1)
992pub type SDMMC2 = crate::Periph<sdmmc1::RegisterBlock, 0x4001_1c00>;
993impl core::fmt::Debug for SDMMC2 {
994    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
995        f.debug_struct("SDMMC2").finish()
996    }
997}
998///Secure digital input/output interface
999pub use self::sdmmc1 as sdmmc2;
1000///Serial audio interface
1001///
1002///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SAI1)
1003pub type SAI1 = crate::Periph<sai1::RegisterBlock, 0x4001_5800>;
1004impl core::fmt::Debug for SAI1 {
1005    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1006        f.debug_struct("SAI1").finish()
1007    }
1008}
1009///Serial audio interface
1010pub mod sai1;
1011///Serial audio interface
1012///
1013///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SAI1)
1014pub type SAI2 = crate::Periph<sai1::RegisterBlock, 0x4001_5c00>;
1015impl core::fmt::Debug for SAI2 {
1016    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1017        f.debug_struct("SAI2").finish()
1018    }
1019}
1020///Serial audio interface
1021pub use self::sai1 as sai2;
1022///Serial peripheral interface
1023///
1024///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SPI1)
1025pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
1026impl core::fmt::Debug for SPI1 {
1027    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1028        f.debug_struct("SPI1").finish()
1029    }
1030}
1031///Serial peripheral interface
1032pub mod spi1;
1033///Serial peripheral interface
1034///
1035///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SPI1)
1036pub type SPI5 = crate::Periph<spi1::RegisterBlock, 0x4001_5000>;
1037impl core::fmt::Debug for SPI5 {
1038    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1039        f.debug_struct("SPI5").finish()
1040    }
1041}
1042///Serial peripheral interface
1043pub use self::spi1 as spi5;
1044///Serial peripheral interface
1045///
1046///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SPI1)
1047pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
1048impl core::fmt::Debug for SPI2 {
1049    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1050        f.debug_struct("SPI2").finish()
1051    }
1052}
1053///Serial peripheral interface
1054pub use self::spi1 as spi2;
1055///Serial peripheral interface
1056///
1057///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SPI1)
1058pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3400>;
1059impl core::fmt::Debug for SPI4 {
1060    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1061        f.debug_struct("SPI4").finish()
1062    }
1063}
1064///Serial peripheral interface
1065pub use self::spi1 as spi4;
1066///Serial peripheral interface
1067///
1068///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SPI1)
1069pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
1070impl core::fmt::Debug for SPI3 {
1071    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1072        f.debug_struct("SPI3").finish()
1073    }
1074}
1075///Serial peripheral interface
1076pub use self::spi1 as spi3;
1077///System configuration controller
1078///
1079///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#SYSCFG)
1080pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_3800>;
1081impl core::fmt::Debug for SYSCFG {
1082    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1083        f.debug_struct("SYSCFG").finish()
1084    }
1085}
1086///System configuration controller
1087pub mod syscfg;
1088///Universal synchronous asynchronous receiver transmitter
1089///
1090///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#USART1)
1091pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
1092impl core::fmt::Debug for USART1 {
1093    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1094        f.debug_struct("USART1").finish()
1095    }
1096}
1097///Universal synchronous asynchronous receiver transmitter
1098pub mod usart1;
1099///Universal synchronous asynchronous receiver transmitter
1100///
1101///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#USART1)
1102pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
1103impl core::fmt::Debug for USART3 {
1104    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1105        f.debug_struct("USART3").finish()
1106    }
1107}
1108///Universal synchronous asynchronous receiver transmitter
1109pub use self::usart1 as usart3;
1110///Universal synchronous asynchronous receiver transmitter
1111///
1112///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#USART1)
1113pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4001_1400>;
1114impl core::fmt::Debug for USART6 {
1115    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1116        f.debug_struct("USART6").finish()
1117    }
1118}
1119///Universal synchronous asynchronous receiver transmitter
1120pub use self::usart1 as usart6;
1121///Universal synchronous asynchronous receiver transmitter
1122///
1123///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#USART1)
1124pub type UART8 = crate::Periph<usart1::RegisterBlock, 0x4000_7c00>;
1125impl core::fmt::Debug for UART8 {
1126    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1127        f.debug_struct("UART8").finish()
1128    }
1129}
1130///Universal synchronous asynchronous receiver transmitter
1131pub use self::usart1 as uart8;
1132///Universal synchronous asynchronous receiver transmitter
1133///
1134///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#USART1)
1135pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
1136impl core::fmt::Debug for USART2 {
1137    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1138        f.debug_struct("USART2").finish()
1139    }
1140}
1141///Universal synchronous asynchronous receiver transmitter
1142pub use self::usart1 as usart2;
1143///Universal synchronous asynchronous receiver transmitter
1144///
1145///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#USART1)
1146pub type UART7 = crate::Periph<usart1::RegisterBlock, 0x4000_7800>;
1147impl core::fmt::Debug for UART7 {
1148    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1149        f.debug_struct("UART7").finish()
1150    }
1151}
1152///Universal synchronous asynchronous receiver transmitter
1153pub use self::usart1 as uart7;
1154///Universal synchronous asynchronous receiver transmitter
1155///
1156///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#USART1)
1157pub type UART4 = crate::Periph<usart1::RegisterBlock, 0x4000_4c00>;
1158impl core::fmt::Debug for UART4 {
1159    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1160        f.debug_struct("UART4").finish()
1161    }
1162}
1163///Universal synchronous asynchronous receiver transmitter
1164pub use self::usart1 as uart4;
1165///Universal synchronous asynchronous receiver transmitter
1166///
1167///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#USART1)
1168pub type UART5 = crate::Periph<usart1::RegisterBlock, 0x4000_5000>;
1169impl core::fmt::Debug for UART5 {
1170    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1171        f.debug_struct("UART5").finish()
1172    }
1173}
1174///Universal synchronous asynchronous receiver transmitter
1175pub use self::usart1 as uart5;
1176///USB on the go full speed
1177///
1178///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#OTG_FS_GLOBAL)
1179pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
1180impl core::fmt::Debug for OTG_FS_GLOBAL {
1181    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1182        f.debug_struct("OTG_FS_GLOBAL").finish()
1183    }
1184}
1185///USB on the go full speed
1186pub mod otg_fs_global;
1187///USB on the go full speed
1188///
1189///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#OTG_FS_HOST)
1190pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
1191impl core::fmt::Debug for OTG_FS_HOST {
1192    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1193        f.debug_struct("OTG_FS_HOST").finish()
1194    }
1195}
1196///USB on the go full speed
1197pub mod otg_fs_host;
1198///USB on the go full speed
1199///
1200///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#OTG_FS_DEVICE)
1201pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
1202impl core::fmt::Debug for OTG_FS_DEVICE {
1203    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1204        f.debug_struct("OTG_FS_DEVICE").finish()
1205    }
1206}
1207///USB on the go full speed
1208pub mod otg_fs_device;
1209///USB on the go full speed
1210///
1211///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#OTG_FS_PWRCLK)
1212pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
1213impl core::fmt::Debug for OTG_FS_PWRCLK {
1214    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1215        f.debug_struct("OTG_FS_PWRCLK").finish()
1216    }
1217}
1218///USB on the go full speed
1219pub mod otg_fs_pwrclk;
1220///USB on the go high speed
1221///
1222///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#OTG_HS_HOST)
1223pub type OTG_HS_HOST = crate::Periph<otg_hs_host::RegisterBlock, 0x4004_0400>;
1224impl core::fmt::Debug for OTG_HS_HOST {
1225    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1226        f.debug_struct("OTG_HS_HOST").finish()
1227    }
1228}
1229///USB on the go high speed
1230pub mod otg_hs_host;
1231///USB on the go high speed
1232///
1233///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#OTG_HS_GLOBAL)
1234pub type OTG_HS_GLOBAL = crate::Periph<otg_hs_global::RegisterBlock, 0x4004_0000>;
1235impl core::fmt::Debug for OTG_HS_GLOBAL {
1236    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1237        f.debug_struct("OTG_HS_GLOBAL").finish()
1238    }
1239}
1240///USB on the go high speed
1241pub mod otg_hs_global;
1242///USB on the go high speed
1243///
1244///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#OTG_HS_PWRCLK)
1245pub type OTG_HS_PWRCLK = crate::Periph<otg_hs_pwrclk::RegisterBlock, 0x4004_0e00>;
1246impl core::fmt::Debug for OTG_HS_PWRCLK {
1247    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1248        f.debug_struct("OTG_HS_PWRCLK").finish()
1249    }
1250}
1251///USB on the go high speed
1252pub mod otg_hs_pwrclk;
1253///USB on the go high speed
1254///
1255///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#OTG_HS_DEVICE)
1256pub type OTG_HS_DEVICE = crate::Periph<otg_hs_device::RegisterBlock, 0x4004_0800>;
1257impl core::fmt::Debug for OTG_HS_DEVICE {
1258    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1259        f.debug_struct("OTG_HS_DEVICE").finish()
1260    }
1261}
1262///USB on the go high speed
1263pub mod otg_hs_device;
1264///Window watchdog
1265///
1266///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#WWDG)
1267pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
1268impl core::fmt::Debug for WWDG {
1269    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1270        f.debug_struct("WWDG").finish()
1271    }
1272}
1273///Window watchdog
1274pub mod wwdg;
1275#[no_mangle]
1276static mut DEVICE_PERIPHERALS: bool = false;
1277/// All the peripherals.
1278#[allow(non_snake_case)]
1279pub struct Peripherals {
1280    ///TIM1
1281    pub TIM1: TIM1,
1282    ///TIM8
1283    pub TIM8: TIM8,
1284    ///ADC2
1285    pub ADC2: ADC2,
1286    ///ADC1
1287    pub ADC1: ADC1,
1288    ///ADC3
1289    pub ADC3: ADC3,
1290    ///TIM6
1291    pub TIM6: TIM6,
1292    ///TIM7
1293    pub TIM7: TIM7,
1294    ///ADC_Common
1295    pub ADC_COMMON: ADC_COMMON,
1296    ///CAN1
1297    pub CAN1: CAN1,
1298    ///CRC
1299    pub CRC: CRC,
1300    ///CRYP
1301    pub CRYP: CRYP,
1302    ///DBGMCU
1303    pub DBGMCU: DBGMCU,
1304    ///DAC
1305    pub DAC: DAC,
1306    ///DMA2
1307    pub DMA2: DMA2,
1308    ///DMA1
1309    pub DMA1: DMA1,
1310    ///EXTI
1311    pub EXTI: EXTI,
1312    ///FLASH
1313    pub FLASH: FLASH,
1314    ///FMC
1315    pub FMC: FMC,
1316    ///TIM9
1317    pub TIM9: TIM9,
1318    ///TIM12
1319    pub TIM12: TIM12,
1320    ///TIM2
1321    pub TIM2: TIM2,
1322    ///TIM3
1323    pub TIM3: TIM3,
1324    ///TIM4
1325    pub TIM4: TIM4,
1326    ///TIM5
1327    pub TIM5: TIM5,
1328    ///GPIOH
1329    pub GPIOH: GPIOH,
1330    ///GPIOF
1331    pub GPIOF: GPIOF,
1332    ///GPIOG
1333    pub GPIOG: GPIOG,
1334    ///GPIOI
1335    pub GPIOI: GPIOI,
1336    ///GPIOE
1337    pub GPIOE: GPIOE,
1338    ///GPIOD
1339    pub GPIOD: GPIOD,
1340    ///GPIOC
1341    pub GPIOC: GPIOC,
1342    ///GPIOB
1343    pub GPIOB: GPIOB,
1344    ///GPIOA
1345    pub GPIOA: GPIOA,
1346    ///TIM13
1347    pub TIM13: TIM13,
1348    ///TIM14
1349    pub TIM14: TIM14,
1350    ///TIM10
1351    pub TIM10: TIM10,
1352    ///TIM11
1353    pub TIM11: TIM11,
1354    ///IWDG
1355    pub IWDG: IWDG,
1356    ///I2C1
1357    pub I2C1: I2C1,
1358    ///I2C2
1359    pub I2C2: I2C2,
1360    ///I2C3
1361    pub I2C3: I2C3,
1362    ///LPTIM1
1363    pub LPTIM1: LPTIM1,
1364    ///PWR
1365    pub PWR: PWR,
1366    ///QUADSPI
1367    pub QUADSPI: QUADSPI,
1368    ///RNG
1369    pub RNG: RNG,
1370    ///RTC
1371    pub RTC: RTC,
1372    ///RCC
1373    pub RCC: RCC,
1374    ///SDMMC1
1375    pub SDMMC1: SDMMC1,
1376    ///SDMMC2
1377    pub SDMMC2: SDMMC2,
1378    ///SAI1
1379    pub SAI1: SAI1,
1380    ///SAI2
1381    pub SAI2: SAI2,
1382    ///SPI1
1383    pub SPI1: SPI1,
1384    ///SPI5
1385    pub SPI5: SPI5,
1386    ///SPI2
1387    pub SPI2: SPI2,
1388    ///SPI4
1389    pub SPI4: SPI4,
1390    ///SPI3
1391    pub SPI3: SPI3,
1392    ///SYSCFG
1393    pub SYSCFG: SYSCFG,
1394    ///USART1
1395    pub USART1: USART1,
1396    ///USART3
1397    pub USART3: USART3,
1398    ///USART6
1399    pub USART6: USART6,
1400    ///UART8
1401    pub UART8: UART8,
1402    ///USART2
1403    pub USART2: USART2,
1404    ///UART7
1405    pub UART7: UART7,
1406    ///UART4
1407    pub UART4: UART4,
1408    ///UART5
1409    pub UART5: UART5,
1410    ///OTG_FS_GLOBAL
1411    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
1412    ///OTG_FS_HOST
1413    pub OTG_FS_HOST: OTG_FS_HOST,
1414    ///OTG_FS_DEVICE
1415    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
1416    ///OTG_FS_PWRCLK
1417    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
1418    ///OTG_HS_HOST
1419    pub OTG_HS_HOST: OTG_HS_HOST,
1420    ///OTG_HS_GLOBAL
1421    pub OTG_HS_GLOBAL: OTG_HS_GLOBAL,
1422    ///OTG_HS_PWRCLK
1423    pub OTG_HS_PWRCLK: OTG_HS_PWRCLK,
1424    ///OTG_HS_DEVICE
1425    pub OTG_HS_DEVICE: OTG_HS_DEVICE,
1426    ///WWDG
1427    pub WWDG: WWDG,
1428}
1429impl Peripherals {
1430    /// Returns all the peripherals *once*.
1431    #[cfg(feature = "critical-section")]
1432    #[inline]
1433    pub fn take() -> Option<Self> {
1434        critical_section::with(|_| {
1435            if unsafe { DEVICE_PERIPHERALS } {
1436                return None;
1437            }
1438            Some(unsafe { Peripherals::steal() })
1439        })
1440    }
1441    /// Unchecked version of `Peripherals::take`.
1442    ///
1443    /// # Safety
1444    ///
1445    /// Each of the returned peripherals must be used at most once.
1446    #[inline]
1447    pub unsafe fn steal() -> Self {
1448        DEVICE_PERIPHERALS = true;
1449        Peripherals {
1450            TIM1: TIM1::steal(),
1451            TIM8: TIM8::steal(),
1452            ADC2: ADC2::steal(),
1453            ADC1: ADC1::steal(),
1454            ADC3: ADC3::steal(),
1455            TIM6: TIM6::steal(),
1456            TIM7: TIM7::steal(),
1457            ADC_COMMON: ADC_COMMON::steal(),
1458            CAN1: CAN1::steal(),
1459            CRC: CRC::steal(),
1460            CRYP: CRYP::steal(),
1461            DBGMCU: DBGMCU::steal(),
1462            DAC: DAC::steal(),
1463            DMA2: DMA2::steal(),
1464            DMA1: DMA1::steal(),
1465            EXTI: EXTI::steal(),
1466            FLASH: FLASH::steal(),
1467            FMC: FMC::steal(),
1468            TIM9: TIM9::steal(),
1469            TIM12: TIM12::steal(),
1470            TIM2: TIM2::steal(),
1471            TIM3: TIM3::steal(),
1472            TIM4: TIM4::steal(),
1473            TIM5: TIM5::steal(),
1474            GPIOH: GPIOH::steal(),
1475            GPIOF: GPIOF::steal(),
1476            GPIOG: GPIOG::steal(),
1477            GPIOI: GPIOI::steal(),
1478            GPIOE: GPIOE::steal(),
1479            GPIOD: GPIOD::steal(),
1480            GPIOC: GPIOC::steal(),
1481            GPIOB: GPIOB::steal(),
1482            GPIOA: GPIOA::steal(),
1483            TIM13: TIM13::steal(),
1484            TIM14: TIM14::steal(),
1485            TIM10: TIM10::steal(),
1486            TIM11: TIM11::steal(),
1487            IWDG: IWDG::steal(),
1488            I2C1: I2C1::steal(),
1489            I2C2: I2C2::steal(),
1490            I2C3: I2C3::steal(),
1491            LPTIM1: LPTIM1::steal(),
1492            PWR: PWR::steal(),
1493            QUADSPI: QUADSPI::steal(),
1494            RNG: RNG::steal(),
1495            RTC: RTC::steal(),
1496            RCC: RCC::steal(),
1497            SDMMC1: SDMMC1::steal(),
1498            SDMMC2: SDMMC2::steal(),
1499            SAI1: SAI1::steal(),
1500            SAI2: SAI2::steal(),
1501            SPI1: SPI1::steal(),
1502            SPI5: SPI5::steal(),
1503            SPI2: SPI2::steal(),
1504            SPI4: SPI4::steal(),
1505            SPI3: SPI3::steal(),
1506            SYSCFG: SYSCFG::steal(),
1507            USART1: USART1::steal(),
1508            USART3: USART3::steal(),
1509            USART6: USART6::steal(),
1510            UART8: UART8::steal(),
1511            USART2: USART2::steal(),
1512            UART7: UART7::steal(),
1513            UART4: UART4::steal(),
1514            UART5: UART5::steal(),
1515            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1516            OTG_FS_HOST: OTG_FS_HOST::steal(),
1517            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1518            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1519            OTG_HS_HOST: OTG_HS_HOST::steal(),
1520            OTG_HS_GLOBAL: OTG_HS_GLOBAL::steal(),
1521            OTG_HS_PWRCLK: OTG_HS_PWRCLK::steal(),
1522            OTG_HS_DEVICE: OTG_HS_DEVICE::steal(),
1523            WWDG: WWDG::steal(),
1524        }
1525    }
1526}
stm32f7_staging/stm32f733/mod.rs

stm32f7_staging/stm32f733/
mod.rs
