stm32f7_staging/stm32f733/gpioa/
ospeedr.rs

1///Register `OSPEEDR` reader
2pub type R = crate::R<OSPEEDRrs>;
3///Register `OSPEEDR` writer
4pub type W = crate::W<OSPEEDRrs>;
5/**Port x configuration pin %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum OUTPUT_SPEED {
12    ///0: Low speed
13    LowSpeed = 0,
14    ///1: Medium speed
15    MediumSpeed = 1,
16    ///2: High speed
17    HighSpeed = 2,
18    ///3: Very high speed
19    VeryHighSpeed = 3,
20}
21impl From<OUTPUT_SPEED> for u8 {
22    #[inline(always)]
23    fn from(variant: OUTPUT_SPEED) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for OUTPUT_SPEED {
28    type Ux = u8;
29}
30impl crate::IsEnum for OUTPUT_SPEED {}
31///Field `OSPEEDR(0-15)` reader - Port x configuration pin %s
32pub type OSPEEDR_R = crate::FieldReader<OUTPUT_SPEED>;
33impl OSPEEDR_R {
34    ///Get enumerated values variant
35    #[inline(always)]
36    pub const fn variant(&self) -> OUTPUT_SPEED {
37        match self.bits {
38            0 => OUTPUT_SPEED::LowSpeed,
39            1 => OUTPUT_SPEED::MediumSpeed,
40            2 => OUTPUT_SPEED::HighSpeed,
41            3 => OUTPUT_SPEED::VeryHighSpeed,
42            _ => unreachable!(),
43        }
44    }
45    ///Low speed
46    #[inline(always)]
47    pub fn is_low_speed(&self) -> bool {
48        *self == OUTPUT_SPEED::LowSpeed
49    }
50    ///Medium speed
51    #[inline(always)]
52    pub fn is_medium_speed(&self) -> bool {
53        *self == OUTPUT_SPEED::MediumSpeed
54    }
55    ///High speed
56    #[inline(always)]
57    pub fn is_high_speed(&self) -> bool {
58        *self == OUTPUT_SPEED::HighSpeed
59    }
60    ///Very high speed
61    #[inline(always)]
62    pub fn is_very_high_speed(&self) -> bool {
63        *self == OUTPUT_SPEED::VeryHighSpeed
64    }
65}
66///Field `OSPEEDR(0-15)` writer - Port x configuration pin %s
67pub type OSPEEDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OUTPUT_SPEED, crate::Safe>;
68impl<'a, REG> OSPEEDR_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    ///Low speed
74    #[inline(always)]
75    pub fn low_speed(self) -> &'a mut crate::W<REG> {
76        self.variant(OUTPUT_SPEED::LowSpeed)
77    }
78    ///Medium speed
79    #[inline(always)]
80    pub fn medium_speed(self) -> &'a mut crate::W<REG> {
81        self.variant(OUTPUT_SPEED::MediumSpeed)
82    }
83    ///High speed
84    #[inline(always)]
85    pub fn high_speed(self) -> &'a mut crate::W<REG> {
86        self.variant(OUTPUT_SPEED::HighSpeed)
87    }
88    ///Very high speed
89    #[inline(always)]
90    pub fn very_high_speed(self) -> &'a mut crate::W<REG> {
91        self.variant(OUTPUT_SPEED::VeryHighSpeed)
92    }
93}
94impl R {
95    ///Port x configuration pin (0-15)
96    ///
97    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
98    #[inline(always)]
99    pub fn ospeedr(&self, n: u8) -> OSPEEDR_R {
100        #[allow(clippy::no_effect)]
101        [(); 16][n as usize];
102        OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8)
103    }
104    ///Iterator for array of:
105    ///Port x configuration pin (0-15)
106    #[inline(always)]
107    pub fn ospeedr_iter(&self) -> impl Iterator<Item = OSPEEDR_R> + '_ {
108        (0..16).map(move |n| OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8))
109    }
110    ///Bits 0:1 - Port x configuration pin 0
111    #[inline(always)]
112    pub fn ospeedr0(&self) -> OSPEEDR_R {
113        OSPEEDR_R::new((self.bits & 3) as u8)
114    }
115    ///Bits 2:3 - Port x configuration pin 1
116    #[inline(always)]
117    pub fn ospeedr1(&self) -> OSPEEDR_R {
118        OSPEEDR_R::new(((self.bits >> 2) & 3) as u8)
119    }
120    ///Bits 4:5 - Port x configuration pin 2
121    #[inline(always)]
122    pub fn ospeedr2(&self) -> OSPEEDR_R {
123        OSPEEDR_R::new(((self.bits >> 4) & 3) as u8)
124    }
125    ///Bits 6:7 - Port x configuration pin 3
126    #[inline(always)]
127    pub fn ospeedr3(&self) -> OSPEEDR_R {
128        OSPEEDR_R::new(((self.bits >> 6) & 3) as u8)
129    }
130    ///Bits 8:9 - Port x configuration pin 4
131    #[inline(always)]
132    pub fn ospeedr4(&self) -> OSPEEDR_R {
133        OSPEEDR_R::new(((self.bits >> 8) & 3) as u8)
134    }
135    ///Bits 10:11 - Port x configuration pin 5
136    #[inline(always)]
137    pub fn ospeedr5(&self) -> OSPEEDR_R {
138        OSPEEDR_R::new(((self.bits >> 10) & 3) as u8)
139    }
140    ///Bits 12:13 - Port x configuration pin 6
141    #[inline(always)]
142    pub fn ospeedr6(&self) -> OSPEEDR_R {
143        OSPEEDR_R::new(((self.bits >> 12) & 3) as u8)
144    }
145    ///Bits 14:15 - Port x configuration pin 7
146    #[inline(always)]
147    pub fn ospeedr7(&self) -> OSPEEDR_R {
148        OSPEEDR_R::new(((self.bits >> 14) & 3) as u8)
149    }
150    ///Bits 16:17 - Port x configuration pin 8
151    #[inline(always)]
152    pub fn ospeedr8(&self) -> OSPEEDR_R {
153        OSPEEDR_R::new(((self.bits >> 16) & 3) as u8)
154    }
155    ///Bits 18:19 - Port x configuration pin 9
156    #[inline(always)]
157    pub fn ospeedr9(&self) -> OSPEEDR_R {
158        OSPEEDR_R::new(((self.bits >> 18) & 3) as u8)
159    }
160    ///Bits 20:21 - Port x configuration pin 10
161    #[inline(always)]
162    pub fn ospeedr10(&self) -> OSPEEDR_R {
163        OSPEEDR_R::new(((self.bits >> 20) & 3) as u8)
164    }
165    ///Bits 22:23 - Port x configuration pin 11
166    #[inline(always)]
167    pub fn ospeedr11(&self) -> OSPEEDR_R {
168        OSPEEDR_R::new(((self.bits >> 22) & 3) as u8)
169    }
170    ///Bits 24:25 - Port x configuration pin 12
171    #[inline(always)]
172    pub fn ospeedr12(&self) -> OSPEEDR_R {
173        OSPEEDR_R::new(((self.bits >> 24) & 3) as u8)
174    }
175    ///Bits 26:27 - Port x configuration pin 13
176    #[inline(always)]
177    pub fn ospeedr13(&self) -> OSPEEDR_R {
178        OSPEEDR_R::new(((self.bits >> 26) & 3) as u8)
179    }
180    ///Bits 28:29 - Port x configuration pin 14
181    #[inline(always)]
182    pub fn ospeedr14(&self) -> OSPEEDR_R {
183        OSPEEDR_R::new(((self.bits >> 28) & 3) as u8)
184    }
185    ///Bits 30:31 - Port x configuration pin 15
186    #[inline(always)]
187    pub fn ospeedr15(&self) -> OSPEEDR_R {
188        OSPEEDR_R::new(((self.bits >> 30) & 3) as u8)
189    }
190}
191impl core::fmt::Debug for R {
192    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
193        f.debug_struct("OSPEEDR")
194            .field("ospeedr0", &self.ospeedr0())
195            .field("ospeedr1", &self.ospeedr1())
196            .field("ospeedr2", &self.ospeedr2())
197            .field("ospeedr3", &self.ospeedr3())
198            .field("ospeedr4", &self.ospeedr4())
199            .field("ospeedr5", &self.ospeedr5())
200            .field("ospeedr6", &self.ospeedr6())
201            .field("ospeedr7", &self.ospeedr7())
202            .field("ospeedr8", &self.ospeedr8())
203            .field("ospeedr9", &self.ospeedr9())
204            .field("ospeedr10", &self.ospeedr10())
205            .field("ospeedr11", &self.ospeedr11())
206            .field("ospeedr12", &self.ospeedr12())
207            .field("ospeedr13", &self.ospeedr13())
208            .field("ospeedr14", &self.ospeedr14())
209            .field("ospeedr15", &self.ospeedr15())
210            .finish()
211    }
212}
213impl W {
214    ///Port x configuration pin (0-15)
215    ///
216    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
217    #[inline(always)]
218    pub fn ospeedr(&mut self, n: u8) -> OSPEEDR_W<OSPEEDRrs> {
219        #[allow(clippy::no_effect)]
220        [(); 16][n as usize];
221        OSPEEDR_W::new(self, n * 2)
222    }
223    ///Bits 0:1 - Port x configuration pin 0
224    #[inline(always)]
225    pub fn ospeedr0(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
226        OSPEEDR_W::new(self, 0)
227    }
228    ///Bits 2:3 - Port x configuration pin 1
229    #[inline(always)]
230    pub fn ospeedr1(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
231        OSPEEDR_W::new(self, 2)
232    }
233    ///Bits 4:5 - Port x configuration pin 2
234    #[inline(always)]
235    pub fn ospeedr2(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
236        OSPEEDR_W::new(self, 4)
237    }
238    ///Bits 6:7 - Port x configuration pin 3
239    #[inline(always)]
240    pub fn ospeedr3(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
241        OSPEEDR_W::new(self, 6)
242    }
243    ///Bits 8:9 - Port x configuration pin 4
244    #[inline(always)]
245    pub fn ospeedr4(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
246        OSPEEDR_W::new(self, 8)
247    }
248    ///Bits 10:11 - Port x configuration pin 5
249    #[inline(always)]
250    pub fn ospeedr5(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
251        OSPEEDR_W::new(self, 10)
252    }
253    ///Bits 12:13 - Port x configuration pin 6
254    #[inline(always)]
255    pub fn ospeedr6(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
256        OSPEEDR_W::new(self, 12)
257    }
258    ///Bits 14:15 - Port x configuration pin 7
259    #[inline(always)]
260    pub fn ospeedr7(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
261        OSPEEDR_W::new(self, 14)
262    }
263    ///Bits 16:17 - Port x configuration pin 8
264    #[inline(always)]
265    pub fn ospeedr8(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
266        OSPEEDR_W::new(self, 16)
267    }
268    ///Bits 18:19 - Port x configuration pin 9
269    #[inline(always)]
270    pub fn ospeedr9(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
271        OSPEEDR_W::new(self, 18)
272    }
273    ///Bits 20:21 - Port x configuration pin 10
274    #[inline(always)]
275    pub fn ospeedr10(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
276        OSPEEDR_W::new(self, 20)
277    }
278    ///Bits 22:23 - Port x configuration pin 11
279    #[inline(always)]
280    pub fn ospeedr11(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
281        OSPEEDR_W::new(self, 22)
282    }
283    ///Bits 24:25 - Port x configuration pin 12
284    #[inline(always)]
285    pub fn ospeedr12(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
286        OSPEEDR_W::new(self, 24)
287    }
288    ///Bits 26:27 - Port x configuration pin 13
289    #[inline(always)]
290    pub fn ospeedr13(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
291        OSPEEDR_W::new(self, 26)
292    }
293    ///Bits 28:29 - Port x configuration pin 14
294    #[inline(always)]
295    pub fn ospeedr14(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
296        OSPEEDR_W::new(self, 28)
297    }
298    ///Bits 30:31 - Port x configuration pin 15
299    #[inline(always)]
300    pub fn ospeedr15(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
301        OSPEEDR_W::new(self, 30)
302    }
303}
304/**GPIO port output speed register
305
306You can [`read`](crate::Reg::read) this register and get [`ospeedr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ospeedr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
307
308See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOA:OSPEEDR)*/
309pub struct OSPEEDRrs;
310impl crate::RegisterSpec for OSPEEDRrs {
311    type Ux = u32;
312}
313///`read()` method returns [`ospeedr::R`](R) reader structure
314impl crate::Readable for OSPEEDRrs {}
315///`write(|w| ..)` method takes [`ospeedr::W`](W) writer structure
316impl crate::Writable for OSPEEDRrs {
317    type Safety = crate::Unsafe;
318}
319///`reset()` method sets OSPEEDR to value 0
320impl crate::Resettable for OSPEEDRrs {}
stm32f7_staging/stm32f733/gpioa/ospeedr.rs

stm32f7_staging/stm32f733/gpioa/
ospeedr.rs
