stm32f7_staging/stm32f733/gpioa/
odr.rs

1///Register `ODR` reader
2pub type R = crate::R<ODRrs>;
3///Register `ODR` writer
4pub type W = crate::W<ODRrs>;
5/**Port output data pin %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum OUTPUT_DATA {
11    ///0: Set output to logic low
12    Low = 0,
13    ///1: Set output to logic high
14    High = 1,
15}
16impl From<OUTPUT_DATA> for bool {
17    #[inline(always)]
18    fn from(variant: OUTPUT_DATA) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `ODR(0-15)` reader - Port output data pin %s
23pub type ODR_R = crate::BitReader<OUTPUT_DATA>;
24impl ODR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> OUTPUT_DATA {
28        match self.bits {
29            false => OUTPUT_DATA::Low,
30            true => OUTPUT_DATA::High,
31        }
32    }
33    ///Set output to logic low
34    #[inline(always)]
35    pub fn is_low(&self) -> bool {
36        *self == OUTPUT_DATA::Low
37    }
38    ///Set output to logic high
39    #[inline(always)]
40    pub fn is_high(&self) -> bool {
41        *self == OUTPUT_DATA::High
42    }
43}
44///Field `ODR(0-15)` writer - Port output data pin %s
45pub type ODR_W<'a, REG> = crate::BitWriter<'a, REG, OUTPUT_DATA>;
46impl<'a, REG> ODR_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Set output to logic low
51    #[inline(always)]
52    pub fn low(self) -> &'a mut crate::W<REG> {
53        self.variant(OUTPUT_DATA::Low)
54    }
55    ///Set output to logic high
56    #[inline(always)]
57    pub fn high(self) -> &'a mut crate::W<REG> {
58        self.variant(OUTPUT_DATA::High)
59    }
60}
61impl R {
62    ///Port output data pin (0-15)
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ODR0` field.</div>
65    #[inline(always)]
66    pub fn odr(&self, n: u8) -> ODR_R {
67        #[allow(clippy::no_effect)]
68        [(); 16][n as usize];
69        ODR_R::new(((self.bits >> n) & 1) != 0)
70    }
71    ///Iterator for array of:
72    ///Port output data pin (0-15)
73    #[inline(always)]
74    pub fn odr_iter(&self) -> impl Iterator<Item = ODR_R> + '_ {
75        (0..16).map(move |n| ODR_R::new(((self.bits >> n) & 1) != 0))
76    }
77    ///Bit 0 - Port output data pin 0
78    #[inline(always)]
79    pub fn odr0(&self) -> ODR_R {
80        ODR_R::new((self.bits & 1) != 0)
81    }
82    ///Bit 1 - Port output data pin 1
83    #[inline(always)]
84    pub fn odr1(&self) -> ODR_R {
85        ODR_R::new(((self.bits >> 1) & 1) != 0)
86    }
87    ///Bit 2 - Port output data pin 2
88    #[inline(always)]
89    pub fn odr2(&self) -> ODR_R {
90        ODR_R::new(((self.bits >> 2) & 1) != 0)
91    }
92    ///Bit 3 - Port output data pin 3
93    #[inline(always)]
94    pub fn odr3(&self) -> ODR_R {
95        ODR_R::new(((self.bits >> 3) & 1) != 0)
96    }
97    ///Bit 4 - Port output data pin 4
98    #[inline(always)]
99    pub fn odr4(&self) -> ODR_R {
100        ODR_R::new(((self.bits >> 4) & 1) != 0)
101    }
102    ///Bit 5 - Port output data pin 5
103    #[inline(always)]
104    pub fn odr5(&self) -> ODR_R {
105        ODR_R::new(((self.bits >> 5) & 1) != 0)
106    }
107    ///Bit 6 - Port output data pin 6
108    #[inline(always)]
109    pub fn odr6(&self) -> ODR_R {
110        ODR_R::new(((self.bits >> 6) & 1) != 0)
111    }
112    ///Bit 7 - Port output data pin 7
113    #[inline(always)]
114    pub fn odr7(&self) -> ODR_R {
115        ODR_R::new(((self.bits >> 7) & 1) != 0)
116    }
117    ///Bit 8 - Port output data pin 8
118    #[inline(always)]
119    pub fn odr8(&self) -> ODR_R {
120        ODR_R::new(((self.bits >> 8) & 1) != 0)
121    }
122    ///Bit 9 - Port output data pin 9
123    #[inline(always)]
124    pub fn odr9(&self) -> ODR_R {
125        ODR_R::new(((self.bits >> 9) & 1) != 0)
126    }
127    ///Bit 10 - Port output data pin 10
128    #[inline(always)]
129    pub fn odr10(&self) -> ODR_R {
130        ODR_R::new(((self.bits >> 10) & 1) != 0)
131    }
132    ///Bit 11 - Port output data pin 11
133    #[inline(always)]
134    pub fn odr11(&self) -> ODR_R {
135        ODR_R::new(((self.bits >> 11) & 1) != 0)
136    }
137    ///Bit 12 - Port output data pin 12
138    #[inline(always)]
139    pub fn odr12(&self) -> ODR_R {
140        ODR_R::new(((self.bits >> 12) & 1) != 0)
141    }
142    ///Bit 13 - Port output data pin 13
143    #[inline(always)]
144    pub fn odr13(&self) -> ODR_R {
145        ODR_R::new(((self.bits >> 13) & 1) != 0)
146    }
147    ///Bit 14 - Port output data pin 14
148    #[inline(always)]
149    pub fn odr14(&self) -> ODR_R {
150        ODR_R::new(((self.bits >> 14) & 1) != 0)
151    }
152    ///Bit 15 - Port output data pin 15
153    #[inline(always)]
154    pub fn odr15(&self) -> ODR_R {
155        ODR_R::new(((self.bits >> 15) & 1) != 0)
156    }
157}
158impl core::fmt::Debug for R {
159    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
160        f.debug_struct("ODR")
161            .field("odr0", &self.odr0())
162            .field("odr1", &self.odr1())
163            .field("odr2", &self.odr2())
164            .field("odr3", &self.odr3())
165            .field("odr4", &self.odr4())
166            .field("odr5", &self.odr5())
167            .field("odr6", &self.odr6())
168            .field("odr7", &self.odr7())
169            .field("odr8", &self.odr8())
170            .field("odr9", &self.odr9())
171            .field("odr10", &self.odr10())
172            .field("odr11", &self.odr11())
173            .field("odr12", &self.odr12())
174            .field("odr13", &self.odr13())
175            .field("odr14", &self.odr14())
176            .field("odr15", &self.odr15())
177            .finish()
178    }
179}
180impl W {
181    ///Port output data pin (0-15)
182    ///
183    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ODR0` field.</div>
184    #[inline(always)]
185    pub fn odr(&mut self, n: u8) -> ODR_W<ODRrs> {
186        #[allow(clippy::no_effect)]
187        [(); 16][n as usize];
188        ODR_W::new(self, n)
189    }
190    ///Bit 0 - Port output data pin 0
191    #[inline(always)]
192    pub fn odr0(&mut self) -> ODR_W<ODRrs> {
193        ODR_W::new(self, 0)
194    }
195    ///Bit 1 - Port output data pin 1
196    #[inline(always)]
197    pub fn odr1(&mut self) -> ODR_W<ODRrs> {
198        ODR_W::new(self, 1)
199    }
200    ///Bit 2 - Port output data pin 2
201    #[inline(always)]
202    pub fn odr2(&mut self) -> ODR_W<ODRrs> {
203        ODR_W::new(self, 2)
204    }
205    ///Bit 3 - Port output data pin 3
206    #[inline(always)]
207    pub fn odr3(&mut self) -> ODR_W<ODRrs> {
208        ODR_W::new(self, 3)
209    }
210    ///Bit 4 - Port output data pin 4
211    #[inline(always)]
212    pub fn odr4(&mut self) -> ODR_W<ODRrs> {
213        ODR_W::new(self, 4)
214    }
215    ///Bit 5 - Port output data pin 5
216    #[inline(always)]
217    pub fn odr5(&mut self) -> ODR_W<ODRrs> {
218        ODR_W::new(self, 5)
219    }
220    ///Bit 6 - Port output data pin 6
221    #[inline(always)]
222    pub fn odr6(&mut self) -> ODR_W<ODRrs> {
223        ODR_W::new(self, 6)
224    }
225    ///Bit 7 - Port output data pin 7
226    #[inline(always)]
227    pub fn odr7(&mut self) -> ODR_W<ODRrs> {
228        ODR_W::new(self, 7)
229    }
230    ///Bit 8 - Port output data pin 8
231    #[inline(always)]
232    pub fn odr8(&mut self) -> ODR_W<ODRrs> {
233        ODR_W::new(self, 8)
234    }
235    ///Bit 9 - Port output data pin 9
236    #[inline(always)]
237    pub fn odr9(&mut self) -> ODR_W<ODRrs> {
238        ODR_W::new(self, 9)
239    }
240    ///Bit 10 - Port output data pin 10
241    #[inline(always)]
242    pub fn odr10(&mut self) -> ODR_W<ODRrs> {
243        ODR_W::new(self, 10)
244    }
245    ///Bit 11 - Port output data pin 11
246    #[inline(always)]
247    pub fn odr11(&mut self) -> ODR_W<ODRrs> {
248        ODR_W::new(self, 11)
249    }
250    ///Bit 12 - Port output data pin 12
251    #[inline(always)]
252    pub fn odr12(&mut self) -> ODR_W<ODRrs> {
253        ODR_W::new(self, 12)
254    }
255    ///Bit 13 - Port output data pin 13
256    #[inline(always)]
257    pub fn odr13(&mut self) -> ODR_W<ODRrs> {
258        ODR_W::new(self, 13)
259    }
260    ///Bit 14 - Port output data pin 14
261    #[inline(always)]
262    pub fn odr14(&mut self) -> ODR_W<ODRrs> {
263        ODR_W::new(self, 14)
264    }
265    ///Bit 15 - Port output data pin 15
266    #[inline(always)]
267    pub fn odr15(&mut self) -> ODR_W<ODRrs> {
268        ODR_W::new(self, 15)
269    }
270}
271/**GPIO port output data register
272
273You can [`read`](crate::Reg::read) this register and get [`odr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`odr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
274
275See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#GPIOA:ODR)*/
276pub struct ODRrs;
277impl crate::RegisterSpec for ODRrs {
278    type Ux = u32;
279}
280///`read()` method returns [`odr::R`](R) reader structure
281impl crate::Readable for ODRrs {}
282///`write(|w| ..)` method takes [`odr::W`](W) writer structure
283impl crate::Writable for ODRrs {
284    type Safety = crate::Unsafe;
285}
286///`reset()` method sets ODR to value 0
287impl crate::Resettable for ODRrs {}
stm32f7_staging/stm32f733/gpioa/odr.rs

stm32f7_staging/stm32f733/gpioa/
odr.rs
