stm32f7_staging/stm32f733/exti/
imr.rs

1///Register `IMR` reader
2pub type R = crate::R<IMRrs>;
3///Register `IMR` writer
4pub type W = crate::W<IMRrs>;
5/**Interrupt Mask on line %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum INTERRUPT_MASK {
11    ///0: Interrupt request line is masked
12    Masked = 0,
13    ///1: Interrupt request line is unmasked
14    Unmasked = 1,
15}
16impl From<INTERRUPT_MASK> for bool {
17    #[inline(always)]
18    fn from(variant: INTERRUPT_MASK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `IM(0-23)` reader - Interrupt Mask on line %s
23pub type IM_R = crate::BitReader<INTERRUPT_MASK>;
24impl IM_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> INTERRUPT_MASK {
28        match self.bits {
29            false => INTERRUPT_MASK::Masked,
30            true => INTERRUPT_MASK::Unmasked,
31        }
32    }
33    ///Interrupt request line is masked
34    #[inline(always)]
35    pub fn is_masked(&self) -> bool {
36        *self == INTERRUPT_MASK::Masked
37    }
38    ///Interrupt request line is unmasked
39    #[inline(always)]
40    pub fn is_unmasked(&self) -> bool {
41        *self == INTERRUPT_MASK::Unmasked
42    }
43}
44///Field `IM(0-23)` writer - Interrupt Mask on line %s
45pub type IM_W<'a, REG> = crate::BitWriter<'a, REG, INTERRUPT_MASK>;
46impl<'a, REG> IM_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Interrupt request line is masked
51    #[inline(always)]
52    pub fn masked(self) -> &'a mut crate::W<REG> {
53        self.variant(INTERRUPT_MASK::Masked)
54    }
55    ///Interrupt request line is unmasked
56    #[inline(always)]
57    pub fn unmasked(self) -> &'a mut crate::W<REG> {
58        self.variant(INTERRUPT_MASK::Unmasked)
59    }
60}
61impl R {
62    ///Interrupt Mask on line (0-23)
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IM0` field.</div>
65    #[inline(always)]
66    pub fn im(&self, n: u8) -> IM_R {
67        #[allow(clippy::no_effect)]
68        [(); 24][n as usize];
69        IM_R::new(((self.bits >> n) & 1) != 0)
70    }
71    ///Iterator for array of:
72    ///Interrupt Mask on line (0-23)
73    #[inline(always)]
74    pub fn im_iter(&self) -> impl Iterator<Item = IM_R> + '_ {
75        (0..24).map(move |n| IM_R::new(((self.bits >> n) & 1) != 0))
76    }
77    ///Bit 0 - Interrupt Mask on line 0
78    #[inline(always)]
79    pub fn im0(&self) -> IM_R {
80        IM_R::new((self.bits & 1) != 0)
81    }
82    ///Bit 1 - Interrupt Mask on line 1
83    #[inline(always)]
84    pub fn im1(&self) -> IM_R {
85        IM_R::new(((self.bits >> 1) & 1) != 0)
86    }
87    ///Bit 2 - Interrupt Mask on line 2
88    #[inline(always)]
89    pub fn im2(&self) -> IM_R {
90        IM_R::new(((self.bits >> 2) & 1) != 0)
91    }
92    ///Bit 3 - Interrupt Mask on line 3
93    #[inline(always)]
94    pub fn im3(&self) -> IM_R {
95        IM_R::new(((self.bits >> 3) & 1) != 0)
96    }
97    ///Bit 4 - Interrupt Mask on line 4
98    #[inline(always)]
99    pub fn im4(&self) -> IM_R {
100        IM_R::new(((self.bits >> 4) & 1) != 0)
101    }
102    ///Bit 5 - Interrupt Mask on line 5
103    #[inline(always)]
104    pub fn im5(&self) -> IM_R {
105        IM_R::new(((self.bits >> 5) & 1) != 0)
106    }
107    ///Bit 6 - Interrupt Mask on line 6
108    #[inline(always)]
109    pub fn im6(&self) -> IM_R {
110        IM_R::new(((self.bits >> 6) & 1) != 0)
111    }
112    ///Bit 7 - Interrupt Mask on line 7
113    #[inline(always)]
114    pub fn im7(&self) -> IM_R {
115        IM_R::new(((self.bits >> 7) & 1) != 0)
116    }
117    ///Bit 8 - Interrupt Mask on line 8
118    #[inline(always)]
119    pub fn im8(&self) -> IM_R {
120        IM_R::new(((self.bits >> 8) & 1) != 0)
121    }
122    ///Bit 9 - Interrupt Mask on line 9
123    #[inline(always)]
124    pub fn im9(&self) -> IM_R {
125        IM_R::new(((self.bits >> 9) & 1) != 0)
126    }
127    ///Bit 10 - Interrupt Mask on line 10
128    #[inline(always)]
129    pub fn im10(&self) -> IM_R {
130        IM_R::new(((self.bits >> 10) & 1) != 0)
131    }
132    ///Bit 11 - Interrupt Mask on line 11
133    #[inline(always)]
134    pub fn im11(&self) -> IM_R {
135        IM_R::new(((self.bits >> 11) & 1) != 0)
136    }
137    ///Bit 12 - Interrupt Mask on line 12
138    #[inline(always)]
139    pub fn im12(&self) -> IM_R {
140        IM_R::new(((self.bits >> 12) & 1) != 0)
141    }
142    ///Bit 13 - Interrupt Mask on line 13
143    #[inline(always)]
144    pub fn im13(&self) -> IM_R {
145        IM_R::new(((self.bits >> 13) & 1) != 0)
146    }
147    ///Bit 14 - Interrupt Mask on line 14
148    #[inline(always)]
149    pub fn im14(&self) -> IM_R {
150        IM_R::new(((self.bits >> 14) & 1) != 0)
151    }
152    ///Bit 15 - Interrupt Mask on line 15
153    #[inline(always)]
154    pub fn im15(&self) -> IM_R {
155        IM_R::new(((self.bits >> 15) & 1) != 0)
156    }
157    ///Bit 16 - Interrupt Mask on line 16
158    #[inline(always)]
159    pub fn im16(&self) -> IM_R {
160        IM_R::new(((self.bits >> 16) & 1) != 0)
161    }
162    ///Bit 17 - Interrupt Mask on line 17
163    #[inline(always)]
164    pub fn im17(&self) -> IM_R {
165        IM_R::new(((self.bits >> 17) & 1) != 0)
166    }
167    ///Bit 18 - Interrupt Mask on line 18
168    #[inline(always)]
169    pub fn im18(&self) -> IM_R {
170        IM_R::new(((self.bits >> 18) & 1) != 0)
171    }
172    ///Bit 19 - Interrupt Mask on line 19
173    #[inline(always)]
174    pub fn im19(&self) -> IM_R {
175        IM_R::new(((self.bits >> 19) & 1) != 0)
176    }
177    ///Bit 20 - Interrupt Mask on line 20
178    #[inline(always)]
179    pub fn im20(&self) -> IM_R {
180        IM_R::new(((self.bits >> 20) & 1) != 0)
181    }
182    ///Bit 21 - Interrupt Mask on line 21
183    #[inline(always)]
184    pub fn im21(&self) -> IM_R {
185        IM_R::new(((self.bits >> 21) & 1) != 0)
186    }
187    ///Bit 22 - Interrupt Mask on line 22
188    #[inline(always)]
189    pub fn im22(&self) -> IM_R {
190        IM_R::new(((self.bits >> 22) & 1) != 0)
191    }
192    ///Bit 23 - Interrupt Mask on line 23
193    #[inline(always)]
194    pub fn im23(&self) -> IM_R {
195        IM_R::new(((self.bits >> 23) & 1) != 0)
196    }
197}
198impl core::fmt::Debug for R {
199    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
200        f.debug_struct("IMR")
201            .field("im0", &self.im0())
202            .field("im1", &self.im1())
203            .field("im2", &self.im2())
204            .field("im3", &self.im3())
205            .field("im4", &self.im4())
206            .field("im5", &self.im5())
207            .field("im6", &self.im6())
208            .field("im7", &self.im7())
209            .field("im8", &self.im8())
210            .field("im9", &self.im9())
211            .field("im10", &self.im10())
212            .field("im11", &self.im11())
213            .field("im12", &self.im12())
214            .field("im13", &self.im13())
215            .field("im14", &self.im14())
216            .field("im15", &self.im15())
217            .field("im16", &self.im16())
218            .field("im17", &self.im17())
219            .field("im18", &self.im18())
220            .field("im19", &self.im19())
221            .field("im20", &self.im20())
222            .field("im21", &self.im21())
223            .field("im22", &self.im22())
224            .field("im23", &self.im23())
225            .finish()
226    }
227}
228impl W {
229    ///Interrupt Mask on line (0-23)
230    ///
231    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IM0` field.</div>
232    #[inline(always)]
233    pub fn im(&mut self, n: u8) -> IM_W<IMRrs> {
234        #[allow(clippy::no_effect)]
235        [(); 24][n as usize];
236        IM_W::new(self, n)
237    }
238    ///Bit 0 - Interrupt Mask on line 0
239    #[inline(always)]
240    pub fn im0(&mut self) -> IM_W<IMRrs> {
241        IM_W::new(self, 0)
242    }
243    ///Bit 1 - Interrupt Mask on line 1
244    #[inline(always)]
245    pub fn im1(&mut self) -> IM_W<IMRrs> {
246        IM_W::new(self, 1)
247    }
248    ///Bit 2 - Interrupt Mask on line 2
249    #[inline(always)]
250    pub fn im2(&mut self) -> IM_W<IMRrs> {
251        IM_W::new(self, 2)
252    }
253    ///Bit 3 - Interrupt Mask on line 3
254    #[inline(always)]
255    pub fn im3(&mut self) -> IM_W<IMRrs> {
256        IM_W::new(self, 3)
257    }
258    ///Bit 4 - Interrupt Mask on line 4
259    #[inline(always)]
260    pub fn im4(&mut self) -> IM_W<IMRrs> {
261        IM_W::new(self, 4)
262    }
263    ///Bit 5 - Interrupt Mask on line 5
264    #[inline(always)]
265    pub fn im5(&mut self) -> IM_W<IMRrs> {
266        IM_W::new(self, 5)
267    }
268    ///Bit 6 - Interrupt Mask on line 6
269    #[inline(always)]
270    pub fn im6(&mut self) -> IM_W<IMRrs> {
271        IM_W::new(self, 6)
272    }
273    ///Bit 7 - Interrupt Mask on line 7
274    #[inline(always)]
275    pub fn im7(&mut self) -> IM_W<IMRrs> {
276        IM_W::new(self, 7)
277    }
278    ///Bit 8 - Interrupt Mask on line 8
279    #[inline(always)]
280    pub fn im8(&mut self) -> IM_W<IMRrs> {
281        IM_W::new(self, 8)
282    }
283    ///Bit 9 - Interrupt Mask on line 9
284    #[inline(always)]
285    pub fn im9(&mut self) -> IM_W<IMRrs> {
286        IM_W::new(self, 9)
287    }
288    ///Bit 10 - Interrupt Mask on line 10
289    #[inline(always)]
290    pub fn im10(&mut self) -> IM_W<IMRrs> {
291        IM_W::new(self, 10)
292    }
293    ///Bit 11 - Interrupt Mask on line 11
294    #[inline(always)]
295    pub fn im11(&mut self) -> IM_W<IMRrs> {
296        IM_W::new(self, 11)
297    }
298    ///Bit 12 - Interrupt Mask on line 12
299    #[inline(always)]
300    pub fn im12(&mut self) -> IM_W<IMRrs> {
301        IM_W::new(self, 12)
302    }
303    ///Bit 13 - Interrupt Mask on line 13
304    #[inline(always)]
305    pub fn im13(&mut self) -> IM_W<IMRrs> {
306        IM_W::new(self, 13)
307    }
308    ///Bit 14 - Interrupt Mask on line 14
309    #[inline(always)]
310    pub fn im14(&mut self) -> IM_W<IMRrs> {
311        IM_W::new(self, 14)
312    }
313    ///Bit 15 - Interrupt Mask on line 15
314    #[inline(always)]
315    pub fn im15(&mut self) -> IM_W<IMRrs> {
316        IM_W::new(self, 15)
317    }
318    ///Bit 16 - Interrupt Mask on line 16
319    #[inline(always)]
320    pub fn im16(&mut self) -> IM_W<IMRrs> {
321        IM_W::new(self, 16)
322    }
323    ///Bit 17 - Interrupt Mask on line 17
324    #[inline(always)]
325    pub fn im17(&mut self) -> IM_W<IMRrs> {
326        IM_W::new(self, 17)
327    }
328    ///Bit 18 - Interrupt Mask on line 18
329    #[inline(always)]
330    pub fn im18(&mut self) -> IM_W<IMRrs> {
331        IM_W::new(self, 18)
332    }
333    ///Bit 19 - Interrupt Mask on line 19
334    #[inline(always)]
335    pub fn im19(&mut self) -> IM_W<IMRrs> {
336        IM_W::new(self, 19)
337    }
338    ///Bit 20 - Interrupt Mask on line 20
339    #[inline(always)]
340    pub fn im20(&mut self) -> IM_W<IMRrs> {
341        IM_W::new(self, 20)
342    }
343    ///Bit 21 - Interrupt Mask on line 21
344    #[inline(always)]
345    pub fn im21(&mut self) -> IM_W<IMRrs> {
346        IM_W::new(self, 21)
347    }
348    ///Bit 22 - Interrupt Mask on line 22
349    #[inline(always)]
350    pub fn im22(&mut self) -> IM_W<IMRrs> {
351        IM_W::new(self, 22)
352    }
353    ///Bit 23 - Interrupt Mask on line 23
354    #[inline(always)]
355    pub fn im23(&mut self) -> IM_W<IMRrs> {
356        IM_W::new(self, 23)
357    }
358}
359/**Interrupt mask register (EXTI_IMR)
360
361You can [`read`](crate::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
362
363See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#EXTI:IMR)*/
364pub struct IMRrs;
365impl crate::RegisterSpec for IMRrs {
366    type Ux = u32;
367}
368///`read()` method returns [`imr::R`](R) reader structure
369impl crate::Readable for IMRrs {}
370///`write(|w| ..)` method takes [`imr::W`](W) writer structure
371impl crate::Writable for IMRrs {
372    type Safety = crate::Unsafe;
373}
374///`reset()` method sets IMR to value 0
375impl crate::Resettable for IMRrs {}
stm32f7_staging/stm32f733/exti/imr.rs

stm32f7_staging/stm32f733/exti/
imr.rs
