stm32f7_staging/stm32f733/dma2/
lisr.rs

1///Register `LISR` reader
2pub type R = crate::R<LISRrs>;
3/**Stream x FIFO error interrupt flag (x=3..0)
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum FEIF0 {
9    ///0: No FIFO error event on stream x
10    NoError = 0,
11    ///1: A FIFO error event occurred on stream x
12    Error = 1,
13}
14impl From<FEIF0> for bool {
15    #[inline(always)]
16    fn from(variant: FEIF0) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `FEIF0` reader - Stream x FIFO error interrupt flag (x=3..0)
21pub type FEIF0_R = crate::BitReader<FEIF0>;
22impl FEIF0_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> FEIF0 {
26        match self.bits {
27            false => FEIF0::NoError,
28            true => FEIF0::Error,
29        }
30    }
31    ///No FIFO error event on stream x
32    #[inline(always)]
33    pub fn is_no_error(&self) -> bool {
34        *self == FEIF0::NoError
35    }
36    ///A FIFO error event occurred on stream x
37    #[inline(always)]
38    pub fn is_error(&self) -> bool {
39        *self == FEIF0::Error
40    }
41}
42/**Stream x direct mode error interrupt flag (x=3..0)
43
44Value on reset: 0*/
45#[cfg_attr(feature = "defmt", derive(defmt::Format))]
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum DMEIF0 {
48    ///0: No Direct Mode error on stream x
49    NoError = 0,
50    ///1: A Direct Mode error occurred on stream x
51    Error = 1,
52}
53impl From<DMEIF0> for bool {
54    #[inline(always)]
55    fn from(variant: DMEIF0) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `DMEIF0` reader - Stream x direct mode error interrupt flag (x=3..0)
60pub type DMEIF0_R = crate::BitReader<DMEIF0>;
61impl DMEIF0_R {
62    ///Get enumerated values variant
63    #[inline(always)]
64    pub const fn variant(&self) -> DMEIF0 {
65        match self.bits {
66            false => DMEIF0::NoError,
67            true => DMEIF0::Error,
68        }
69    }
70    ///No Direct Mode error on stream x
71    #[inline(always)]
72    pub fn is_no_error(&self) -> bool {
73        *self == DMEIF0::NoError
74    }
75    ///A Direct Mode error occurred on stream x
76    #[inline(always)]
77    pub fn is_error(&self) -> bool {
78        *self == DMEIF0::Error
79    }
80}
81/**Stream x transfer error interrupt flag (x=3..0)
82
83Value on reset: 0*/
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum TEIF0 {
87    ///0: No transfer error on stream x
88    NoError = 0,
89    ///1: A transfer error occurred on stream x
90    Error = 1,
91}
92impl From<TEIF0> for bool {
93    #[inline(always)]
94    fn from(variant: TEIF0) -> Self {
95        variant as u8 != 0
96    }
97}
98///Field `TEIF0` reader - Stream x transfer error interrupt flag (x=3..0)
99pub type TEIF0_R = crate::BitReader<TEIF0>;
100impl TEIF0_R {
101    ///Get enumerated values variant
102    #[inline(always)]
103    pub const fn variant(&self) -> TEIF0 {
104        match self.bits {
105            false => TEIF0::NoError,
106            true => TEIF0::Error,
107        }
108    }
109    ///No transfer error on stream x
110    #[inline(always)]
111    pub fn is_no_error(&self) -> bool {
112        *self == TEIF0::NoError
113    }
114    ///A transfer error occurred on stream x
115    #[inline(always)]
116    pub fn is_error(&self) -> bool {
117        *self == TEIF0::Error
118    }
119}
120/**Stream x half transfer interrupt flag (x=3..0)
121
122Value on reset: 0*/
123#[cfg_attr(feature = "defmt", derive(defmt::Format))]
124#[derive(Clone, Copy, Debug, PartialEq, Eq)]
125pub enum HTIF0 {
126    ///0: No half transfer event on stream x
127    NotHalf = 0,
128    ///1: A half transfer event occurred on stream x
129    Half = 1,
130}
131impl From<HTIF0> for bool {
132    #[inline(always)]
133    fn from(variant: HTIF0) -> Self {
134        variant as u8 != 0
135    }
136}
137///Field `HTIF0` reader - Stream x half transfer interrupt flag (x=3..0)
138pub type HTIF0_R = crate::BitReader<HTIF0>;
139impl HTIF0_R {
140    ///Get enumerated values variant
141    #[inline(always)]
142    pub const fn variant(&self) -> HTIF0 {
143        match self.bits {
144            false => HTIF0::NotHalf,
145            true => HTIF0::Half,
146        }
147    }
148    ///No half transfer event on stream x
149    #[inline(always)]
150    pub fn is_not_half(&self) -> bool {
151        *self == HTIF0::NotHalf
152    }
153    ///A half transfer event occurred on stream x
154    #[inline(always)]
155    pub fn is_half(&self) -> bool {
156        *self == HTIF0::Half
157    }
158}
159/**Stream x transfer complete interrupt flag (x = 3..0)
160
161Value on reset: 0*/
162#[cfg_attr(feature = "defmt", derive(defmt::Format))]
163#[derive(Clone, Copy, Debug, PartialEq, Eq)]
164pub enum TCIF0 {
165    ///0: No transfer complete event on stream x
166    NotComplete = 0,
167    ///1: A transfer complete event occurred on stream x
168    Complete = 1,
169}
170impl From<TCIF0> for bool {
171    #[inline(always)]
172    fn from(variant: TCIF0) -> Self {
173        variant as u8 != 0
174    }
175}
176///Field `TCIF0` reader - Stream x transfer complete interrupt flag (x = 3..0)
177pub type TCIF0_R = crate::BitReader<TCIF0>;
178impl TCIF0_R {
179    ///Get enumerated values variant
180    #[inline(always)]
181    pub const fn variant(&self) -> TCIF0 {
182        match self.bits {
183            false => TCIF0::NotComplete,
184            true => TCIF0::Complete,
185        }
186    }
187    ///No transfer complete event on stream x
188    #[inline(always)]
189    pub fn is_not_complete(&self) -> bool {
190        *self == TCIF0::NotComplete
191    }
192    ///A transfer complete event occurred on stream x
193    #[inline(always)]
194    pub fn is_complete(&self) -> bool {
195        *self == TCIF0::Complete
196    }
197}
198///Field `DMEIF1` reader - Stream x direct mode error interrupt flag (x=3..0)
199pub use DMEIF0_R as DMEIF1_R;
200///Field `DMEIF2` reader - Stream x direct mode error interrupt flag (x=3..0)
201pub use DMEIF0_R as DMEIF2_R;
202///Field `DMEIF3` reader - Stream x direct mode error interrupt flag (x=3..0)
203pub use DMEIF0_R as DMEIF3_R;
204///Field `FEIF1` reader - Stream x FIFO error interrupt flag (x=3..0)
205pub use FEIF0_R as FEIF1_R;
206///Field `FEIF2` reader - Stream x FIFO error interrupt flag (x=3..0)
207pub use FEIF0_R as FEIF2_R;
208///Field `FEIF3` reader - Stream x FIFO error interrupt flag (x=3..0)
209pub use FEIF0_R as FEIF3_R;
210///Field `HTIF1` reader - Stream x half transfer interrupt flag (x=3..0)
211pub use HTIF0_R as HTIF1_R;
212///Field `HTIF2` reader - Stream x half transfer interrupt flag (x=3..0)
213pub use HTIF0_R as HTIF2_R;
214///Field `HTIF3` reader - Stream x half transfer interrupt flag (x=3..0)
215pub use HTIF0_R as HTIF3_R;
216///Field `TCIF1` reader - Stream x transfer complete interrupt flag (x = 3..0)
217pub use TCIF0_R as TCIF1_R;
218///Field `TCIF2` reader - Stream x transfer complete interrupt flag (x = 3..0)
219pub use TCIF0_R as TCIF2_R;
220///Field `TCIF3` reader - Stream x transfer complete interrupt flag (x = 3..0)
221pub use TCIF0_R as TCIF3_R;
222///Field `TEIF1` reader - Stream x transfer error interrupt flag (x=3..0)
223pub use TEIF0_R as TEIF1_R;
224///Field `TEIF2` reader - Stream x transfer error interrupt flag (x=3..0)
225pub use TEIF0_R as TEIF2_R;
226///Field `TEIF3` reader - Stream x transfer error interrupt flag (x=3..0)
227pub use TEIF0_R as TEIF3_R;
228impl R {
229    ///Bit 0 - Stream x FIFO error interrupt flag (x=3..0)
230    #[inline(always)]
231    pub fn feif0(&self) -> FEIF0_R {
232        FEIF0_R::new((self.bits & 1) != 0)
233    }
234    ///Bit 2 - Stream x direct mode error interrupt flag (x=3..0)
235    #[inline(always)]
236    pub fn dmeif0(&self) -> DMEIF0_R {
237        DMEIF0_R::new(((self.bits >> 2) & 1) != 0)
238    }
239    ///Bit 3 - Stream x transfer error interrupt flag (x=3..0)
240    #[inline(always)]
241    pub fn teif0(&self) -> TEIF0_R {
242        TEIF0_R::new(((self.bits >> 3) & 1) != 0)
243    }
244    ///Bit 4 - Stream x half transfer interrupt flag (x=3..0)
245    #[inline(always)]
246    pub fn htif0(&self) -> HTIF0_R {
247        HTIF0_R::new(((self.bits >> 4) & 1) != 0)
248    }
249    ///Bit 5 - Stream x transfer complete interrupt flag (x = 3..0)
250    #[inline(always)]
251    pub fn tcif0(&self) -> TCIF0_R {
252        TCIF0_R::new(((self.bits >> 5) & 1) != 0)
253    }
254    ///Bit 6 - Stream x FIFO error interrupt flag (x=3..0)
255    #[inline(always)]
256    pub fn feif1(&self) -> FEIF1_R {
257        FEIF1_R::new(((self.bits >> 6) & 1) != 0)
258    }
259    ///Bit 8 - Stream x direct mode error interrupt flag (x=3..0)
260    #[inline(always)]
261    pub fn dmeif1(&self) -> DMEIF1_R {
262        DMEIF1_R::new(((self.bits >> 8) & 1) != 0)
263    }
264    ///Bit 9 - Stream x transfer error interrupt flag (x=3..0)
265    #[inline(always)]
266    pub fn teif1(&self) -> TEIF1_R {
267        TEIF1_R::new(((self.bits >> 9) & 1) != 0)
268    }
269    ///Bit 10 - Stream x half transfer interrupt flag (x=3..0)
270    #[inline(always)]
271    pub fn htif1(&self) -> HTIF1_R {
272        HTIF1_R::new(((self.bits >> 10) & 1) != 0)
273    }
274    ///Bit 11 - Stream x transfer complete interrupt flag (x = 3..0)
275    #[inline(always)]
276    pub fn tcif1(&self) -> TCIF1_R {
277        TCIF1_R::new(((self.bits >> 11) & 1) != 0)
278    }
279    ///Bit 16 - Stream x FIFO error interrupt flag (x=3..0)
280    #[inline(always)]
281    pub fn feif2(&self) -> FEIF2_R {
282        FEIF2_R::new(((self.bits >> 16) & 1) != 0)
283    }
284    ///Bit 18 - Stream x direct mode error interrupt flag (x=3..0)
285    #[inline(always)]
286    pub fn dmeif2(&self) -> DMEIF2_R {
287        DMEIF2_R::new(((self.bits >> 18) & 1) != 0)
288    }
289    ///Bit 19 - Stream x transfer error interrupt flag (x=3..0)
290    #[inline(always)]
291    pub fn teif2(&self) -> TEIF2_R {
292        TEIF2_R::new(((self.bits >> 19) & 1) != 0)
293    }
294    ///Bit 20 - Stream x half transfer interrupt flag (x=3..0)
295    #[inline(always)]
296    pub fn htif2(&self) -> HTIF2_R {
297        HTIF2_R::new(((self.bits >> 20) & 1) != 0)
298    }
299    ///Bit 21 - Stream x transfer complete interrupt flag (x = 3..0)
300    #[inline(always)]
301    pub fn tcif2(&self) -> TCIF2_R {
302        TCIF2_R::new(((self.bits >> 21) & 1) != 0)
303    }
304    ///Bit 22 - Stream x FIFO error interrupt flag (x=3..0)
305    #[inline(always)]
306    pub fn feif3(&self) -> FEIF3_R {
307        FEIF3_R::new(((self.bits >> 22) & 1) != 0)
308    }
309    ///Bit 24 - Stream x direct mode error interrupt flag (x=3..0)
310    #[inline(always)]
311    pub fn dmeif3(&self) -> DMEIF3_R {
312        DMEIF3_R::new(((self.bits >> 24) & 1) != 0)
313    }
314    ///Bit 25 - Stream x transfer error interrupt flag (x=3..0)
315    #[inline(always)]
316    pub fn teif3(&self) -> TEIF3_R {
317        TEIF3_R::new(((self.bits >> 25) & 1) != 0)
318    }
319    ///Bit 26 - Stream x half transfer interrupt flag (x=3..0)
320    #[inline(always)]
321    pub fn htif3(&self) -> HTIF3_R {
322        HTIF3_R::new(((self.bits >> 26) & 1) != 0)
323    }
324    ///Bit 27 - Stream x transfer complete interrupt flag (x = 3..0)
325    #[inline(always)]
326    pub fn tcif3(&self) -> TCIF3_R {
327        TCIF3_R::new(((self.bits >> 27) & 1) != 0)
328    }
329}
330impl core::fmt::Debug for R {
331    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
332        f.debug_struct("LISR")
333            .field("tcif0", &self.tcif0())
334            .field("tcif3", &self.tcif3())
335            .field("htif0", &self.htif0())
336            .field("htif3", &self.htif3())
337            .field("teif0", &self.teif0())
338            .field("teif3", &self.teif3())
339            .field("dmeif0", &self.dmeif0())
340            .field("dmeif3", &self.dmeif3())
341            .field("feif0", &self.feif0())
342            .field("feif3", &self.feif3())
343            .field("tcif2", &self.tcif2())
344            .field("htif2", &self.htif2())
345            .field("teif2", &self.teif2())
346            .field("dmeif2", &self.dmeif2())
347            .field("feif2", &self.feif2())
348            .field("tcif1", &self.tcif1())
349            .field("htif1", &self.htif1())
350            .field("teif1", &self.teif1())
351            .field("dmeif1", &self.dmeif1())
352            .field("feif1", &self.feif1())
353            .finish()
354    }
355}
356/**low interrupt status register
357
358You can [`read`](crate::Reg::read) this register and get [`lisr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
359
360See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F733.html#DMA2:LISR)*/
361pub struct LISRrs;
362impl crate::RegisterSpec for LISRrs {
363    type Ux = u32;
364}
365///`read()` method returns [`lisr::R`](R) reader structure
366impl crate::Readable for LISRrs {}
367///`reset()` method sets LISR to value 0
368impl crate::Resettable for LISRrs {}
stm32f7_staging/stm32f733/dma2/lisr.rs

stm32f7_staging/stm32f733/dma2/
lisr.rs
