stm32f7_staging/stm32f779/rcc/
pllcfgr.rs

1///Register `PLLCFGR` reader
2pub type R = crate::R<PLLCFGRrs>;
3///Register `PLLCFGR` writer
4pub type W = crate::W<PLLCFGRrs>;
5///Field `PLLM` reader - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
6pub type PLLM_R = crate::FieldReader;
7///Field `PLLM` writer - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
8pub type PLLM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9///Field `PLLN` reader - Main PLL (PLL) multiplication factor for VCO
10pub type PLLN_R = crate::FieldReader<u16>;
11///Field `PLLN` writer - Main PLL (PLL) multiplication factor for VCO
12pub type PLLN_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
13/**Main PLL (PLL) division factor for main system clock
14
15Value on reset: 0*/
16#[cfg_attr(feature = "defmt", derive(defmt::Format))]
17#[derive(Clone, Copy, Debug, PartialEq, Eq)]
18#[repr(u8)]
19pub enum PLLP {
20    ///0: PLLP=2
21    Div2 = 0,
22    ///1: PLLP=4
23    Div4 = 1,
24    ///2: PLLP=6
25    Div6 = 2,
26    ///3: PLLP=8
27    Div8 = 3,
28}
29impl From<PLLP> for u8 {
30    #[inline(always)]
31    fn from(variant: PLLP) -> Self {
32        variant as _
33    }
34}
35impl crate::FieldSpec for PLLP {
36    type Ux = u8;
37}
38impl crate::IsEnum for PLLP {}
39///Field `PLLP` reader - Main PLL (PLL) division factor for main system clock
40pub type PLLP_R = crate::FieldReader<PLLP>;
41impl PLLP_R {
42    ///Get enumerated values variant
43    #[inline(always)]
44    pub const fn variant(&self) -> PLLP {
45        match self.bits {
46            0 => PLLP::Div2,
47            1 => PLLP::Div4,
48            2 => PLLP::Div6,
49            3 => PLLP::Div8,
50            _ => unreachable!(),
51        }
52    }
53    ///PLLP=2
54    #[inline(always)]
55    pub fn is_div2(&self) -> bool {
56        *self == PLLP::Div2
57    }
58    ///PLLP=4
59    #[inline(always)]
60    pub fn is_div4(&self) -> bool {
61        *self == PLLP::Div4
62    }
63    ///PLLP=6
64    #[inline(always)]
65    pub fn is_div6(&self) -> bool {
66        *self == PLLP::Div6
67    }
68    ///PLLP=8
69    #[inline(always)]
70    pub fn is_div8(&self) -> bool {
71        *self == PLLP::Div8
72    }
73}
74///Field `PLLP` writer - Main PLL (PLL) division factor for main system clock
75pub type PLLP_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PLLP, crate::Safe>;
76impl<'a, REG> PLLP_W<'a, REG>
77where
78    REG: crate::Writable + crate::RegisterSpec,
79    REG::Ux: From<u8>,
80{
81    ///PLLP=2
82    #[inline(always)]
83    pub fn div2(self) -> &'a mut crate::W<REG> {
84        self.variant(PLLP::Div2)
85    }
86    ///PLLP=4
87    #[inline(always)]
88    pub fn div4(self) -> &'a mut crate::W<REG> {
89        self.variant(PLLP::Div4)
90    }
91    ///PLLP=6
92    #[inline(always)]
93    pub fn div6(self) -> &'a mut crate::W<REG> {
94        self.variant(PLLP::Div6)
95    }
96    ///PLLP=8
97    #[inline(always)]
98    pub fn div8(self) -> &'a mut crate::W<REG> {
99        self.variant(PLLP::Div8)
100    }
101}
102/**Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
103
104Value on reset: 0*/
105#[cfg_attr(feature = "defmt", derive(defmt::Format))]
106#[derive(Clone, Copy, Debug, PartialEq, Eq)]
107pub enum PLLSRC {
108    ///0: HSI clock selected as PLL and PLLI2S clock entry
109    Hsi = 0,
110    ///1: HSE oscillator clock selected as PLL and PLLI2S clock entry
111    Hse = 1,
112}
113impl From<PLLSRC> for bool {
114    #[inline(always)]
115    fn from(variant: PLLSRC) -> Self {
116        variant as u8 != 0
117    }
118}
119///Field `PLLSRC` reader - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
120pub type PLLSRC_R = crate::BitReader<PLLSRC>;
121impl PLLSRC_R {
122    ///Get enumerated values variant
123    #[inline(always)]
124    pub const fn variant(&self) -> PLLSRC {
125        match self.bits {
126            false => PLLSRC::Hsi,
127            true => PLLSRC::Hse,
128        }
129    }
130    ///HSI clock selected as PLL and PLLI2S clock entry
131    #[inline(always)]
132    pub fn is_hsi(&self) -> bool {
133        *self == PLLSRC::Hsi
134    }
135    ///HSE oscillator clock selected as PLL and PLLI2S clock entry
136    #[inline(always)]
137    pub fn is_hse(&self) -> bool {
138        *self == PLLSRC::Hse
139    }
140}
141///Field `PLLSRC` writer - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
142pub type PLLSRC_W<'a, REG> = crate::BitWriter<'a, REG, PLLSRC>;
143impl<'a, REG> PLLSRC_W<'a, REG>
144where
145    REG: crate::Writable + crate::RegisterSpec,
146{
147    ///HSI clock selected as PLL and PLLI2S clock entry
148    #[inline(always)]
149    pub fn hsi(self) -> &'a mut crate::W<REG> {
150        self.variant(PLLSRC::Hsi)
151    }
152    ///HSE oscillator clock selected as PLL and PLLI2S clock entry
153    #[inline(always)]
154    pub fn hse(self) -> &'a mut crate::W<REG> {
155        self.variant(PLLSRC::Hse)
156    }
157}
158///Field `PLLQ` reader - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
159pub type PLLQ_R = crate::FieldReader;
160///Field `PLLQ` writer - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
161pub type PLLQ_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
162///Field `PLLR` reader - PLL division factor for DSI clock
163pub type PLLR_R = crate::FieldReader;
164///Field `PLLR` writer - PLL division factor for DSI clock
165pub type PLLR_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
166impl R {
167    ///Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
168    #[inline(always)]
169    pub fn pllm(&self) -> PLLM_R {
170        PLLM_R::new((self.bits & 0x3f) as u8)
171    }
172    ///Bits 6:14 - Main PLL (PLL) multiplication factor for VCO
173    #[inline(always)]
174    pub fn plln(&self) -> PLLN_R {
175        PLLN_R::new(((self.bits >> 6) & 0x01ff) as u16)
176    }
177    ///Bits 16:17 - Main PLL (PLL) division factor for main system clock
178    #[inline(always)]
179    pub fn pllp(&self) -> PLLP_R {
180        PLLP_R::new(((self.bits >> 16) & 3) as u8)
181    }
182    ///Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
183    #[inline(always)]
184    pub fn pllsrc(&self) -> PLLSRC_R {
185        PLLSRC_R::new(((self.bits >> 22) & 1) != 0)
186    }
187    ///Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
188    #[inline(always)]
189    pub fn pllq(&self) -> PLLQ_R {
190        PLLQ_R::new(((self.bits >> 24) & 0x0f) as u8)
191    }
192    ///Bits 28:30 - PLL division factor for DSI clock
193    #[inline(always)]
194    pub fn pllr(&self) -> PLLR_R {
195        PLLR_R::new(((self.bits >> 28) & 7) as u8)
196    }
197}
198impl core::fmt::Debug for R {
199    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
200        f.debug_struct("PLLCFGR")
201            .field("pllq", &self.pllq())
202            .field("pllsrc", &self.pllsrc())
203            .field("pllp", &self.pllp())
204            .field("plln", &self.plln())
205            .field("pllm", &self.pllm())
206            .field("pllr", &self.pllr())
207            .finish()
208    }
209}
210impl W {
211    ///Bits 0:5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
212    #[inline(always)]
213    pub fn pllm(&mut self) -> PLLM_W<PLLCFGRrs> {
214        PLLM_W::new(self, 0)
215    }
216    ///Bits 6:14 - Main PLL (PLL) multiplication factor for VCO
217    #[inline(always)]
218    pub fn plln(&mut self) -> PLLN_W<PLLCFGRrs> {
219        PLLN_W::new(self, 6)
220    }
221    ///Bits 16:17 - Main PLL (PLL) division factor for main system clock
222    #[inline(always)]
223    pub fn pllp(&mut self) -> PLLP_W<PLLCFGRrs> {
224        PLLP_W::new(self, 16)
225    }
226    ///Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
227    #[inline(always)]
228    pub fn pllsrc(&mut self) -> PLLSRC_W<PLLCFGRrs> {
229        PLLSRC_W::new(self, 22)
230    }
231    ///Bits 24:27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
232    #[inline(always)]
233    pub fn pllq(&mut self) -> PLLQ_W<PLLCFGRrs> {
234        PLLQ_W::new(self, 24)
235    }
236    ///Bits 28:30 - PLL division factor for DSI clock
237    #[inline(always)]
238    pub fn pllr(&mut self) -> PLLR_W<PLLCFGRrs> {
239        PLLR_W::new(self, 28)
240    }
241}
242/**PLL configuration register
243
244You can [`read`](crate::Reg::read) this register and get [`pllcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
245
246See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F779.html#RCC:PLLCFGR)*/
247pub struct PLLCFGRrs;
248impl crate::RegisterSpec for PLLCFGRrs {
249    type Ux = u32;
250}
251///`read()` method returns [`pllcfgr::R`](R) reader structure
252impl crate::Readable for PLLCFGRrs {}
253///`write(|w| ..)` method takes [`pllcfgr::W`](W) writer structure
254impl crate::Writable for PLLCFGRrs {
255    type Safety = crate::Unsafe;
256    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
257    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
258}
259///`reset()` method sets PLLCFGR to value 0x2400_3010
260impl crate::Resettable for PLLCFGRrs {
261    const RESET_VALUE: u32 = 0x2400_3010;
262}
stm32f7_staging/stm32f779/rcc/pllcfgr.rs

stm32f7_staging/stm32f779/rcc/
pllcfgr.rs
