stm32f4xx_hal/pacext/
uart.rs

1#![allow(unused)]
2
3use crate::{sealed, Sealed};
4
5use super::*;
6#[cfg(feature = "uart4")]
7use crate::pac::uart4;
8use crate::pac::usart1;
9
10pub trait UartRB: Sealed {
11    fn cr1(&self) -> &usart1::CR1;
12    fn dr(&self) -> &usart1::DR;
13    fn brr(&self) -> &usart1::BRR;
14    type SRrs: reg::SrR + reg::SrW;
15    fn sr(&self) -> &Reg<Self::SRrs>;
16    type CR2rs: reg::Cr2R + reg::Cr2W;
17    fn cr2(&self) -> &Reg<Self::CR2rs>;
18    type CR3rs: reg::Cr3R + reg::Cr3W;
19    fn cr3(&self) -> &Reg<Self::CR3rs>;
20    type GTPRrs: reg::GtprR + reg::GtprW;
21    fn gtpr(&self) -> &Reg<Self::GTPRrs>;
22}
23
24wrap_r! {
25    pub trait SrR {
26        fn pe(&self) -> usart1::sr::PE_R;
27        fn fe(&self) -> usart1::sr::FE_R;
28        fn nf(&self) -> usart1::sr::NF_R;
29        fn ore(&self) -> usart1::sr::ORE_R;
30        fn idle(&self) -> usart1::sr::IDLE_R;
31        fn rxne(&self) -> usart1::sr::RXNE_R;
32        fn tc(&self) -> usart1::sr::TC_R;
33        fn txe(&self) -> usart1::sr::TXE_R;
34        fn lbd(&self) -> usart1::sr::LBD_R;
35    }
36}
37wrap_w! {
38    pub trait SrW {
39        fn rxne(&mut self) -> usart1::sr::RXNE_W<'_, REG>;
40        fn tc(&mut self) -> usart1::sr::TC_W<'_, REG>;
41        fn lbd(&mut self) -> usart1::sr::LBD_W<'_, REG>;
42    }
43}
44
45wrap_r! {
46    pub trait Cr2R {
47        fn add(&self) -> usart1::cr2::ADD_R;
48        fn lbdl(&self) -> usart1::cr2::LBDL_R;
49        fn lbdie(&self) -> usart1::cr2::LBDIE_R;
50        fn linen(&self) -> usart1::cr2::LINEN_R;
51    }
52}
53wrap_w! {
54    pub trait Cr2W {
55        fn add(&mut self) -> usart1::cr2::ADD_W<'_, REG>;
56        fn lbdl(&mut self) -> usart1::cr2::LBDL_W<'_, REG>;
57        fn lbdie(&mut self) -> usart1::cr2::LBDIE_W<'_, REG>;
58        fn linen(&mut self) -> usart1::cr2::LINEN_W<'_, REG>;
59    }
60}
61
62wrap_r! {
63    pub trait Cr3R {
64        fn eie(&self) -> usart1::cr3::EIE_R;
65        fn iren(&self) -> usart1::cr3::IREN_R;
66        fn irlp(&self) -> usart1::cr3::IRLP_R;
67        fn hdsel(&self) -> usart1::cr3::HDSEL_R;
68        fn dmar(&self) -> usart1::cr3::DMAR_R;
69        fn dmat(&self) -> usart1::cr3::DMAT_R;
70        fn onebit(&self) -> usart1::cr3::ONEBIT_R;
71    }
72}
73wrap_w! {
74    pub trait Cr3W {
75        fn eie(&mut self) -> usart1::cr3::EIE_W<'_, REG>;
76        fn iren(&mut self) -> usart1::cr3::IREN_W<'_, REG>;
77        fn irlp(&mut self) -> usart1::cr3::IRLP_W<'_, REG>;
78        fn hdsel(&mut self) -> usart1::cr3::HDSEL_W<'_, REG>;
79        fn dmar(&mut self) -> usart1::cr3::DMAR_W<'_, REG>;
80        fn dmat(&mut self) -> usart1::cr3::DMAT_W<'_, REG>;
81        fn onebit(&mut self) -> usart1::cr3::ONEBIT_W<'_, REG>;
82    }
83}
84
85wrap_r! {
86    pub trait GtprR {
87        fn psc(&self) -> usart1::gtpr::PSC_R;
88    }
89}
90wrap_w! {
91    pub trait GtprW {
92        fn psc(&mut self) -> usart1::gtpr::PSC_W<'_, REG>;
93    }
94}
95
96mod reg {
97    use super::*;
98
99    pub trait SrR: RegisterSpec<Ux = u16> + Readable + Sized {
100        fn pe(r: &R<Self>) -> usart1::sr::PE_R;
101        fn fe(r: &R<Self>) -> usart1::sr::FE_R;
102        fn nf(r: &R<Self>) -> usart1::sr::NF_R;
103        fn ore(r: &R<Self>) -> usart1::sr::ORE_R;
104        fn idle(r: &R<Self>) -> usart1::sr::IDLE_R;
105        fn rxne(r: &R<Self>) -> usart1::sr::RXNE_R;
106        fn tc(r: &R<Self>) -> usart1::sr::TC_R;
107        fn txe(r: &R<Self>) -> usart1::sr::TXE_R;
108        fn lbd(r: &R<Self>) -> usart1::sr::LBD_R;
109    }
110    pub trait SrW: RegisterSpec<Ux = u16> + Writable + Resettable + Sized {
111        fn rxne(w: &mut W<Self>) -> usart1::sr::RXNE_W<'_, Self>;
112        fn tc(w: &mut W<Self>) -> usart1::sr::TC_W<'_, Self>;
113        fn lbd(w: &mut W<Self>) -> usart1::sr::LBD_W<'_, Self>;
114    }
115
116    pub trait Cr2R: RegisterSpec<Ux = u16> + Readable + Sized {
117        fn add(r: &R<Self>) -> usart1::cr2::ADD_R;
118        fn lbdl(r: &R<Self>) -> usart1::cr2::LBDL_R;
119        fn lbdie(r: &R<Self>) -> usart1::cr2::LBDIE_R;
120        fn linen(r: &R<Self>) -> usart1::cr2::LINEN_R;
121    }
122    pub trait Cr2W: RegisterSpec<Ux = u16> + Writable + Resettable + Sized {
123        fn add(w: &mut W<Self>) -> usart1::cr2::ADD_W<'_, Self>;
124        fn lbdl(w: &mut W<Self>) -> usart1::cr2::LBDL_W<'_, Self>;
125        fn lbdie(w: &mut W<Self>) -> usart1::cr2::LBDIE_W<'_, Self>;
126        fn linen(w: &mut W<Self>) -> usart1::cr2::LINEN_W<'_, Self>;
127    }
128
129    pub trait Cr3R: RegisterSpec<Ux = u16> + Readable + Sized {
130        fn eie(r: &R<Self>) -> usart1::cr3::EIE_R;
131        fn iren(r: &R<Self>) -> usart1::cr3::IREN_R;
132        fn irlp(r: &R<Self>) -> usart1::cr3::IRLP_R;
133        fn hdsel(r: &R<Self>) -> usart1::cr3::HDSEL_R;
134        fn dmar(r: &R<Self>) -> usart1::cr3::DMAR_R;
135        fn dmat(r: &R<Self>) -> usart1::cr3::DMAT_R;
136        fn onebit(r: &R<Self>) -> usart1::cr3::ONEBIT_R;
137    }
138    pub trait Cr3W: RegisterSpec<Ux = u16> + Writable + Resettable + Sized {
139        fn eie(w: &mut W<Self>) -> usart1::cr3::EIE_W<'_, Self>;
140        fn iren(w: &mut W<Self>) -> usart1::cr3::IREN_W<'_, Self>;
141        fn irlp(w: &mut W<Self>) -> usart1::cr3::IRLP_W<'_, Self>;
142        fn hdsel(w: &mut W<Self>) -> usart1::cr3::HDSEL_W<'_, Self>;
143        fn dmar(w: &mut W<Self>) -> usart1::cr3::DMAR_W<'_, Self>;
144        fn dmat(w: &mut W<Self>) -> usart1::cr3::DMAT_W<'_, Self>;
145        fn onebit(w: &mut W<Self>) -> usart1::cr3::ONEBIT_W<'_, Self>;
146    }
147
148    pub trait GtprR: RegisterSpec<Ux = u16> + Readable + Sized {
149        fn psc(r: &R<Self>) -> usart1::gtpr::PSC_R;
150    }
151    pub trait GtprW: RegisterSpec<Ux = u16> + Writable + Resettable + Sized {
152        fn psc(w: &mut W<Self>) -> usart1::gtpr::PSC_W<'_, Self>;
153    }
154}
155
156macro_rules! impl_ext {
157    ($(#[$attr:meta])* $uart:ident) => {
158        impl Sealed for $uart::RegisterBlock {}
159        impl UartRB for $uart::RegisterBlock {
160            type SRrs = $uart::sr::SRrs;
161            type CR2rs = $uart::cr2::CR2rs;
162            type CR3rs = $uart::cr3::CR3rs;
163            type GTPRrs = $uart::gtpr::GTPRrs;
164            impl_reg! {
165                cr1 -> &usart1::CR1;
166                dr -> &usart1::DR;
167                brr -> &usart1::BRR;
168                sr -> &Reg<Self::SRrs>;
169                cr2 -> &Reg<Self::CR2rs>;
170                cr3 -> &Reg<Self::CR3rs>;
171                gtpr -> &Reg<Self::GTPRrs>;
172            }
173        }
174
175        impl reg::SrR for $uart::sr::SRrs {
176            impl_read! {
177                pe -> usart1::sr::PE_R;
178                fe -> usart1::sr::FE_R;
179                nf -> usart1::sr::NF_R;
180                ore -> usart1::sr::ORE_R;
181                idle -> usart1::sr::IDLE_R;
182                rxne -> usart1::sr::RXNE_R;
183                tc -> usart1::sr::TC_R;
184                txe -> usart1::sr::TXE_R;
185                lbd -> usart1::sr::LBD_R;
186            }
187        }
188        impl reg::SrW for $uart::sr::SRrs {
189            impl_write! {
190                rxne -> usart1::sr::RXNE_W<'_, Self>;
191                tc -> usart1::sr::TC_W<'_, Self>;
192                lbd -> usart1::sr::LBD_W<'_, Self>;
193            }
194        }
195
196        impl reg::Cr2R for $uart::cr2::CR2rs {
197            impl_read! {
198                add -> usart1::cr2::ADD_R;
199                lbdl -> usart1::cr2::LBDL_R;
200                lbdie -> usart1::cr2::LBDIE_R;
201                linen -> usart1::cr2::LINEN_R;
202            }
203        }
204        impl reg::Cr2W for $uart::cr2::CR2rs {
205            impl_write! {
206                add -> usart1::cr2::ADD_W<'_, Self>;
207                lbdl -> usart1::cr2::LBDL_W<'_, Self>;
208                lbdie -> usart1::cr2::LBDIE_W<'_, Self>;
209                linen -> usart1::cr2::LINEN_W<'_, Self>;
210            }
211        }
212
213        $(#[$attr])*
214        impl reg::Cr3R for $uart::cr3::CR3rs {
215            impl_read! {
216                eie -> usart1::cr3::EIE_R;
217                iren -> usart1::cr3::IREN_R;
218                irlp -> usart1::cr3::IRLP_R;
219                hdsel -> usart1::cr3::HDSEL_R;
220                dmar -> usart1::cr3::DMAR_R;
221                dmat -> usart1::cr3::DMAT_R;
222                onebit -> usart1::cr3::ONEBIT_R;
223            }
224        }
225        $(#[$attr])*
226        impl reg::Cr3W for $uart::cr3::CR3rs {
227            impl_write! {
228                eie -> usart1::cr3::EIE_W<'_, Self>;
229                iren -> usart1::cr3::IREN_W<'_, Self>;
230                irlp -> usart1::cr3::IRLP_W<'_, Self>;
231                hdsel -> usart1::cr3::HDSEL_W<'_, Self>;
232                dmar -> usart1::cr3::DMAR_W<'_, Self>;
233                dmat -> usart1::cr3::DMAT_W<'_, Self>;
234                onebit -> usart1::cr3::ONEBIT_W<'_, Self>;
235            }
236        }
237
238        impl reg::GtprR for $uart::gtpr::GTPRrs {
239            impl_read! {
240                psc -> usart1::gtpr::PSC_R;
241            }
242        }
243        impl reg::GtprW for $uart::gtpr::GTPRrs {
244            impl_write! {
245                psc -> usart1::gtpr::PSC_W<'_, Self>;
246            }
247        }
248    };
249}
250
251impl_ext!(usart1);
252#[cfg(feature = "uart4")]
253impl_ext!(
254    #[cfg(not(feature = "gpio-f446"))]
255    uart4
256);
stm32f4xx_hal/pacext/uart.rs

stm32f4xx_hal/pacext/
uart.rs
