Struct stm32f4xx_hal::dma::MemoryToPeripheral
source · [−]pub struct MemoryToPeripheral;
Expand description
DMA from a memory location to a peripheral.
Trait Implementations
sourceimpl Clone for MemoryToPeripheral
impl Clone for MemoryToPeripheral
sourcefn clone(&self) -> MemoryToPeripheral
fn clone(&self) -> MemoryToPeripheral
Returns a copy of the value. Read more
1.0.0 · sourcefn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
Performs copy-assignment from source
. Read more
sourceimpl Debug for MemoryToPeripheral
impl Debug for MemoryToPeripheral
sourceimpl Direction for MemoryToPeripheral
impl Direction for MemoryToPeripheral
sourcefn direction() -> DmaDirection
fn direction() -> DmaDirection
Returns the DmaDirection
of the type.
impl Copy for MemoryToPeripheral
impl DMASet<StreamX<DMA1, 0_u8>, 2_u8, MemoryToPeripheral> for CCR1<TIM4>
impl DMASet<StreamX<DMA1, 0_u8>, 5_u8, MemoryToPeripheral> for UART8
impl DMASet<StreamX<DMA1, 0_u8>, 6_u8, MemoryToPeripheral> for CCR3<TIM5>
impl DMASet<StreamX<DMA1, 0_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 1_u8>, 3_u8, MemoryToPeripheral> for DMAR<TIM2>
impl DMASet<StreamX<DMA1, 1_u8>, 3_u8, MemoryToPeripheral> for CCR3<TIM2>
impl DMASet<StreamX<DMA1, 1_u8>, 5_u8, MemoryToPeripheral> for UART7
impl DMASet<StreamX<DMA1, 1_u8>, 6_u8, MemoryToPeripheral> for CCR4<TIM5>
impl DMASet<StreamX<DMA1, 1_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 2_u8>, 5_u8, MemoryToPeripheral> for CCR4<TIM3>
impl DMASet<StreamX<DMA1, 2_u8>, 5_u8, MemoryToPeripheral> for DMAR<TIM3>
impl DMASet<StreamX<DMA1, 2_u8>, 6_u8, MemoryToPeripheral> for CCR1<TIM5>
impl DMASet<StreamX<DMA1, 3_u8>, 2_u8, MemoryToPeripheral> for CCR2<TIM4>
impl DMASet<StreamX<DMA1, 3_u8>, 4_u8, MemoryToPeripheral> for USART3
impl DMASet<StreamX<DMA1, 3_u8>, 4_u8, MemoryToPeripheral> for Tx<USART3>
impl DMASet<StreamX<DMA1, 3_u8>, 6_u8, MemoryToPeripheral> for CCR4<TIM5>
impl DMASet<StreamX<DMA1, 3_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 4_u8>, 0_u8, MemoryToPeripheral> for SPI2
impl DMASet<StreamX<DMA1, 4_u8>, 0_u8, MemoryToPeripheral> for Tx<SPI2>
impl DMASet<StreamX<DMA1, 4_u8>, 3_u8, MemoryToPeripheral> for I2C3
impl DMASet<StreamX<DMA1, 4_u8>, 4_u8, MemoryToPeripheral> for UART4
impl DMASet<StreamX<DMA1, 4_u8>, 5_u8, MemoryToPeripheral> for CCR1<TIM3>
impl DMASet<StreamX<DMA1, 4_u8>, 5_u8, MemoryToPeripheral> for DMAR<TIM3>
impl DMASet<StreamX<DMA1, 4_u8>, 6_u8, MemoryToPeripheral> for CCR2<TIM5>
impl DMASet<StreamX<DMA1, 4_u8>, 7_u8, MemoryToPeripheral> for USART3
impl DMASet<StreamX<DMA1, 4_u8>, 7_u8, MemoryToPeripheral> for Tx<USART3>
impl DMASet<StreamX<DMA1, 5_u8>, 0_u8, MemoryToPeripheral> for SPI3
impl DMASet<StreamX<DMA1, 5_u8>, 0_u8, MemoryToPeripheral> for Tx<SPI3>
impl DMASet<StreamX<DMA1, 5_u8>, 3_u8, MemoryToPeripheral> for CCR1<TIM2>
impl DMASet<StreamX<DMA1, 5_u8>, 5_u8, MemoryToPeripheral> for CCR2<TIM3>
impl DMASet<StreamX<DMA1, 6_u8>, 1_u8, MemoryToPeripheral> for I2C1
impl DMASet<StreamX<DMA1, 6_u8>, 2_u8, MemoryToPeripheral> for DMAR<TIM4>
impl DMASet<StreamX<DMA1, 6_u8>, 3_u8, MemoryToPeripheral> for CCR2<TIM2>
impl DMASet<StreamX<DMA1, 6_u8>, 3_u8, MemoryToPeripheral> for CCR4<TIM2>
impl DMASet<StreamX<DMA1, 6_u8>, 4_u8, MemoryToPeripheral> for USART2
impl DMASet<StreamX<DMA1, 6_u8>, 4_u8, MemoryToPeripheral> for Tx<USART2>
impl DMASet<StreamX<DMA1, 6_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM5>
impl DMASet<StreamX<DMA1, 7_u8>, 0_u8, MemoryToPeripheral> for SPI3
impl DMASet<StreamX<DMA1, 7_u8>, 0_u8, MemoryToPeripheral> for Tx<SPI3>
impl DMASet<StreamX<DMA1, 7_u8>, 1_u8, MemoryToPeripheral> for I2C1
impl DMASet<StreamX<DMA1, 7_u8>, 2_u8, MemoryToPeripheral> for CCR3<TIM4>
impl DMASet<StreamX<DMA1, 7_u8>, 3_u8, MemoryToPeripheral> for DMAR<TIM2>
impl DMASet<StreamX<DMA1, 7_u8>, 3_u8, MemoryToPeripheral> for CCR4<TIM2>
impl DMASet<StreamX<DMA1, 7_u8>, 4_u8, MemoryToPeripheral> for UART5
impl DMASet<StreamX<DMA1, 7_u8>, 5_u8, MemoryToPeripheral> for CCR3<TIM3>
impl DMASet<StreamX<DMA1, 7_u8>, 7_u8, MemoryToPeripheral> for I2C2
impl DMASet<StreamX<DMA2, 0_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM1>
impl DMASet<StreamX<DMA2, 1_u8>, 4_u8, MemoryToPeripheral> for SPI4
impl DMASet<StreamX<DMA2, 1_u8>, 4_u8, MemoryToPeripheral> for Tx<SPI4>
impl DMASet<StreamX<DMA2, 1_u8>, 6_u8, MemoryToPeripheral> for CCR1<TIM1>
impl DMASet<StreamX<DMA2, 1_u8>, 7_u8, MemoryToPeripheral> for DMAR<TIM8>
impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, MemoryToPeripheral> for CCR1<TIM8>
impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, MemoryToPeripheral> for CCR2<TIM8>
impl DMASet<StreamX<DMA2, 2_u8>, 0_u8, MemoryToPeripheral> for CCR3<TIM8>
impl DMASet<StreamX<DMA2, 2_u8>, 6_u8, MemoryToPeripheral> for CCR2<TIM1>
impl DMASet<StreamX<DMA2, 2_u8>, 7_u8, MemoryToPeripheral> for CCR1<TIM8>
impl DMASet<StreamX<DMA2, 3_u8>, 3_u8, MemoryToPeripheral> for SPI1
impl DMASet<StreamX<DMA2, 3_u8>, 3_u8, MemoryToPeripheral> for Tx<SPI1>
impl DMASet<StreamX<DMA2, 3_u8>, 4_u8, MemoryToPeripheral> for SDIO
impl DMASet<StreamX<DMA2, 3_u8>, 6_u8, MemoryToPeripheral> for CCR1<TIM1>
impl DMASet<StreamX<DMA2, 3_u8>, 7_u8, MemoryToPeripheral> for CCR2<TIM8>
impl DMASet<StreamX<DMA2, 4_u8>, 2_u8, MemoryToPeripheral> for SPI5
impl DMASet<StreamX<DMA2, 4_u8>, 2_u8, MemoryToPeripheral> for Tx<SPI5>
impl DMASet<StreamX<DMA2, 4_u8>, 5_u8, MemoryToPeripheral> for SPI4
impl DMASet<StreamX<DMA2, 4_u8>, 5_u8, MemoryToPeripheral> for Tx<SPI4>
impl DMASet<StreamX<DMA2, 4_u8>, 6_u8, MemoryToPeripheral> for CCR4<TIM1>
impl DMASet<StreamX<DMA2, 4_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM1>
impl DMASet<StreamX<DMA2, 4_u8>, 7_u8, MemoryToPeripheral> for CCR3<TIM8>
impl DMASet<StreamX<DMA2, 5_u8>, 1_u8, MemoryToPeripheral> for SPI6
impl DMASet<StreamX<DMA2, 5_u8>, 1_u8, MemoryToPeripheral> for Tx<SPI6>
impl DMASet<StreamX<DMA2, 5_u8>, 3_u8, MemoryToPeripheral> for SPI1
impl DMASet<StreamX<DMA2, 5_u8>, 3_u8, MemoryToPeripheral> for Tx<SPI1>
impl DMASet<StreamX<DMA2, 5_u8>, 6_u8, MemoryToPeripheral> for DMAR<TIM1>
impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, MemoryToPeripheral> for CCR1<TIM1>
impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, MemoryToPeripheral> for CCR2<TIM1>
impl DMASet<StreamX<DMA2, 6_u8>, 0_u8, MemoryToPeripheral> for CCR3<TIM1>
impl DMASet<StreamX<DMA2, 6_u8>, 2_u8, MemoryToPeripheral> for CRYP
impl DMASet<StreamX<DMA2, 6_u8>, 4_u8, MemoryToPeripheral> for SDIO
impl DMASet<StreamX<DMA2, 6_u8>, 5_u8, MemoryToPeripheral> for USART6
impl DMASet<StreamX<DMA2, 6_u8>, 5_u8, MemoryToPeripheral> for Tx<USART6>
impl DMASet<StreamX<DMA2, 6_u8>, 6_u8, MemoryToPeripheral> for CCR3<TIM1>
impl DMASet<StreamX<DMA2, 6_u8>, 7_u8, MemoryToPeripheral> for SPI5
impl DMASet<StreamX<DMA2, 6_u8>, 7_u8, MemoryToPeripheral> for Tx<SPI5>
impl DMASet<StreamX<DMA2, 7_u8>, 2_u8, MemoryToPeripheral> for HASH
impl DMASet<StreamX<DMA2, 7_u8>, 4_u8, MemoryToPeripheral> for USART1
impl DMASet<StreamX<DMA2, 7_u8>, 4_u8, MemoryToPeripheral> for Tx<USART1>
impl DMASet<StreamX<DMA2, 7_u8>, 5_u8, MemoryToPeripheral> for USART6
impl DMASet<StreamX<DMA2, 7_u8>, 5_u8, MemoryToPeripheral> for Tx<USART6>
impl DMASet<StreamX<DMA2, 7_u8>, 7_u8, MemoryToPeripheral> for CCR4<TIM8>
impl DMASet<StreamX<DMA2, 7_u8>, 7_u8, MemoryToPeripheral> for DMAR<TIM8>
Auto Trait Implementations
impl RefUnwindSafe for MemoryToPeripheral
impl Send for MemoryToPeripheral
impl Sync for MemoryToPeripheral
impl Unpin for MemoryToPeripheral
impl UnwindSafe for MemoryToPeripheral
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more