Struct stm32f469xx::dma2::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 52 fields
    pub lisr: LISR,
    pub hisr: HISR,
    pub lifcr: LIFCR,
    pub hifcr: HIFCR,
    pub s0cr: S0CR,
    pub s0ndtr: S0NDTR,
    pub s0par: S0PAR,
    pub s0m0ar: S0M0AR,
    pub s0m1ar: S0M1AR,
    pub s0fcr: S0FCR,
    pub s1cr: S1CR,
    pub s1ndtr: S1NDTR,
    pub s1par: S1PAR,
    pub s1m0ar: S1M0AR,
    pub s1m1ar: S1M1AR,
    pub s1fcr: S1FCR,
    pub s2cr: S2CR,
    pub s2ndtr: S2NDTR,
    pub s2par: S2PAR,
    pub s2m0ar: S2M0AR,
    pub s2m1ar: S2M1AR,
    pub s2fcr: S2FCR,
    pub s3cr: S3CR,
    pub s3ndtr: S3NDTR,
    pub s3par: S3PAR,
    pub s3m0ar: S3M0AR,
    pub s3m1ar: S3M1AR,
    pub s3fcr: S3FCR,
    pub s4cr: S4CR,
    pub s4ndtr: S4NDTR,
    pub s4par: S4PAR,
    pub s4m0ar: S4M0AR,
    pub s4m1ar: S4M1AR,
    pub s4fcr: S4FCR,
    pub s5cr: S5CR,
    pub s5ndtr: S5NDTR,
    pub s5par: S5PAR,
    pub s5m0ar: S5M0AR,
    pub s5m1ar: S5M1AR,
    pub s5fcr: S5FCR,
    pub s6cr: S6CR,
    pub s6ndtr: S6NDTR,
    pub s6par: S6PAR,
    pub s6m0ar: S6M0AR,
    pub s6m1ar: S6M1AR,
    pub s6fcr: S6FCR,
    pub s7cr: S7CR,
    pub s7ndtr: S7NDTR,
    pub s7par: S7PAR,
    pub s7m0ar: S7M0AR,
    pub s7m1ar: S7M1AR,
    pub s7fcr: S7FCR,

}
Expand description

Register block

Fields§

§lisr: LISR

0x00 - low interrupt status register

§hisr: HISR

0x04 - high interrupt status register

§lifcr: LIFCR

0x08 - low interrupt flag clear register

§hifcr: HIFCR

0x0c - high interrupt flag clear register

§s0cr: S0CR

0x10 - stream x configuration register

§s0ndtr: S0NDTR

0x14 - stream x number of data register

§s0par: S0PAR

0x18 - stream x peripheral address register

§s0m0ar: S0M0AR

0x1c - stream x memory 0 address register

§s0m1ar: S0M1AR

0x20 - stream x memory 1 address register

§s0fcr: S0FCR

0x24 - stream x FIFO control register

§s1cr: S1CR

0x28 - stream x configuration register

§s1ndtr: S1NDTR

0x2c - stream x number of data register

§s1par: S1PAR

0x30 - stream x peripheral address register

§s1m0ar: S1M0AR

0x34 - stream x memory 0 address register

§s1m1ar: S1M1AR

0x38 - stream x memory 1 address register

§s1fcr: S1FCR

0x3c - stream x FIFO control register

§s2cr: S2CR

0x40 - stream x configuration register

§s2ndtr: S2NDTR

0x44 - stream x number of data register

§s2par: S2PAR

0x48 - stream x peripheral address register

§s2m0ar: S2M0AR

0x4c - stream x memory 0 address register

§s2m1ar: S2M1AR

0x50 - stream x memory 1 address register

§s2fcr: S2FCR

0x54 - stream x FIFO control register

§s3cr: S3CR

0x58 - stream x configuration register

§s3ndtr: S3NDTR

0x5c - stream x number of data register

§s3par: S3PAR

0x60 - stream x peripheral address register

§s3m0ar: S3M0AR

0x64 - stream x memory 0 address register

§s3m1ar: S3M1AR

0x68 - stream x memory 1 address register

§s3fcr: S3FCR

0x6c - stream x FIFO control register

§s4cr: S4CR

0x70 - stream x configuration register

§s4ndtr: S4NDTR

0x74 - stream x number of data register

§s4par: S4PAR

0x78 - stream x peripheral address register

§s4m0ar: S4M0AR

0x7c - stream x memory 0 address register

§s4m1ar: S4M1AR

0x80 - stream x memory 1 address register

§s4fcr: S4FCR

0x84 - stream x FIFO control register

§s5cr: S5CR

0x88 - stream x configuration register

§s5ndtr: S5NDTR

0x8c - stream x number of data register

§s5par: S5PAR

0x90 - stream x peripheral address register

§s5m0ar: S5M0AR

0x94 - stream x memory 0 address register

§s5m1ar: S5M1AR

0x98 - stream x memory 1 address register

§s5fcr: S5FCR

0x9c - stream x FIFO control register

§s6cr: S6CR

0xa0 - stream x configuration register

§s6ndtr: S6NDTR

0xa4 - stream x number of data register

§s6par: S6PAR

0xa8 - stream x peripheral address register

§s6m0ar: S6M0AR

0xac - stream x memory 0 address register

§s6m1ar: S6M1AR

0xb0 - stream x memory 1 address register

§s6fcr: S6FCR

0xb4 - stream x FIFO control register

§s7cr: S7CR

0xb8 - stream x configuration register

§s7ndtr: S7NDTR

0xbc - stream x number of data register

§s7par: S7PAR

0xc0 - stream x peripheral address register

§s7m0ar: S7M0AR

0xc4 - stream x memory 0 address register

§s7m1ar: S7M1AR

0xc8 - stream x memory 1 address register

§s7fcr: S7FCR

0xcc - stream x FIFO control register

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