Struct stm32f469xx::dsihost::dsi_wpcr1::R

pub struct R { /* private fields */ }

Value read from the register

Implementations

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn tclkposten(&self) -> TCLKPOSTENR

Bit 27 - custom time for tCLK-POST Enable

pub fn tlpxcen(&self) -> TLPXCENR

Bit 26 - custom time for tLPX for Clock lane Enable

pub fn thsexiten(&self) -> THSEXITENR

Bit 25 - custom time for tHS-EXIT Enable

pub fn tlpxden(&self) -> TLPXDENR

Bit 24 - custom time for tLPX for Data lanes Enable

pub fn thszeroen(&self) -> THSZEROENR

Bit 23 - custom time for tHS-ZERO Enable

pub fn thstrailen(&self) -> THSTRAILENR

Bit 22 - custom time for tHS-TRAIL Enable

pub fn thsprepen(&self) -> THSPREPENR

Bit 21 - custom time for tHS-PREPARE Enable

pub fn tclkzeroen(&self) -> TCLKZEROENR

Bit 20 - custom time for tCLK-ZERO Enable

pub fn tclkprepen(&self) -> TCLKPREPENR

Bit 19 - custom time for tCLK-PREPARE Enable

pub fn pden(&self) -> PDENR

Bit 18 - Pull-Down Enable

pub fn tddl(&self) -> TDDLR

Bit 16 - Turn Disable Data Lanes

pub fn cdoffdl(&self) -> CDOFFDLR

Bit 14 - Contention Detection OFF on Data Lanes

pub fn ftxsmdl(&self) -> FTXSMDLR

Bit 13 - Force in TX Stop Mode the Data Lanes

pub fn ftxsmcl(&self) -> FTXSMCLR

Bit 12 - Force in TX Stop Mode the Clock Lane

pub fn hsidl1(&self) -> HSIDL1R

Bit 11 - Invert the High-Speed data signal on Data Lane 1

pub fn hsidl0(&self) -> HSIDL0R

Bit 10 - Invert the Hight-Speed data signal on Data Lane 0

pub fn hsicl(&self) -> HSICLR

Bit 9 - Invert Hight-Speed data signal on Clock Lane

pub fn swdl1(&self) -> SWDL1R

Bit 8 - Swap Data Lane 1 pins

pub fn swdl0(&self) -> SWDL0R

Bit 7 - Swap Data Lane 0 pins

pub fn swcl(&self) -> SWCLR

Bit 6 - Swap Clock Lane pins

pub fn uix4(&self) -> UIX4R

Bits 0:5 - Unit Interval multiplied by 4