Module stm32f429_hal::i2s
[−]
[src]
I2S bus
Structs
| DmaRx |
Rx direction |
| DmaTx |
Tx direction |
| I2s |
I2S peripheral |
| I2sOutput |
I2S peripheral |
| MasterRole |
Master role (provides clock) |
| SlaveRole |
Slave role (doesn't provide clock) |
Enums
| I2sStandard |
I2S standard |
Traits
| CkPin |
CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode and serial clock input in slave mode. |
| ExtSdPin |
SPI2ext_SD and SPI3ext_SD: additional pins (mapped on the MISO pin) to control the I 2 S full duplex mode. |
| I2sData |
Implemented by data types that fit the device's data width: |
| I2sDmaStream |
Possible DMA configuration for an SPI device |
| MckPin |
MCK: Master Clock (mapped separately) is used, when the I 2 S is configured in master mode (and when the MCKOE bit in the SPI_I2SPR register is set), to output this additional clock generated at a preconfigured frequency rate equal to 256 × F S , where F S is the audio sampling frequency. |
| SdPin |
SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time- multiplexed data channels (in half-duplex mode only). |
| WsPin |
WS: Word Select (mapped on the NSS pin) is the data control signal output in master mode and input in slave mode. |