Struct stm32f41x::dma2::lifcr::R
[−]
[src]
pub struct R { /* fields omitted */ }
Value read from the register
Methods
impl R
[src]
fn bits(&self) -> u32
Value of the register as raw bits
fn ctcif3(&self) -> CTCIF3R
Bit 27 - Stream x clear transfer complete interrupt flag (x = 3..0)
fn chtif3(&self) -> CHTIF3R
Bit 26 - Stream x clear half transfer interrupt flag (x = 3..0)
fn cteif3(&self) -> CTEIF3R
Bit 25 - Stream x clear transfer error interrupt flag (x = 3..0)
fn cdmeif3(&self) -> CDMEIF3R
Bit 24 - Stream x clear direct mode error interrupt flag (x = 3..0)
fn cfeif3(&self) -> CFEIF3R
Bit 22 - Stream x clear FIFO error interrupt flag (x = 3..0)
fn ctcif2(&self) -> CTCIF2R
Bit 21 - Stream x clear transfer complete interrupt flag (x = 3..0)
fn chtif2(&self) -> CHTIF2R
Bit 20 - Stream x clear half transfer interrupt flag (x = 3..0)
fn cteif2(&self) -> CTEIF2R
Bit 19 - Stream x clear transfer error interrupt flag (x = 3..0)
fn cdmeif2(&self) -> CDMEIF2R
Bit 18 - Stream x clear direct mode error interrupt flag (x = 3..0)
fn cfeif2(&self) -> CFEIF2R
Bit 16 - Stream x clear FIFO error interrupt flag (x = 3..0)
fn ctcif1(&self) -> CTCIF1R
Bit 11 - Stream x clear transfer complete interrupt flag (x = 3..0)
fn chtif1(&self) -> CHTIF1R
Bit 10 - Stream x clear half transfer interrupt flag (x = 3..0)
fn cteif1(&self) -> CTEIF1R
Bit 9 - Stream x clear transfer error interrupt flag (x = 3..0)
fn cdmeif1(&self) -> CDMEIF1R
Bit 8 - Stream x clear direct mode error interrupt flag (x = 3..0)
fn cfeif1(&self) -> CFEIF1R
Bit 6 - Stream x clear FIFO error interrupt flag (x = 3..0)
fn ctcif0(&self) -> CTCIF0R
Bit 5 - Stream x clear transfer complete interrupt flag (x = 3..0)
fn chtif0(&self) -> CHTIF0R
Bit 4 - Stream x clear half transfer interrupt flag (x = 3..0)
fn cteif0(&self) -> CTEIF0R
Bit 3 - Stream x clear transfer error interrupt flag (x = 3..0)
fn cdmeif0(&self) -> CDMEIF0R
Bit 2 - Stream x clear direct mode error interrupt flag (x = 3..0)
fn cfeif0(&self) -> CFEIF0R
Bit 0 - Stream x clear FIFO error interrupt flag (x = 3..0)