Struct stm32f40x::dma2::s1cr::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
fn bits(&self) -> u32[src]
Value of the register as raw bits
fn chsel(&self) -> CHSELR[src]
Bits 25:27 - Channel selection
fn mburst(&self) -> MBURSTR[src]
Bits 23:24 - Memory burst transfer configuration
fn pburst(&self) -> PBURSTR[src]
Bits 21:22 - Peripheral burst transfer configuration
fn ack(&self) -> ACKR[src]
Bit 20 - ACK
fn ct(&self) -> CTR[src]
Bit 19 - Current target(only in double buffer mode)
fn dbm(&self) -> DBMR[src]
Bit 18 - Double buffer mode
fn pl(&self) -> PLR[src]
Bits 16:17 - Priority level
fn pincos(&self) -> PINCOSR[src]
Bit 15 - Peripheral increment offset size
fn msize(&self) -> MSIZER[src]
Bits 13:14 - Memory data size
fn psize(&self) -> PSIZER[src]
Bits 11:12 - Peripheral data size
fn minc(&self) -> MINCR[src]
Bit 10 - Memory increment mode
fn pinc(&self) -> PINCR[src]
Bit 9 - Peripheral increment mode
fn circ(&self) -> CIRCR[src]
Bit 8 - Circular mode
fn dir(&self) -> DIRR[src]
Bits 6:7 - Data transfer direction
fn pfctrl(&self) -> PFCTRLR[src]
Bit 5 - Peripheral flow controller
fn tcie(&self) -> TCIER[src]
Bit 4 - Transfer complete interrupt enable
fn htie(&self) -> HTIER[src]
Bit 3 - Half transfer interrupt enable
fn teie(&self) -> TEIER[src]
Bit 2 - Transfer error interrupt enable
fn dmeie(&self) -> DMEIER[src]
Bit 1 - Direct mode error interrupt enable
fn en(&self) -> ENR[src]
Bit 0 - Stream enable / flag stream ready when read low