Struct stm32f40x::dma2::hisr::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
fn bits(&self) -> u32[src]
Value of the register as raw bits
fn tcif7(&self) -> TCIF7R[src]
Bit 27 - Stream x transfer complete interrupt flag(x=7..4)
fn htif7(&self) -> HTIF7R[src]
Bit 26 - Stream x half transfer interrupt flag(x=7..4)
fn teif7(&self) -> TEIF7R[src]
Bit 25 - Stream x transfer error interrupt flag(x=7..4)
fn dmeif7(&self) -> DMEIF7R[src]
Bit 24 - Stream x direct mode error interrupt flag(x=7..4)
fn feif7(&self) -> FEIF7R[src]
Bit 22 - Stream x FIFO error interrupt flag(x=7..4)
fn tcif6(&self) -> TCIF6R[src]
Bit 21 - Stream x transfer complete interrupt flag(x=7..4)
fn htif6(&self) -> HTIF6R[src]
Bit 20 - Stream x half transfer interrupt flag(x=7..4)
fn teif6(&self) -> TEIF6R[src]
Bit 19 - Stream x transfer error interrupt flag(x=7..4)
fn dmeif6(&self) -> DMEIF6R[src]
Bit 18 - Stream x direct mode error interrupt flag(x=7..4)
fn feif6(&self) -> FEIF6R[src]
Bit 16 - Stream x FIFO error interrupt flag(x=7..4)
fn tcif5(&self) -> TCIF5R[src]
Bit 11 - Stream x transfer complete interrupt flag(x=7..4)
fn htif5(&self) -> HTIF5R[src]
Bit 10 - Stream x half transfer interrupt flag(x=7..4)
fn teif5(&self) -> TEIF5R[src]
Bit 9 - Stream x transfer error interrupt flag(x=7..4)
fn dmeif5(&self) -> DMEIF5R[src]
Bit 8 - Stream x direct mode error interrupt flag(x=7..4)
fn feif5(&self) -> FEIF5R[src]
Bit 6 - Stream x FIFO error interrupt flag(x=7..4)
fn tcif4(&self) -> TCIF4R[src]
Bit 5 - Stream x transfer complete interrupt flag(x=7..4)
fn htif4(&self) -> HTIF4R[src]
Bit 4 - Stream x half transfer interrupt flag(x=7..4)
fn teif4(&self) -> TEIF4R[src]
Bit 3 - Stream x transfer error interrupt flag(x=7..4)
fn dmeif4(&self) -> DMEIF4R[src]
Bit 2 - Stream x direct mode error interrupt flag(x=7..4)
fn feif4(&self) -> FEIF4R[src]
Bit 0 - Stream x FIFO error interrupt flag(x=7..4)