Enum stm32f407g_disc::tim6::cr1::URSW
pub enum URSW {
ANYEVENT,
COUNTERONLY,
}
Expand description
Values that can be written to the field URS
Variants§
ANYEVENT
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
COUNTERONLY
Only counter overflow/underflow generates an update interrupt or DMA request