Enum stm32f407g_disc::tim10::cr1::URSR
pub enum URSR {
ANYEVENT,
COUNTERONLY,
}
Expand description
Possible values of the field URS
Variants§
ANYEVENT
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
COUNTERONLY
Only counter overflow/underflow generates an update interrupt or DMA request
Implementations§
§impl URSR
impl URSR
pub fn bit_is_clear(&self) -> bool
pub fn bit_is_clear(&self) -> bool
Returns true
if the bit is clear (0)
pub fn bit_is_set(&self) -> bool
pub fn bit_is_set(&self) -> bool
Returns true
if the bit is set (1)
pub fn is_any_event(&self) -> bool
pub fn is_any_event(&self) -> bool
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool
pub fn is_counter_only(&self) -> bool
Checks if the value of the field is COUNTERONLY