Struct stm32f407::rcc::RegisterBlock [−] [src]

#[repr(C)]

pub struct RegisterBlock {
    pub cr: CR,
    pub pllcfgr: PLLCFGR,
    pub cfgr: CFGR,
    pub cir: CIR,
    pub ahb1rstr: AHB1RSTR,
    pub ahb2rstr: AHB2RSTR,
    pub ahb3rstr: AHB3RSTR,
    pub apb1rstr: APB1RSTR,
    pub apb2rstr: APB2RSTR,
    pub ahb1enr: AHB1ENR,
    pub ahb2enr: AHB2ENR,
    pub ahb3enr: AHB3ENR,
    pub apb1enr: APB1ENR,
    pub apb2enr: APB2ENR,
    pub ahb1lpenr: AHB1LPENR,
    pub ahb2lpenr: AHB2LPENR,
    pub ahb3lpenr: AHB3LPENR,
    pub apb1lpenr: APB1LPENR,
    pub apb2lpenr: APB2LPENR,
    pub bdcr: BDCR,
    pub csr: CSR,
    pub sscgr: SSCGR,
    pub plli2scfgr: PLLI2SCFGR,
    // some fields omitted
}

Register block

Fields

0x00 - clock control register

0x04 - PLL configuration register

0x08 - clock configuration register

0x0c - clock interrupt register

0x10 - AHB1 peripheral reset register

0x14 - AHB2 peripheral reset register

0x18 - AHB3 peripheral reset register

0x20 - APB1 peripheral reset register

0x24 - APB2 peripheral reset register

0x30 - AHB1 peripheral clock register

0x34 - AHB2 peripheral clock enable register

0x38 - AHB3 peripheral clock enable register

0x40 - APB1 peripheral clock enable register

0x44 - APB2 peripheral clock enable register

0x50 - AHB1 peripheral clock enable in low power mode register

0x54 - AHB2 peripheral clock enable in low power mode register

0x58 - AHB3 peripheral clock enable in low power mode register

0x60 - APB1 peripheral clock enable in low power mode register

0x64 - APB2 peripheral clock enabled in low power mode register

0x70 - Backup domain control register

0x74 - clock control & status register

0x80 - spread spectrum clock generation register

0x84 - PLLI2S configuration register