stm32f4/stm32f469/spi1/
i2spr.rs

1///Register `I2SPR` reader
2pub type R = crate::R<I2SPRrs>;
3///Register `I2SPR` writer
4pub type W = crate::W<I2SPRrs>;
5///Field `I2SDIV` reader - I2S Linear prescaler
6pub type I2SDIV_R = crate::FieldReader;
7///Field `I2SDIV` writer - I2S Linear prescaler
8pub type I2SDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9/**Odd factor for the prescaler
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum ODD {
15    ///0: Real divider value is I2SDIV * 2
16    Even = 0,
17    ///1: Real divider value is (I2SDIV * 2) + 1
18    Odd = 1,
19}
20impl From<ODD> for bool {
21    #[inline(always)]
22    fn from(variant: ODD) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `ODD` reader - Odd factor for the prescaler
27pub type ODD_R = crate::BitReader<ODD>;
28impl ODD_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> ODD {
32        match self.bits {
33            false => ODD::Even,
34            true => ODD::Odd,
35        }
36    }
37    ///Real divider value is I2SDIV * 2
38    #[inline(always)]
39    pub fn is_even(&self) -> bool {
40        *self == ODD::Even
41    }
42    ///Real divider value is (I2SDIV * 2) + 1
43    #[inline(always)]
44    pub fn is_odd(&self) -> bool {
45        *self == ODD::Odd
46    }
47}
48///Field `ODD` writer - Odd factor for the prescaler
49pub type ODD_W<'a, REG> = crate::BitWriter<'a, REG, ODD>;
50impl<'a, REG> ODD_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///Real divider value is I2SDIV * 2
55    #[inline(always)]
56    pub fn even(self) -> &'a mut crate::W<REG> {
57        self.variant(ODD::Even)
58    }
59    ///Real divider value is (I2SDIV * 2) + 1
60    #[inline(always)]
61    pub fn odd(self) -> &'a mut crate::W<REG> {
62        self.variant(ODD::Odd)
63    }
64}
65/**Master clock output enable
66
67Value on reset: 0*/
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum MCKOE {
71    ///0: Master clock output is disabled
72    Disabled = 0,
73    ///1: Master clock output is enabled
74    Enabled = 1,
75}
76impl From<MCKOE> for bool {
77    #[inline(always)]
78    fn from(variant: MCKOE) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `MCKOE` reader - Master clock output enable
83pub type MCKOE_R = crate::BitReader<MCKOE>;
84impl MCKOE_R {
85    ///Get enumerated values variant
86    #[inline(always)]
87    pub const fn variant(&self) -> MCKOE {
88        match self.bits {
89            false => MCKOE::Disabled,
90            true => MCKOE::Enabled,
91        }
92    }
93    ///Master clock output is disabled
94    #[inline(always)]
95    pub fn is_disabled(&self) -> bool {
96        *self == MCKOE::Disabled
97    }
98    ///Master clock output is enabled
99    #[inline(always)]
100    pub fn is_enabled(&self) -> bool {
101        *self == MCKOE::Enabled
102    }
103}
104///Field `MCKOE` writer - Master clock output enable
105pub type MCKOE_W<'a, REG> = crate::BitWriter<'a, REG, MCKOE>;
106impl<'a, REG> MCKOE_W<'a, REG>
107where
108    REG: crate::Writable + crate::RegisterSpec,
109{
110    ///Master clock output is disabled
111    #[inline(always)]
112    pub fn disabled(self) -> &'a mut crate::W<REG> {
113        self.variant(MCKOE::Disabled)
114    }
115    ///Master clock output is enabled
116    #[inline(always)]
117    pub fn enabled(self) -> &'a mut crate::W<REG> {
118        self.variant(MCKOE::Enabled)
119    }
120}
121impl R {
122    ///Bits 0:7 - I2S Linear prescaler
123    #[inline(always)]
124    pub fn i2sdiv(&self) -> I2SDIV_R {
125        I2SDIV_R::new((self.bits & 0xff) as u8)
126    }
127    ///Bit 8 - Odd factor for the prescaler
128    #[inline(always)]
129    pub fn odd(&self) -> ODD_R {
130        ODD_R::new(((self.bits >> 8) & 1) != 0)
131    }
132    ///Bit 9 - Master clock output enable
133    #[inline(always)]
134    pub fn mckoe(&self) -> MCKOE_R {
135        MCKOE_R::new(((self.bits >> 9) & 1) != 0)
136    }
137}
138impl core::fmt::Debug for R {
139    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
140        f.debug_struct("I2SPR")
141            .field("mckoe", &self.mckoe())
142            .field("odd", &self.odd())
143            .field("i2sdiv", &self.i2sdiv())
144            .finish()
145    }
146}
147impl W {
148    ///Bits 0:7 - I2S Linear prescaler
149    #[inline(always)]
150    pub fn i2sdiv(&mut self) -> I2SDIV_W<I2SPRrs> {
151        I2SDIV_W::new(self, 0)
152    }
153    ///Bit 8 - Odd factor for the prescaler
154    #[inline(always)]
155    pub fn odd(&mut self) -> ODD_W<I2SPRrs> {
156        ODD_W::new(self, 8)
157    }
158    ///Bit 9 - Master clock output enable
159    #[inline(always)]
160    pub fn mckoe(&mut self) -> MCKOE_W<I2SPRrs> {
161        MCKOE_W::new(self, 9)
162    }
163}
164/**I2S prescaler register
165
166You can [`read`](crate::Reg::read) this register and get [`i2spr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2spr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SPI1:I2SPR)*/
169pub struct I2SPRrs;
170impl crate::RegisterSpec for I2SPRrs {
171    type Ux = u16;
172}
173///`read()` method returns [`i2spr::R`](R) reader structure
174impl crate::Readable for I2SPRrs {}
175///`write(|w| ..)` method takes [`i2spr::W`](W) writer structure
176impl crate::Writable for I2SPRrs {
177    type Safety = crate::Unsafe;
178}
179///`reset()` method sets I2SPR to value 0x0a
180impl crate::Resettable for I2SPRrs {
181    const RESET_VALUE: u16 = 0x0a;
182}
stm32f4/stm32f469/spi1/i2spr.rs

stm32f4/stm32f469/spi1/
i2spr.rs
